Microprocessor Fundamentals Course

The International Congress for global Science and Technology www.icgst.com Instructor: Ashraf Aboshosha, Dr. rer. nat. Engineering Dept., Atomic Energy Authority, 8th Section, Nasr City, Cairo, P.O. Box. 29 E-mail: aboshosha@icgst.com, Tel.: 012-1804952

Lecture (3): Microprocessor Architecture

Course Syllabus:

Computer Architecture Microprocessor structure and Design Microprocessor programming and operation Microprocessor based Interfacing

This is free educational material.

Microprocessor Architecture Introduction

The basic function of a p is to fetch, decode and execute instructions held in ROM or RAM. To accomplish this it must fetch data from an external memory source and transfer it into its own internal memory, each addressable component of which is called a register. It must also be able to distinguish between instructions and operands, that is, the. read/write memory locations containing the data to be operated on. These may be byte addressable location in ROM, RAM or in the ps own registers. In addition, the p must perform additional tasks such as responding to external events such as resets and interrupts, provide memory management facilities to the operating system, etc. A consideration of the fundamental components in a basic microprocessor is first undertaken before introducing more complex modern devices. Figure 1 illustrates a typical 80C186 Family p architecture

Figure 1. Simplified Functional Block Diagram of the 80C186 Family CPU

80C186 Family Execution Unit The Execution Unit executes all instructions, provides data and addresses to the Bus Interface Unit and manipulates the general registers and the Processor Status Word. The 16-bit ALU within the Execution Unit maintains the p status and control flags and manipulates the general registers and instruction operands. All registers and data paths in the Execution Unit are 16 bits wide for fast internal transfers. The Execution Unit does not connect directly to the system bus. It obtains instructions from a queue maintained by the Bus Interface Unit. When an instruction requires access to memory or a peripheral device, the Execution Unit requests the Bus Interface Unit to read and write data. Addresses manipulated by the Execution Unit are 16 bits wide. The Bus Interface Unit, however, performs an address calculation that allows the Execution Unit to access the full megabyte of memory space.

To execute an instruction, the Execution Unit must first fetch the object code byte from the instruction queue and then execute the instruction. If the queue is empty when the Execution Unit is ready to fetch an instruction byte, the Execution Unit waits for the Bus Interface Unit to fetch the instruction byte. 80C186 Family Bus Interface Unit The 80C186 family Bus Interface Units are functionally identical. They are implemented differently to match the structure and performance characteristics of their respective system buses. The Bus Interface Unit executes all external bus cycles. This unit consists of the segment registers, the Instruction Pointer, the instruction code queue and several miscellaneous registers. The Bus Interface Unit transfers data to and from the Execution Unit on the ALU data bus. Registers Registers for a variety of purposes such as holding the address of instructions and data, storing the result of an operation, signaling the result of a logic operation, or indicating the status of the program or the p itself. Some registers may be accessible to programmers, while others are reserved for us by the p itself. Registers store binary values such as 1 or 0 as electrical voltages of say 5 volts or 0 volts. They consist of several integrated transistors which are configured as a flip-flop circuits each of which can be switched into a 1 or 0 state. They remain in that state until changed under control of the p or until the power is removed from the processor. Each register has a specific name and is addressable, some, however, are dedicated to specific tasks while the majority are general purpose. The width of a register depends on the type of p, e.g., an 16, 32 or 64 bit microprocessor. In order to provide backward compatibility, registers may be sub-divided. For example, the Pentium processor is a 32 bit CPU, and its registers are 32 bits wide. Some of these are sub-divided and named as 8 and 16 bit registers in order to run 8 and 16 bit applications designed for earlier x86 microprocessors. Instruction Register When the Bus Interface Unit receives an instruction it transfers it to the Instruction Register for temporary storage. In Pentium processors the Bus Interface Unit transfers instructions to the L1 I-Cache, there is no instruction register as such. Stack Pointer A stack is a small area of reserved memory used to store the data in the ps registers when: (1) system calls are made by a process to operating system routines; (2) when hardware interrupts generated by input/output (I/O) transactions on peripheral devices; (3) when a process initiates an I/O transfer; (3) when a process rescheduling event occurs on foot of a hardware timer interrupt. This transfer of register contents is called a context switch. The stack pointer is the register which holds the address of the most recent stack entry. Hence, when a system call is made by a process (to say print a document) and its context is stored on the stack, the called system routine uses the stack pointer to reload the register contents when it is finished printing. Thus the process can continue where it left off. 80C186 Family General Registers The 80C186 family CPU has eight 16-bit general registers (see Figure 2). The general registers are subdivided into two sets of four registers. These sets are the data registers (also called the H & L group for high and low) and the pointer and index registers (also called the P & I group). 3

Figure 2. 80C186 Family General Registers

The data registers can be addressed by their upper or lower halves. Each data register can be used interchangeably as a 16-bit register or two 8-bit registers. The pointer registers are always accessed as 16-bit values. The p can use data registers without constraint in most arithmetic and logic operations. Arithmetic and logic operations can also use the pointer and index registers. Some instructions use certain registers implicitly (see Table 1), allowing compact encoding.
Table 1. Implicit Use of General Registers

Register AX AL AH BX CX CL DX SP SI DI

Operations Word Multiply, Word Divide, Word I/O Byte Multiply, Byte Divide, Byte I/O, Translate, Decimal Arithmetic Byte Multiply, Byte Divide Translate String Operations, Loops Variable Shift and Rotate Word Multiply, Word Divide, Indirect I/O Stack Operations String Operations String Operations

The contents of the general-purpose registers are undefined following a processor reset.

Instruction Decoder The Instruction Decoder is an arrangement of logic elements which act on the bits that constitute the instruction. Simple instructions with corresponding logic hard-wired into the execution unit are simply passed to the Execution Unit, complex instructions are decoded so that related microcode modules can be transferred from the ps microcode ROM to the execution unit. The Instruction Decoder will also store referenced operands in appropriate registers so data at the memory locations referenced can be fetched. Accumulator The accumulator may contain data to be used in a mathematical or logical operation, or it may contain the result of an operation. General purpose registers are used to support the accumulator by holding data to be loaded to/from the accumulator. Computer Status (Flag) Register The result of an ALU operation may have consequences of subsequent operations; for example, changing the path of execution. Individual bits in this register are set or reset in accordance with the result of mathematical or logical operations. Also called a flag, each bit in the register has a pre-assigned meaning and the contents are monitored by the control unit to help control p related actions. Bits in FL reflect ALU status and p (interrupt) status e.g. Negative (N), Zero (Z), Carry (C), Parity Flag (PF), Overflow (V), Interrupt (IF), Trap (TF). 80C186 Family Flags The 80C186 family has six status flags (see Figure 3) that the Execution Unit posts as the result of arithmetic or logical operations. Program branch instructions allow a program to alter its execution depending on conditions flagged by a prior operation. Different instructions affect the status flags differently, generally reflecting the following states: If the Auxiliary Flag (AF) is set, there has been a carry out from the low nibble into the high nibble or a borrow from the high nibble into the low nibble of an 8-bit uantity (low-order byte of a 16-bit quantity). This flag is used by decimal arithmetic instructions. If the Carry Flag (CF) is set, there has been a carry out of or a borrow into the highorder bit of the instruction result (8- or 16-bit). This flag is used by instructions that add or subtract multibyte numbers. Rotate instructions can also isolate a bit in memory or a register by placing it in the Carry Flag. If the Overflow Flag (OF) is set, an arithmetic overflow has occurred. A significant digit has been lost because the size of the result exceeded the capacity of its destination location. An Interrupt On Overflow instruction is available that will generate an interrupt in this situation. If the Sign Flag (SF) is set, the high-order bit of the result is a 1. Since negative binary numbers are represented in standard twos complement notation, SF indicates the sign of the result (0 = positive, 1 = negative). If the Parity Flag (PF) is set, the result has even parity, an even number of 1 bits. This flag can be used to check for data transmission errors. If the Zero Flag (ZF) is set, the result of the operation is zero. Additional control flags (see Figure 3) can be set or cleared by programs to alter processor operations: Setting the Direction Flag (DF) causes string operations to auto-decrement. Strings are processed from high address to low address (or right to left). Clearing DF causes 5

string operations to auto-increment. Strings are processed from low address to high address (or left to right). Setting the Interrupt Enable Flag (IF) allows the p to recognize maskable external or internal interrupt requests. Clearing IF disables these interrupts. The Interrupt Enable Flag has no effect on software interrupts or non-maskable interrupts. Setting the Trap Flag (TF) bit puts the processor into single-step mode for debugging. In this mode, the CPU automatically generates an interrupt after each instruction. This allows a program to be inspected instruction by instruction during execution.

The status and control flags are contained in a 16-bit Processor Status Word (see Figure 3). Reset initializes the Processor Status Word to 0F000H.

Figure 3. 80C186 Family Processor Status Word 80C186 Family Segment Registers The 80C186 family memory space is 1 Mbyte in size and divided into logical segments of up to 64 Kbytes each. The CPU has direct access to four segments at a time. The segment registers contain the base addresses (starting locations) of these memory segments (see Figure 4). The CS register points to the current code segment, which contains instructions to be fetched. The SS register points to the current stack segment, which is used for all stack 6

operations. The DS register points to the current data segment, which generally contains program variables. The ES register points to the current extra segment, which is typically used for data storage. The CS register initializes to 0FFFFH, and the SS, DS and ES registers initialize to 0000H. Programs can access and manipulate the segment registers with several instructions.

Figure 4. 80C186 Family Segment Register Program or Instruction Counter The Program Counter (PC) is the register that stores the address in primary memory (RAM or ROM) of the next instruction to be executed. In 32 bit systems, this is a 32 bit linear or virtual memory address that references a byte (the first of 4 required to store the 32 bit instruction) in the processs virtual memory address space. This value is translated to determine the real memory address in which the instruction is stored. When the referenced instruction is fetched, the address in the PC is incremented to the address of the next instruction to be executed. If the current address is 00B0 hex, then the next address will be 00B4 hex. Remember each byte in RAM is individually addressable, however each complete instruction is 32 bits or 4 bytes, and the address of the next instruction in the process will be 4 bytes on. 80C186 Family Instruction Pointer The Bus Interface Unit updates the 16-bit Instruction Pointer (IP) register so it contains the offset of the next instruction to be fetched. Programs do not have direct access to the Instruction Pointer, but it can change, be saved or be restored as a result of program execution. For example, if the Instruction Pointer is saved on the stack, it is first automatically adjusted to point to the next instruction to be executed. Reset initializes the Instruction Pointer to 0000H. The CS and IP values comprise a starting execution address of 0FFFF0H.

Arithmetic and Logic Unit The Arithmetic and Logic Unit (ALU) performs all arithmetic and logic operations in a microprocessor e.g. addition, subtraction, logical AND, OR, EX-OR, etc.. A typical ALU is connected to accumulator and general purpose registers and other p components that help transfer the result of its operations to RAM via the Bus Interface Unit and the system bus. The results may also be written into internal or external caches. Control Unit The control unit coordinates and manages p activities, in particular the execution of instructions by the arithmetic and logic unit (ALU). In Pentium processors its role is complex, as microcode from decoded instructions are pipelined for execution by two ALUs.

The System Clock The Intel 8088 had a clock speed of 4.77 Mhz; that is, its internal logic gates were opened and closed under the control of a square wave pulsed signal that had a frequency of 4.77 million cycles per second. Alternatively put, the logic gates opened and closed 4.77 million times per second. Thus, instructions and data were pumped through the integrated transistor logic circuits at a rate of 4.77 million bits per second. Later designs ran at higher speeds e.g. the i286 8-20 Mhz, the i386 16-33 Mhz, i486 25-50 Mhz. Where does this clock signal come from? Each motherboard is fitted with a quartz oscillator in a metal package that generates a square wave clock pulse of a certain frequency. In i8088 systems the crystal oscillator ran at 14.318 Mhz and this was fed to the i8284 to generate the system clock frequency of 4.77 Mhz in earlier system, to 10Mhz is later designs. Later, the i286 PCs had a 12 Mhz crystal which provided i82284 IC multiplier/divider with the primary clock signal. This then divided/multiplied the basic 12 Mhz to generate the system clock signal of 8-20 Mhz. With the advent of the i486DX, the system clock signal, which ran at 25 or 33 Mhz, was effectively multiplied by factors of 2 and 3 to deliver an internal p clock speed of 50, 66, 75, 100 Mhz. This approach is used in Pentium IV architectures, where the primary crystal source delivers a relatively slow 50 Mhz clock signal that is then multiplied to the system clock speed of 100133 Mhz. The internal multiplier in the Pentium then multiplies this by a factor 20+ to obtain speeds of 2Ghz and above. Instruction Cycle An instruction cycle consists of the activities required to fetch and execute an instruction. The length of time take to fetch and execute is measured in clock cycles. The p finishes the execution of an instruction it transfers the content of the program or instruction register into the Bus Interface Unit (1 clock cycle) . This is then gated onto the system address bus and the read signal is asserted on the control bus (1 clock cycle). This is a signal to the RAM controller that the value of this address is to be read from memory and loaded onto the data bus (4+ clock cycles). The instruction is read in from the data bus and decoded (2 + clock cycles. The fetch and decode activities constitute the first machine cycle of the instruction cycle. The second machine cycle begins when the instructions operand is read from RAM and ends when the instruction is executed and the result written back to memory. This will take at least another 8+ clock cycles, depending on the complexity of the instruction. Thus an instruction cycle will take at least 16 clock cycles, a considerable length of time. However, Intel made advances by super pipelining instructions, that is by interleaving fetch, decode, operand read, execute, and retire (i.e. write the result of the instruction to RAM) activities into two separate pipelines serving two ALUs. Hence, instructions are not executed sequentially, but concurrently and in parallel more about pipelining later. Microprocessor tasks Microprocessors must perform the following activities: 1. Provide temporary storage for addresses and data 2. Perform arithmetic and logic operations 3. Control and schedule all operations.

Operation of the CPU is sequential : Repeat { If (Reset) Fetch (read) the first/next instruction from memory into the IR Read operands, if required from memory or IO Execute the instruction within the microprocessor Write results, if required, to memory or IO If (Interrupt) { Execute interrupt sequence} } Exercises: Draw the diagram of the basic microprocessor architecture based on the configuration of 80C186 family Explain the sequential CPU operation What is the main role of ALU, instruction counter, flag register and control unit? Write some notes about the categories of CPU general registers