Appendix A Pipelining: Basic and Intermediate Concepts

Based on slides by David Patterson, University of California, Berkeley, Josep Torrellas and Sarita Adve, University of Illinois at UrbanaChampaign

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Outline
Key ideas and simple pipeline (Section A.1) Hazards (Sections A.2 and A.3) Structural hazards Data hazards Control hazards Exceptions (Section A.4) Multicycle operations (Section A.5)

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 An implementation technique whereby multiple instructions are overlapped in execution Takes advantage of parallelism that exists among the actions needed to execute different instructions The pipeline consists of stages; a pipe stage is called segment Each segment in the pipeline completes a different part of an instruction Different instructions execute simultaneously, each is in a different stage of the pipeline Each instruction step (executed by a pipe stage) takes a machine cycle Throughput: how often an instruction exits the pipeline = # instructions completed/machine cycle Want to balance the time needed to do the work in each stage Ideally, time per instruction = Time per instruction on unpipelined machine Number of pipe stages
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Pipelining

Pipelining a Basic RISC ISA

MIPS ISA ( Microprocessor without Interlocked Pipeline Stages ) The instruction formats are few in number with all instructions typically being one size. Only loads and stores affect memory
Base register + immediate offset = effective address

ALU operations
Two sources: two registers, or register and immediate

Branches and jumps

Comparison between a register and zero Branch address = PC + offset
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A Simple Five Stage RISC Pipeline

Pipeline Stages
IF : Instruction Fetch ID : Instruction decode, register read, branch computation EX : Instruction Execution and Effective Address computation MEM : Memory Access (for LOAD & STORE instructions) WB : Writeback (result) to a register

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Figure A.1 Simple RISC pipeline.

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Figure A.17 Nonpipelined Instruction Execution

Implementation of RISC Instructions

1. Instruction Fetch cycle (IF)
IR Mem[PC] ; IR holds the instruction NPC PC+4

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2. Instruction decode/register fetch cycle (ID)

A Regs[rs] ; decode the instruction B Regs[rt] ; in the meantime Imm sign-extend imm field of IR ; Regs A, B, Imm; ok if some of this is not needed

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3.

Execution /Effective address cycle (EX) Reg-Reg (ALU op): ALU output A op B Reg-Immed (ALU op): ALU output A op Imm memory ref: ALU output A+Imm ; compute address for LD,ST Branch: ALU output NPC+ (Imm << 2) ;address of target cond (A op 0 ) ; op = equal, From NPC = not equal

/* note: no instructions need to do 2 of these operations */ /* note: Imm has word count for branches; need to shift by 2 to get bytes to add to PC */

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4. Memory Access/Branch Completion Cycle (MEM)/* only for LD,ST,BR Memory access: LMD Mem[ALU output] ;for loads, Load data in LMD Mem[ALU output] B ; for stores

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4. Memory Access/Branch Completion Cycle (MEM)/* only for LD,ST,BR Branch if (cond) PC ALU output else PC NPC

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5. Write-back cycle (WB)

Load Instruction: Regs[rt] LMD Reg-Reg ALU instr: Regs[rd] ALU output Reg-Imm ALU instr: Regs[rt] ALU output

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5. Write-back cycle (WB)

Load Instruction: Regs[rt] LMD Reg-Reg ALU instr: Regs[rd] ALU output Reg-Imm ALU instr: Regs[rt] ALU output Branches & Stores 4 cycles Rest of ins 5 cycles Now we will try to pipeline instruction execution Note that at the end of each cycle, the data is stored in some registers (PC,LMD,Imm,A,B,). This allows other instructions to execute too.
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Time (clock cycles)

Cycle 1 Cycle 2
Reg

Cycle 3
ALU

Cycle 4 Cycle 5
DMem Reg

Cycle 6

Cycle 7

ALU

I n s t r. O r d e r

Ifetch

register file is written in first part of cycle

Ifetch Reg DMem Reg

ALU

Ifetch

Reg

DMem

Reg

ALU

Ifetch

Reg

DMem

Reg

IF1

ID1 IF2

EX1 ID2

MEM1 EX2

WB1 MEM2

register file is read in second part of cycle

WB2
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Figure A.2 The pipeline can be thought of as a series of data paths shifted in time.

Figure A.18 The data path is pipelined by adding a set of registers, one between each pair of pipe stages

Ensure instructions in different stages of the pipeline do not interfere with one another. At the end of a clock cycle all results from a stage are stored into a register that is used as input to the next stage on the next clock cycle. Carry intermediate results from one stage to another where the source and destination stages may not be directly adjacent.

Figure A.19 Events on every pipe stage of the MIPS pipeline.

Figure A.19 Events on every pipe stage of the MIPS pipeline.

Figure A.19 Events on every pipe stage of the MIPS pipeline.

Why does it work?

Use separate I and D memories (caches) Register file can be read/written in 0.5 cycles PC: incremented in IF if branch taken, in EX, add PC+ (Imm << 2) Cannot keep any state in IR need to move it to another register every cycle
pipeline registers IF/ID, ID/EX, EX/MEM, MEM/WB subsume the temp ones e.g. Destination Reg in a LD
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Control of the pipeline Set the control of the 4 MUXES

ALU stage MUXES MUX in IF MUX in WB

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MUXES set depending on instruction type which is set by ID/EX.IR. top MUX: branch or not (ID/EX.NPC or ID/EX.A) bottom MUX: reg-reg ALU or other ( ID/EX.B or other)

Chooses between PC+4 and EX/MEM. ALUOutput controlled by EX/MEM.cond

controlled by whether inst. is a LD or an ALU op