Unit 6

6.1 8255 Programmable Peripheral Interface and Interfacing

The 8255 is a widely used, programmable parallel I/O device. It can be programmed to transfer data under data under various conditions, from simple I/O to interrupt I/O. It is flexible, versatile and economical (when multiple I/O ports are required). It is an important general purpose I/O device that can be used with almost any microprocessor. The 8255 has 24 I/O pins that can be grouped primarily into two 8 bit parallel ports: A and B, with the remaining 8 bits as Port C. The 8 bits of port C can be used as individual bits or be grouped into two 4 bit ports : CUpper (CU) and CLower (CL). The functions of these ports are defined by writing a control word in the control register. 8255 can be used in two modes: Bit set/Reset (BSR) mode and I/O mode. The BSR mode is used to set or reset the bits in port C. The I/O mode is further divided into 3 modes: mode 0, mode 1 and mode 2. In mode 0, all ports function as simple I/O ports. Mode 1 is a handshake mode whereby Port A and/or Port B use bits from Port C as handshake signals. In the handshake mode, two types of I/O data transfer can be implemented: status check and interrupt. In mode 2, Port A can be set up for

bidirectional data transfer using handshake signals from Port C, and Port B can be set up either in mode 0 or mode 1.

Fig. 6.1 Pin Configuration of 8255 1

6.1.1 Control Logic of 8255

RD (Read) : This signal enables the Read operation. When the signal is low,
microprocessor reads data from a selected I/O port of 8255.

WR (Write) : This control signal enables the write operation.

RESET (Reset) : It clears the control registers and sets all ports in input mode.

CS , A0, A1 : These are device select signals. is connected to a decoded address and
A0, A1 are connected to A0, A1 of microprocessor.

CS
0 0 0 0

A1 0 0 1 1

A0 0 1 0 1

Selected Port A Port B Port C Control Register

8255 is not selected

Fig. 6.2 Block Diagram of 8255

Fig. 6.2 Control word format of 8255

6.1.2 BSR Mode of 8255

Fig. 6.3 BSR Mode of 8255

6.1.3 I/O Modes of 8255 Mode 0 : Simple Input or Output In this mode, Port A and Port B are used as two simple 8-bit I/O ports and Port C as two 4-bit I/O ports. Each port (or half-port, in case of Port C) can be programmed to function as simply an input port or an output port. The input/output features in mode 0 are : Outputs are latched, Inputs are not latched. Ports do not have handshake or interrupt capability. Mode 1 : Input or Output with handshake In mode 1, handshake signals are exchanged between the microprocessor and peripherals prior to data transfer. The ports (A and B) function as 8-bit I/O ports. They can be configured either as input or output ports. Each port (Port A and Port B) uses 3 lines from port C as handshake signals. The remaining two lines of port C can be used for simple I/O functions. Input and output data are latched and Interrupt logic is supported. Mode 1 : Input control signals

Fig. 6.4 Mode 1 Input Control Signals

STB (Strobe Input) : This signal (active low) is generated by a peripheral device
that it has transmitted a byte of data. The 8255, in response to , INTR. IBF (Input buffer full) : This signal is an acknowledgement by the 8255 to indicate that the input latch has received the data byte. This is reset when the microprocessor reads the data. INTR (Interrupt Request) : This is an output signal that may be used to interrupt
STB the microprocessor. This signal is generated if

generates IBF and

, IBF and INTE are all at logic 1.

INTE (Interrupt Enable) : This is an internal flip-flop to a port and needs to be set to generate the INTR signal. The two flip-flops INTEA and INTEB are set /reset using the BSR mode. The INTEA is enabled or disabled through enabled or disabled through PC2 . PC4 , and INTEB is

Fig. 6.5 Timing Waveforms of Mode 1 input operation

Mode 1 : Output control signals

Fig. 6.6 Mode 1 Ounput Control Signals

Timing Waveforms of Mode 1output operation

Fig. 6.7 Timing Waveforms of Mode 1 output operation

OBF (Output Buffer Full) : This is an output signal that goes low when the

microprocessor writes data into the output latch of the 8255. This signal indicates to an output peripheral that new data is ready to be read. It goes high again after the 8255 receives a
ACK

signal from the peripheral.

(Acknowledge) : This is an input signal from a peripheral that must output a low

when the peripheral receives the data from the 8255 ports. INTR (Interrupt Request) : This is an output signal, and it is set by the rising edge of the ACK signal. This signal can be used to interrupt the microprocessor to request the next data byte for output. The INTR is set when OBF , ACK and INTE are all one and , reset by the rising edge of WR . . INTE (Interrupt Enable) : This is an internal flip-flop to a port and needs to be set to generate the INTR signal. The two flip-flops INTEA and INTEB are set /reset using the BSR mode. The INTEA signal can be enabled or disabled through INTEB is enabled or disabled through PC2 . Mode 2 : Bidirectional Data Transfer 7 PC6 , and

This mode is used primarily in applications such as data transfer between the two computers or floppy disk controller interface. Port A can be configured as the bidirectional port and Port B either in mode 0 or mode 1. Port A uses five signals from Port C as handshake signals for data transfer. The remaining three lines from Port C can be used either as simple I/O or as handshake signals for Port B.

Fig. 6.8 Mode 2 Control Signals

INTERFACING ANALOG TO DIGITAL DATA CONVERTERS

This topic is aimed at the study of 8-bit and 12-bit analog to digital converters and their interfacing with 8086. In most of the cases, the PIO 8255 is used for interfacing the analog to digital converters with a microprocessor. We have already studied 8255 interfacing with 8086 as an I/O port, in the previous section. This section will only emphasize the interfacing techniques of analog to digital converters with 8255. The function of an A/D converter is to produce a digital word which represents the magnitude of some analog voltage or current. The specifications for an A/D converter are very similar to those for D/A converter. The resolution of an A/D converter refers to the number of bits in the output binary word. An 8-bit converter for example has a resolution of 1 part in 256. Accuracy and linearity specifications have the same meaning for an A/D converter as they do for a D/A converter. Another important specification for an ADC is its conversion time. This is simply the time it takes the converter to produce a valid output binary code for an applied input voltage. When we refer to a converter as high speed, we mean that it has a short conversion time.
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The analog to digital converter is treated as an input device by the microprocessor that sends an initialising signal to the ADC to start the analog to digital data conversation process. The start of conversion signal is a pulse of a specific duration. The process of analog to digital conversion is a slow process, and the microprocessor has to wait for the digital data till the conversion is over. After the conversion is over, the ADC sends end of conversion (EOC) signal to inform the microprocessor that the conversion is over and the result is ready at the output buffer of the ADC. These tasks of issuing an SOC pulse to ADC, reading EOC signal from the ADC and reading the digital output of the ADC are carried out by the CPU using 8255 I/O ports. The time taken by the ADC from the active edge of SOC pulse (the edge at which the conversion process actually starts) till the active edge of EOC signal is called as the conversion delay of the ADC. Or broadly speaking the time taken by the converter to calculate the equivalent digital data output from the instant of the start of conversion is called conversion delay. It may range any where from a few microseconds in case of fast ADCs to even a few hundred milliseconds in case of slow ADCs. A number of ADCs are available in the market, The selection of ADC for a particular application is done, keeping in mind the required speed, resolution range of operation, power supply requirements, sample and hold device requirements and the cost factors are considered. The available ADCs in the market use different conversion techniques for the conversion of analog signals to digital signals. Parallel converter or flash converter, Successive approximation and dual slope integration techniques are the most popular techniques used in the integrated ADC chips. Whatever may be the technique used for conversion, a general algorithm for ADC interfacing contains the following steps. 1. Ensure the stability of analog input, applied to the ADC. 2. Issue start of conversion (SOC) pulse to ADC. 3. Read end of conversion (EOC) signal to mark the end of conversion process. 4. Read digital data output of the ADC as equivalent digital output. It may be noted that analog input voltage must be constant at the input of the ADC right from the start of conversion till the end of conversion to get correct results. This may be ensured by a sample and hold circuit which samples the analog signal and holds it constant for a specified time duration. The microprocessor may issue a hold signal to the sample
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and Hold circuit. If the applied input changes before the complete conversion process is over, the digital equivalent of the analog input calculated by the ADC may not be correct. ADC 0808/0809 The analog to digital converter chips 0808 and 0809 are 8-bit CMOS, successive approximation converters. Successive approximation technique is one of the fast techniques for analog to digital conversion. The conversion delay is 100 s at a clock frequency of 640 kHz, which is quite low as compared to other converters. These converters do not need any external zero or full scale adjustments as they are already taken care of by internal circuits. These converters internally have a 3:8 analog multiplexer so that at a time eight different analog inputs can be connected to the chips. Out of these eight inputs only one can be selected for conversion by using address lines ADD A, ADD B and ADD C, as shown. Using these address inputs, multichannel data acquisition systems can be designed using a single ADC. The CPU may drive these lines using output port lines in case of multichannel applications. In case of single input applications, these may be hard wired to select the proper input.

Address lines C B A I/P 0 0 0 0 I/P 1 0 0 1 I/P 2 0 1 0 I/P 3 0 1 1 I/P 4 1 0 0 I/P 5 1 0 1 I/P 6 1 1 0 I/P 7 1 1 1 These are unipolar analog to digital converters, i.e. they are able to convert

Analog I/P selected

10

Fig.1. Block Diagram of ADC 0808/0809

only positive analog input voltages to their digital equivalents. These chips do not contain any internal sample and hold circuit. If one needs a sample and hold circuit for the conversion of fast, signals into equivalent digital quantities, it has to be externally connected at each of the analog inputs. Figure1 shows the block diagram and Figure 2 shows the pin diagram for ADC 08/0809.

I/P0-I/P7 Analog ADD Fig.2. Pin Diagram of ADC 0808/0809

inputs A, B, C

Address lines for selecting analog inputs O7 - O0 Digital 8-bit output with O7 MSB and O0 LSB SOC Start of conversion signal pin EOC End of conversion signal pin OE Output latch enable pin, if high enables output CLK Clock input for ADC Vcc, GND Supply pins +5V and GND Vref+ and VrefReference voltage positive (+5 Volts max.) and Reference voltage negative (OV minimum) Some electrical specifications of ADC 0808/0809. Minimum SOC pulse width Minimum ALE pulse width Clock frequency Conversion time Resolution Error 100ns 100ns 10 to 1280 KHz 100s at 640kHz 8-bit 1 LSB
11

Vref+ Vref+Vcc supply Logical 1 i/p voltage Logical 0 i/p voltage Logical 1 o/p voltage Logical 0 o/p voltage

Not more than +5V Not less than GND +5V DC minimum Vcc -1.5V maximum 1.5V minimum Vcc -0.4V maximum 0.45V

Fig.3. Timing Diagram of ADC 0808/0809

Till now we have studied the necessary details of the analog to digital converter chips 0808/0809. Now we consider some interfacing examples of these chips with 8086 so that the working of these ADCs will be absolutely clear along with the required algorithms for interfacing. Example: Interface ADC 0808 with 8086 using 8255 ports. Use Port A of 8255 for transferring digital data output of ADC to the CPU and Port C for control signals. Assume that an analog input is present at I/P2 of the ADC and a clock input of suitable frequency is available for ADC. Draw the schematic and write required ALP. Solution Figure 4 shows the interfacing connections of ADC0808 with 8086 using 8255. The analog input I/P2 is used and therefore address pins A, B, C should be 0,1,0 respectively to select I/P2. The OE and ALE pins are already kept at +5V to select the ADC and enable the outputs. Port C upper acts as the input port to receive the EOC signal while port C lower acts as the output port to send SOC to the ADC.

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Port A acts as a 8-bit input data port to receive the digital data output from the ADC. The 8255 control word is written as follows: D7 1 D6 0 D5 0 D4 1 D3 1 D2 0 Dl 0 Do 0 Control word = 98 H

The required ALP Fig.4. Interfacing ADC 0808 with 8086 is given as follows: MOV AL, 98 H ; Initialisation of 8255 OUT CWR, AL ;. MOV AL, 02 H ; Select I/P 2 as analog OUT Port B, AL ; input. MOV AL,00H ; Give start of conversion OUT Port C,AL ; pulse to the ADC MOV AL,01H OUT Port C,AL Wait: IN AL, PortC ; Check for EOC by RCR ; reading port C upper and rotate through carry JNC Wait IN AL, PortA ; If EOC, read digital equivalent in AL HLT ; Stop

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INTERFACING DIGITAL TO ANALOG ONVERTERS:

The digital to analog converters convert binary numbers into their analog equivalent voltages or currents. Several techniques are employed for digital to analog conversion. i. Weighted resistor network ii. R-2R ladder network iii. Current output D/A converter The DAC find applications in areas like digitally controlled gains, motor speed control, programmable gain amplifiers, digital voltmeters, panel meters, etc. D/A converter have many applications besides those where they are used with a microcomputer. In a compact disk audio player for example a 14-or16-bit D/A converter is used to convert the binary data read off the disk by a laser to an analog audio signal. Most speech synthesizer integrated circuits contain a D/A converter to convert stored binary data words into analog audio signals.

Characteristics
1. Resolution: It is a change in analog output for one LSB change in digital input. It is given by(1/2n )*Vref. If n=8 (i.e.8-bit DAC) 1/256*5V=39.06mV 2. Settling time: It is the time required for the DAC to settle for a full scale code change.

DAC 0800 8-bit Digital to Analog converter Features:

i. ii. iii. DAC0800 is a monolithic 8-bit DAC manufactured by National semiconductor. It has settling time around 100ms It can operate on a range of power supply voltage i.e. from 4.5V to +18V. Usually the supply V+ is 5V or +12V. The V- pin can be kept at a minimum of -12V. Resolution of the DAC is 39.06mV

iv.

Pin Diagram of DAC 0800:

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Interfacing of DAC0800 with 8086:

STEPPER MOTOR INTERFACING A stepper motor is stepped from one position to the next by changing the currents through the fields in the motor. The two common field connections are referred to as two phase or four phase. There are three main areas of applications for stepper motor. i. Instrumentation ii. Computer peripherals iii. Machine drives. They are used in floppy drives, dot-matrix printers, X-Y plotters, digital watches etc to rotate things in steps of small angles. The step size in typical stepper motor varies from 0.9o to 30o.
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A stepper motor is a device used to obtain an accurate position control of rotating shafts. A stepper motor employs rotation of its shaft in terms of steps, rather than continuous rotation as in case of AC or DC motors. To rotate the shaft of the stepper motor, a sequence of pulses is needed to be applied to the windings ofthe stepper motor, in proper sequence. The number of pulses required for one complete rotation of the shaft of the stepper motor are equal to its number of internal teeth on its rotor. The stator teeth and the rotor teeth lock with each other to fix a position of the shaft. With a pulse applied to the winding input, the rotor rotates by one teeth position or an angle x. The angle x may be calculated as. x =360 /no. of rotor teeth After the rotation of the shaft through angle x the rotor locks itself with the next tooth in the sequence on the internal surface of stator. The internal schematic of a typical stepper motor with four windings is Fig. 1. shown in Fig. 1.

Internal Schematic of a Four Winding Stepper Motor

The stepper motors have been designed to work with digital circuits. Binary level pulses of 0-5V are required at its winding inputs to obtain the rotation of shafts. The sequence of the pulses can be decided, depending upon the required motion of the shaft. Figure 1.1 shows a typical winding arrangement of the stepper motor. Figure 1.2 shows conceptual positioning of the rotor teeth on the surface of rotor, for a six teeth rotor.

The circuit for interfacing a winding Wn with an I/O port is given in Fig. 1.3. Fig. 1.1 Winding Arrangement of a Stepper Motor Each of the windings of a stepper motor needs Fig. 1.2 Motor A Stepper Motor Ration this circuit for its interfacing with the output port. A typical stepper motor may have parameters like torque 3 kg-em, operating voltage 12V, current rating 1.2A and a step angle 1.80, i.e. 200 steps/revolution (number of rotor teeth).

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A simple scheme for rotating the shaft of a stepper motor is called as wave scheme. In this scheme, the windings Wa, Wb, We and Wd are applied with the required voltage pulses, in a cyclic fashion. By reversing the sequence of excitation, the direction of rotation of the stepper motor shaft may be reversed. Table 1 shows the excitation sequences for clockwise and anticlockwise rotations. Another popular scheme for rotation of a stepper motor shaft applies pulses to two successive windings at a time but these are shifted only by one position at a time. This scheme for rotation of stepper motor shaft is shown in Table 1. Table 1 excitation Sequences of a Stepper Motor Using Wave Switching Scheme Motion Clockwise Step 1 2 3 4 5 1 2 3 4 5 A 1 0 0 0 1 1 0 0 0 1 B 0 1 0 0 0 0 0 0 1 0 C 0 0 1 0 0 0 0 1 0 0 D 0 0 0 1 0 0 1 0 0 0

Anticlock wise

Fig. 1.3 Interfacing Stepper Motor winding Wa ALP FOR STEPPER MOTOR TO ROTATE CLOCKWISE/ ANTICLOCKWISE DIRECTION FOR N ROTATIONS.
DATA SEGMENT PORTA PORTB PORTC CWR

EQU EQU EQU EQU

0C800H 0C801H 0C802H 0C803H 17

PHA PHB PHC PHD DATA ENDS

EQU EQU EQU EQU

077H 0BBH 0DDH 0EEH

CODE SEGMENT ASSUME CS: CODE, DS: DATA START: MOV AX, DATA MOV DS, AX MOV DX, CWR MOV AL, 80H OUT DX, AL AGAIN: MOV AL, PHA CALL STEP MOV AL, PHB CALL STEP MOV AL, PHC CALL STEP MOV AL, PHD CALL STEP

MOV BL, 0FFH X: MOV CX, 0FFFFH X1: LOOP X1 DEC BL JNZ X MOV AH, 0BH INT 21H OR AL, AL JZ AGAIN MOV AH, 4CH INT 21H

STEP PROC NEAR MOV DX, PORTC

18

K1: K2:

OUT DX, AL MOV BL, 60H MOV CX, 0FFFFH LOOP K2 DEC BL JNZ K1 RET

STEP ENDP CODE ENDS END START

Parallel Printer Interface:

For the most common printer such as the IBM PC printer, the Epson dot matrix printers and the Panasonic dot matrix printers, data to be printed is sent to the printer as ASCII characters on eight parallel lines. The printer receives the characters to be printed and stores them in an internal RAM buffers. When the printer detects a carriage return character, it prints out the first row of characters from the print buffer. When the printer detects a second carries return, it prints out the second row of characters etc. The process continuous until the desired characters have been printed. Transfer of the ASCII codes from a microcomputer to a printer must be done on a handshake basis because the microcomputer can send characters much faster than a printer can print them. The printer must in some way let the microcomputer know that its buffer is full and that is cannot accept any more characters until it prints some out. A common standard for interface with parallel printers in the centronics parallel interface standard, named for the company that developed it. Centronics type printers usually have a 36-pin interface connected. This 36pin connector fall into two categories, i. Signals sent to the printer to tell it what operation to do and ii. signals form the printer that indicate its status. The major control signals to the printer are INIT on pin 31, which tells the printer to perform its initialization sequence, and STROBE on pin1 which tells the printer Here is a character for you. The two addition input pins pin14 and pin16 are usually taken care of inside the printer. The major status signals output from the printer are 1. The ACKNLG signal on pin10, which when low indicates that the character has been accepted and the printer is ready for the next character. 2. The BUSY signal on pin11, which is high if, for some reason such as being out of paper, the printer is not ready to receive a character. 3. The PE signal on pin12 which goes high if the out of paper switch in the printer is activated.

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4. The SLCT signal on pin13, which goes high if the printer is selected for receiving data 5. The ERROR signal on pin32, which goes low for a variety of problem conditions in the printer.

Fig1.2 Centronics printer connector

Fig 1.3 Timing waveform of data transfer to a Centronics compatible parallel printer

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Fig1.1 Printer Interface with 8255

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Example: Interface a standard IEEE-488 parallel bus printer with 8086. Draw the
necessary hardware scheme required for the same and write an ALP to print a character whose ASCII code is available in AL. Solution: Before going through this solution, one should refer to the standard Centronix, INB or EPSON printer pin configuration, given in Table 5.11. There are two types of parallel cables used to connect a microcomputer with a printer, viz. 25 pin cables and 36 pin cables. Basically the 25 pin and the 36 pin cables are similar except for the 11 extra pins for ground (GND) used as 'RETURN' lines for different signals. The group A is used in mode 1 for handshake data transfer so that port A is used for data transfer and port Clines PC3-PC5 are used as handshake lines. Port B lines are used for checking the printer status; hence port B is used as input port in mode o. Port C lower is used as output port for enabling the printer. The control words are shown in Fig. 1.4
Table 5.11 Pin Connections and Descriptions for Centronix-type Parallel Interface to IBM PC and EPSON FX-l 00 Printers
Directi on

Printer Controller
Signal Pin No. Return Pin No. Signal
---

Description

19

STROBE

IN

STROBE pulse to read data in. Pulse width must be morE than 0.5 f..ls at receiving terminal. The signal level is normally "high"; read-in of data is performed at the "low" level of this signal. These signals represent information of the 1st to 8th bits of parallel data respectively. Each signal is at "high" level when data is logical "1" and "low" when logical "0".

2 3 4 5 6 7 8 9 10

20 21 22 23 24 25 26 27 28

DATA 1 DATA 2 DATA 3 DATA 4 DATA 5 DATA 6 DATA 7 DATA 8 ACKNLG

IN IN IN IN IN IN IN IN OUT

Approximately 5 f..ls pulse; "low" indicates the data has been received and the printer is ready to accept other data.

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A "high" signal indicates that the printer cannot receive data. The signal becomes "high" in the following cases. 1. During data entry. 2. During printing operation. 3. In "outline" state. 4. During printer error status. A "high" signal indicates that the printer is out of paper. This signal indicates that the printer is in the selected signal With thisstate being at "low" level, the paper is automatically fed one line after printing. (The signal level can be fixed to "low" with DIPSW Pin 2-3 provided on the control circuit board). Not used. Logic GND Level. Printer chasis GND. In the printer, the chasis GND and the logic GND are isolated from each other.
-

11

29

BUSY

OUT

12

30

PE

OUT

13

SLCT
---

OUT

14

AUTO FEED XT

IN

15 16 17

NC OV CHASIS GND

18 19-30

NC GND --

31

IN IT

IN

Not used. "Twisted-Pair Return" signal; GND level. When the level of this signal becomes "low" the printer controller is reset to its initial state and the print buffer is cleared. This signal is normally at "high" level, and its must be more than 50 J.ts at the pulse width receiving terminal.signal becomes "low" when The level of this the"Paper End "state, "Ofline" state and "Error" in printer is state. Same as with pin numbers 19 to 30. Not used. Pulled up to + 5 Vdc through 4.7 k-ohms resistance. to the printer is possible only when Data entry the level

32 33 34 35
-

ERROR

OUT

GND NC

23

36

SLCT IN

IN

of this signal is "low". (Internal fixing can be carried out with DIP SW 1-8. The condition at the time of shipment is set "low" for this signal.)

Operation: The printer interface connections with 8255 and the printer connector in Fig.1.1 and Fig.1.2 respectively. First of all the printer should be initialised by a 50 S (minimum) pulse on the INIT pin of the printer. Then BUSY pin is to be to confirm if the printer is ready. If this signal is low, it indicates that the printer is to accept a character from the CPU. Port pins of 8255 may not have sufficient drive capacity to drive the printer input signals so the open collector buffers 74LSOY are used to enhance the drive capacity. Then the ASCII code of the character to be printed is sent on the eight parallel port lines. Once the data is sent on eight parallel lines, the STROBE signal is activated after at least 0.5s, to indicate that the data is available on the eight data lines. The falling edge of the STROBE signal causes the printer to make its BUSY pin high, indicating that the printer is busy. After a minimum period of 0.5S, the STROBE signal can be sent high. The data must be valid on the data lines for at least 0.5S after the STROBE signal goes high. After receiving the appropriate STROBE pulse, the printer starts the necessary electromechanical action to print the character and when it is ready to receive the next character, it asserts its ACKNLG signal low approximately for 5 ms. The rising edge of the ACKNLG signal indicates to the computer that it is ready to receive the next character. The rising edge of the ACKNLG signal also resets the BUSY signal from the printer. A low on the BUSY pin further indicates that the printer is ready to accept the next character. The ACKNLG and BUSY signals can be used interchangeably for handshaking purposes. The waveforms for the above printer operation are shown in Fig.1.3

D7 1

D6 0

D5 D4 1 0

D3 0

D2 0

D1 1

D0 0 A2H

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D0 D1 D2 D3

Port C lower O/P port Port B bit I/P port Port B mode 0 Port C upper dont care

D4

Port A O/P port

D5 D6 Group A in mode 1 D7 I/O mode

Strobed I/O mode control word D7 D0 D6 D5 D4 0 0 D3 1 D2 1 D4 D1 0 D0 1

0 0 Set to enable

Port A O/P port Dont cares

D1 D2 D3 Bit PC6 set for sending INTR signal to 8086

D4D5 D6 D7

Bit Set/ Reset mode

Fig1.4 Bit Set/Reset control word

Assembly Language Program
MOV BL,AL ; Get the ASCII code in BL.

MOV AL,02H ; Control word for 8255 OUT 0F6H,AL ; Load CWR with the control word.

BUSY:IN AL,0F2H ; Read printer status from the BUSY pin. AND AL,08H ; Mask all bits except PB3. JNZ BUSY ; If AL#O, printer is busy. Wait till ; it becomes free. MOV AL,BL OUT 0F0H,AL NOP ; Get the character for printer in AL. ; Send it to the port for the printer. ;Wait for some time

MOV AL,08H ;Pull STROBE low OUT 0F6H NOP ;Reset PC4 ;Wait

MOV AL,09H ;Raise STROBE high OUT 0F6H HLT Set PC4

25