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Appendix B-1

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RAMBUSS PROPOSED CLAIM CONSTRUCTIONS AND SUPPORTING EVIDENCE No. Claim Term, Rambuss Proposed Phrase, or Clause Construction 1. address information one or more bits that indicate a storage location Rambuss Supporting Evidence1 916 patent, 1:30-49; 1:61 - 2:6; 3:52 - 4:36; 5:31-54; 6:58 - 7:11; 7:23 8:40; 8:65 - 9:45; 23:50 24:52; Figs. 1, 4. Hynix I2 Joint Claim Construction and Prehearing Statement) (hereinafter referred to as Hynix I JCCS) (R20748263-271). Coordinated Actions3 Claim Construction Order for the Farmwald/Horowitz Patents (hereinafter referred to as Coordinated Actions CC Order) (R20746710-800). Definitions for address and information in IEEE Standard Dictionary of Electrical and Electronics Terms, Fourth Edition, 1988 (hereinafter referred to as 1988 IEEE Dictionary), pp. 23, 473. Definitions for address and information in The New IEEE Standard Dictionary of Electrical and Electronic Terms, Fifth Edition, 1993 (hereinafter referred to as 1993 IEEE Dictionary), pp. 16-17, 642.

In addition to the intrinsic and extrinsic evidence identified below, for each of the terms, Rambus identifies as intrinsic evidence the asserted claim(s) in which the term appears. Rambus may also rely on any intrinsic or extrinsic evidence identified by the defendants in support of their proposed constructions. Rambus may also rely on additional intrinsic and extrinsic evidence, including additional documents from prior litigation, the prosecution history of the patents-in-suit or any other patent claiming priority to U.S. App. No. 07/510,898, and/or any reexaminations, to rebut proposed constructions and/or arguments made by the defendants. In addition, Rambus may introduce the expert testimony of Robert Murphy in the form of a report or declaration. Mr. Murphy is expected to testify that the patents-in-suit pertain to the art of memory device and system design and that a person of ordinary skill in the art would have had a Bachelor of Science degree in Electrical Engineering with 3-5 years of experience designing memory circuits, such as DRAM memory, memory controllers, and/or memory interfaces. Mr. Murphy is expected to provide some background testimony about the nature of the claimed inventions. Mr. Murphy is further expected to testify that a person of ordinary skill in the art would understand, in light of the specification, the meaning of the claim terms listed below. Further, Mr. Murphy may respond to any expert testimony submitted by the defendants. 2 Hynix Semiconductor Inc. et al. v. Rambus Inc., No. 00-cv-20905-RMW (N.D. Cal.). 3 Rambus Inc. v. Hynix Semiconductor Inc., et al., No. 05-cv-00334-RMW (N.D. Cal.); Rambus Inc. v. Samsung Electronics Co. Ltd. et al., No. 05-cv-02298RMW (N.D. Cal.); and Rambus Inc. v. Micron Technology, Inc. et al., No. 06-cv-00244-RMW (N.D. Cal.).

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2. array of memory cells

a plurality of memory cells that are arranged in rows and columns

916 patent at 1:61 - 2:6; 3:23- 48; 3:52-54; 4:27-35; 4:60-61; 4:65-5:1; 5:8-9; 6:10-19; 7:23- 41; 7:58-61; 8:34-35; 8:41-48; 16:7-10; 16:38-40; 17:40-46; 19:20; 19:39-50; 21:38-40; 21:57-62; 22:64 23:33; 23:39-44; 23:51-54; 24:65-67; Figs. 1, 2,3, 4, 8a, 10, 13, 15, and 16. Hynix I JCCS (R20748263-271). Coordinated Actions Joint Claim Construction and Prehearing Statement) (hereinafter referred to as Coordinated Actions JCCS) (R20747285-291). Definitions for memory, storage cell and storage medium in 1988 IEEE Dictionary, pp. 582, 956-957. Definition for memory cell in 1993 IEEE Dictionary, p. 797. Definition for array in Websters New World Dictionary (3d ed. 1988), (hereinafter referred to as 1988 Websters Dictionary), p. 76.

3. binary code

one or more bits representing a value

916 patent, 11:44-67. Definition of binary code in 1988 IEEE Dictionary, p. 95. Definition of binary code in 1993 IEEE Dictionary, p. 108. See operation code. 916 patent, 11:44-67; 17:5-11; 20:23-27; 24:65-67; Fig. 4. Hynix I Claim Construction Order (hereinafter referred to as Hynix I CC Order) (R20749324-357). Coordinated Actions CC Order (R20746710-800). Definition for block in 1988 IEEE Dictionary, p. 99. Definition for block in 1993 IEEE Dictionary, p. 116.

4. block size value

value that specifies the total amount of data that is to be transferred on the bus in response to a read request, write request, or operation code

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5. clock cycle

an amount of time equal to one clock period

916 patent, 7:12-15; 8:40-47; 8:65 - 9:3; 9:17-25; 10:15-19; 15:32-57; 16:1-15; 19:1-50; Figs. 4, 8a, 8b, 13, 14. Definition of bus clock cycle in 1993 IEEE Dictionary, p. 141.

6. clock signal

a periodic signal, i.e. one that is continuously present and repeats at regular intervals, to provide timing information 7. controller/controller an integrated circuit device device that includes circuitry to direct the actions of one or more memory devices 8. external clock a periodic signal, i.e. one signal that is continuously present and repeats at regular intervals, from a source external to the device to provide timing information

See external clock signal.

916 patent, 6:16 - 8:20; 8:47 - 11:67; 12:51 - 17:4. Hynix I JCCS (R20748263-271). See memory device. 916 patent, 3:29-31; 7:12-13; 8:34-35; 8:42-43; 19:1-50; 21:56-22:7; 22:57 - 23:49; 24:65-67; Figs. 2, 8a, 12, 13, 14. Hynix I JCCS (R20748263-271). Coordinated Actions CC Order (R20746710-800). Definitions for clock and signal in 1988 IEEE Dictionary, pp. 155-156, 896. Definitions for clock and signal in 1993 IEEE Dictionary, pp. 196, 1218-1219. Hynix I JCCS (R20748263-271). Coordinated Actions JCCS (R20747285-291).

9. in response to

as a result of

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10. integrated circuit controller device

11. memory device

an integrated circuit device that includes circuitry to direct the actions of one or more memory devices an integrated circuit device in which information can be stored and retrieved electronically, not including a memory controller

916 patent, 6:16 - 8:20; 8:47 - 11:67; 12:51 - 17:4. Hynix I JCCS (R20748263-271). See memory device. 916 patent, 1:20-22; 1:31-60; 2:32-36; 3:5-8; 3:16-22; 3:23-28; 3:32-48; 3:52-54; 3:63-65; 4:27-35; 4:60-61; 4:65 - 5:1; 5:8-9; 6:10-28; 7:23 - 8:14; 8:34-35; 8:41-64; 14:43 - 15:5; 16:1-10; 16:48-63; 17:20-46; 19:20-25; 19:39-43; 19:46 - 20:20; 21:38-40; 21:57-62; 22:64 - 23:33; 23:39-44; 24:65-67; Figs. 1, 2, 3, 4, 8a, 8b, 9, 10, 13, 15, 16. Original claims (R20745742-803). File history of U.S. Patent No. 6,034,918 (R20747241-265). Rambus Inc. v. Infineon, 318 F.3d 1081, 1089-91 (Fed. Cir. 2003). Hynix I JCCS (R20748263-271). Coordinated Actions CC Order (R20746710-800). Testimony of Desi Rhoden (R20745963-966). Rambuss briefs re reconsideration of construction of memory device (R20747163-178, R20747224-231). Order Clarifying the Courts Construction of Memory Device, Case No. 05-00334-RMW, Dkt. No. 2603.

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12. operation code

one or more bits to specify a type of action

916 patent, 9:30-49; 9:54 -10:5; 10:21-64; 11:25 - 12:7; 24:65-67; Fig. 4. Hynix I CC Order (R20749324-357). Coordinated Actions CC Order (R20746710-800). Definitions for operation and code in 1988 IEEE Dictionary, pp. 159, 646. Definitions for operation, code and operation code in 1993 IEEE Dictionary, pp. 201-202, 888, 889.

13. precharged automatically

precharged without an additional command

916 patent, 10:25-31; 10:47-55; 10:60-64; 11:26-44; 24:65-67. Coordinated Actions CC Order (R20746710-800). Definition for automatic/automatically in 1988 Websters Dictionary, p. 93. Definition for automatic in Academic Press Dictionary of Science and Technology, 1992, p. 188.

14. precharge information

one or more bits indicating whether the sense amplifiers and/or bit lines (or a portion of the sense amplifiers and/or bit lines) should be precharged

916 patent, 10:25-28; 10:47-55; 10:60-64; 11:26-44; 24:65-67. Hynix I CC Order (R20749324-357). Coordinated Actions CC Order (R20746710-800). A 4096-b One Transistor per Bit Random Access Memory with Internal Timing and Low Dissipation, L. Boonstra et al., IEEE Journal of Solid State Circuits, Vol. SC-8, No. 5, October 1973, pp. 306-308. CMOS Devices and Technology for VLSI, John Y. Chen, 1990, pp. 106110, 115-116.

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15. programmable register

a register whose contents can be modified based on information received from an external source

916 patent, 4:23-27; 6:31-57; 9:14-16; 9:22-25; 9:54 -10:21; 14:54 - 15:8; 16:1-15; Fig. 16. Hynix I JCCS (R20748263-271). Coordinated Actions JCCS (R20747285-291). Definition for programmable in 1988 IEEE Dictionary, p. 740. Definition for programmable in 1993 IEEE Dictionary, p. 1014. See register. 916 patent, 1:30-47; 9:54-63; 10:22-34; 24:65-67; Fig. 4. Coordinated Actions CC Order (R20746710-800). Definition for read in 1988 IEEE Dictionary, p. 792. Definition for read in 1993 IEEE Dictionary, p. 1081. See operation code. 916 patent, 4:22-27; 6:31-56; 9:22-24; 9:54 - 10:21; 14:53 - 16:25; 24:6567; Fig. 16. Hynix I JCCS (R20748263-271). Coordinated Actions JCCS (R20747285-291). Definition for register in 1988 IEEE Dictionary, p. 808. Definition for register in 1993 IEEE Dictionary, p. 1103. Hynix I CC Order (R20749324-357). Coordinated Actions Order Denying Motion for Summary Judgment No. 1 of Invalidity, 05-00334-RMW Dkt. No. 1832, at 23-24. Definition for represent in 1988 Websters Dictionary, p. 1139.

16. read operation

reading data from the memory array as specified in the operation code

17. register

a data storage element or group of data storage elements not part of a memory array that can store one or more bits of information

18. representative of

indicates

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19. sample(s)/sampled/ sampling

20. synchronous dynamic random access memory device

obtain(s) at one or more discrete points in time/obtained at one or more discrete points in time/obtaining at one or more discrete points in time an integrated circuit device in which information can be stored and retrieved electronically, not including a memory controller, that receives an external clock signal which governs the timing of the response to a read request, write request, or operation code and includes one or more arrays of DRAM cells

916 patent, 19:36-38; 21:48-23:49; Fig. 11. Coordinated Actions CC Order (R20746710-800). Definitions for sampled data and sampled signal in 1988 IEEE Dictionary, p. 855. Definitions for sampled data and sampled signal in 1993 IEEE Dictionary, p. 1164. Hynix I JCCS (R20748263-271). Coordinated Actions JCCS (R20747285-291). Definitions for dynamic memory, dynamic RAM, and memory in HarperCollins Dictionary of Electronics, 1991, pp. 93, 184-85. See synchronous memory device.

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21. synchronous memory device

an integrated circuit device in which information can be stored and retrieved electronically, not including a memory controller, that receives an external clock signal which governs the timing of the response to a read request, write request, or operation code having a known timing relationship with respect to

916 patent, 1:31-60; 3:23-28; 3:32-48; 3:52-54; 4:27-35; 4:60-61; 4:65 5:1; 5:8-9; 6:10-19; 7:23-41; 7:58-61; 8:34-35; 8:41-48; 16:7-10; 16:38-40; 17:40-46; 19:20; 19:39-43; 19:46-50; 21:38-40; 21:57-62; 22:64 - 23:33; 23:21-22; 23:39-44; 24:65-67; Figs. 1, 2, 3, 4, 8a, 10, 13, 15, and 16. Rambus Inc. v. Infineon, 318 F.3d 1081, 1089-91 (Fed. Cir. 2003). Hynix I CC Order (R20749324-357). Coordinated Actions CC Order (R20746710-800). Definitions for synchronous computer, synchronous device and synchronous gate in 1988 IEEE Dictionary, p. 979. Definitions for synchronous, synchronous computer, synchronous device and synchronous gate in 1993 IEEE Dictionary, p. 1326. See memory device, external clock signal. Hynix I JCCS (R20748263-271). Hynix I CC Order (R20749324-357), Coordinated Actions CC Order (R20746710-800). Definitions for synchronous computer, synchronous device and synchronous gate in 1988 IEEE Dictionary, p. 979. Definitions for synchronous, synchronous computer, synchronous device and synchronous gate in 1993 IEEE Dictionary, p. 1326. Definition for synchronization in McGraw-Hill Dictionary of Scientific and Technical Terms, Fourth Edition, 1989, p. 1873. See external clock signal.

22. synchronously with respect to

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23. write operation

writing data to the memory array as specified in the operation code

916 patent, 1:30-47; 9:54-63; 10:22-34; 24:65-67; Fig. 4. Coordinated Actions CC Order (R20746710-800). Definition for write in 1988 IEEE Dictionary, p. 1104. Definition for write in 1993 IEEE Dictionary, p. 1498. See operation code.

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