Submitted in partial fulfillment for the award of the Degree of Bachelor of Technology in Electronics & Telecommunication Engineering

Submitted by:
PRANAY KUMAR NAYAK (0801223001) MUKESH MISHRA (0801223002) DEVALIPSA MALLA SAMANTA (0801223070) SATYABRATA DASH (0801223223) SASANKA SEKHAR PATI (0801223224) DIPAK KUMAR MUDULI (0801223236)

Under the guidance of: Professor Sunil Ku. Routray

KRUPAJAL ENGINEERING COLLEGE PRASANTI VIHAR, PUBASASAN, KAUSALYA GANGA, BHUBANESWAR-751002

CERTIFICATE

This is to certify that the dissertation work entitled SMS BASED HEART BEAT ALERT SYSTEM is the work done by Pranay Kumar Nayak, Mukesh Mishra , Devalipsa Malla Samanta, Satyabrata Dash, Sasanka Sekhar Pati, and Dipak Kumar Muduli bearing REGD. No 08012230001, 0801223002, 0801223070, 0801223223, 0801223224 and 0801223236 respectively, the award of BACHELOR OF submitted in partial fulfillment for in Electronics and

TECHNOLOGY

Telecommunication Engineering from KRUPAJAL ENGINEERING COLLEGE affiliated to BIJU PATTNAIK UNIVERSITY OF TECHNOLOGY, Rourkela.

PROF. SANJIT KUMAR DASH ( Head of the Department)

EXTERNAL INVIGILATOR

ACKNOWLEDGEMENT
The satisfaction and euphoria that accompany the successful completion of any task would be incomplete without the mentioning the people whose constant guidance and encouragement made it possible. We take pleasure in presenting before you, our project, which is result of studied blend of both research and knowledge.

We express our earnest gratitude to our internal guide, PROFESSOR SUNIL KU. ROUTRAY, Department of EnTC, our project guide, for his constant

support, encouragement and guidance. We are grateful for his cooperation and his valuable suggestions. We would also like to express our gratitude to PROF. SANJIT KUMAR DASH, Head of Department, Electronics and

Telecommunication for his guidance throughout the work.

Finally, we express our gratitude to all other members who are involved either directly or indirectly in the completion of this project.

DECLARATION
We, the undersigned, declare that the project entitled SMS BASED HEART BEAT ALERT SYSTEM, being submitted in partial fulfillment for the award of Bachelor of Technology Degree in Electronics and Telecommunication Engineering of KRUPAJAL ENGINEERING COLLEGE, affiliated to BIJU PATTNAIK UNIVERSITY OF TECHNOLOGY, ROURKELA for the completion of eight semester during the academic year 2008-2012 is the work carried out by us.

PRANAY KUMAR NAYAK (0801223001) MUKESH MISHRA (0801223002) DEVALIPSA MALLA SAMANTA (0801223070) SATYABRATA DASH (0801223223) SASANKA SEKHAR PATI (0801223224) DIPAK KUMAR MUDULI (0801223236)

CONTENTS
1. INTRODUCTION. 2. DESIGN PRINCIPLE. 3. BLOCK DIAGRAM. 4. CIRCUIT DESCRIPTION.
a) Power Supply b) Heart Beat Detector c) Signal conditioning d) LED Indicators e) Mother board f) LCD Interface g) Serial Interface Unit h) Monostable multivibrator i) GSM Modem

6 7 8 9
10 13 17 20 22 42 45 57 61

5. FUTURE EXPANSION. 6. CONCLUSION. 7. REFERENCE.

67 68 69
5

1. INTRODUCTION:
The Application of Electronics Engineering in the field of medical diagnostic and management of patients in large hospital is one of the needs of the present scenario of technological diversification and development. In the large hospitals there may be multiple CCU or ICU where the patient needs to be monitored very carefully and closely. The different body parameters of the patient are continuously need to be monitored and those parameters should be within a range of safety limit. If any of the body parameter goes beyond the safety limit then the patient need to be attended by the specialists. The specialist may need the data of the different body parameter over a period to study and analyze the patient. This work normally carried out by an attendant dedicatedly monitoring the patient. An electronic solution to this using embedded system is the objective of this project work. In this project work the sensors used to read the body parameter in the form of analog or digital data. A system is designed using an AT89C51 microcontroller for reading the data and sending to the doctor as when the doctor needs to know the status of the patient. The microcontroller communicate data to a GSM Modem through its serial port, the serial is received by a GSM modem. The microcontroller based system is designed in such a way it reads the sensors on TDM (Time Division Multiplexing) and transmit the data to The GSM modem to send as SMS for further analysis. There is a common attendant for all the patients in the CCU/ ICU there a microcontroller based system is designed to receive the information. A GSM Modem with a SIM card accepts command and sends the information as a SMS from the ICU/ CCU. The received signal directly received by a mobile Hand set. In this way different patients are monitored at a single point located at a distance without having any wire contact. As this system is connected to a mobile network the distance is not a limitation.

2. DESIGN PRINCIPLE:
The patient monitoring system is designed with a microcontroller interfaced with a GSM modem. The microcontroller based system receives the signal from input devices like temperature sensor and Heartbeat sensor. The photo-diode and IR LED forms a heart beat detector. The microcontroller receives pulses and counts the number of beat per minutes. The system is waiting for a user request to send the information. When the microcontroller receives a user request then the controller reads the HEART BEAT / minute for counting the number of pulses in one minute. Then constitute a SMS in the memory and send to the GSM modem along with the AT commands to transfer the SMS. The SMS constituted by the microcontroller is send to the commands. pre defined mobile number using the GSM modem and AT

3.BLOCK DIAGRAM:
ANT

GSM MODEM

HEART BEAT DETECTOR

SIGNAL CONDITIONING

MICROCONTROLLER BASED MOTHER BOARD

SERIAL INTERFACE UNIT

MONO-SHOT MULTIVIBRATOR

+5v +12v LCD DISPLAY UNIT

POWER SUPPLY

Fig.(1)- Block Diagram

4.CIRCUIT DESCRIPTION:

Fig.(2)- circuit diagram 9

a) Power Supply:
The power supply designed for catering a fixed demand connected in this project. The basic requirement for designing a power supply is as follows, 1. The different voltage levels required for operating the devices. Here +5 Volt required for operating Microcontroller, Temperature sensor, amplifier & ADC etc. 2. The current requirement of each device or load must be added to estimate the final capacity of the power supply. The power supply always specified with one or multiple voltage outputs along with a current capacity. As it is estimate the requirement of power is approximately as follows, Out Put Voltage = +5Volt, +12Volt Capacity = 1000mA The power supply is basically consisting of three sections as follows, 1. 2. 3. Step down section Rectifier Section Regulator section

Fig.(3)- Power Supply

10

Design principle:
There are two methods for designing power supply, the average value method and peak value method. In case of small power supply peak value method is quit economical, for a particular value of DC output the input AC requirement is appreciably less. In this method the DC output is approximately equal to Vm. A full wave bridge rectifier is designed using four diodes and the output of the rectifier is filtered with a capacitor. There are two capacitors connected in this power supply, one for filtering and providing back up to positive power supply and other one for providing backup and filter action to the negative power supply. The capacitor value is decided so that it will back up for the voltage and current during the discharging period of the DC output. In this case the output with reference to the center tap of the transformer is taken into consideration, though the rectifier designed is a full wave bridge rectifier but the voltage across the load is a half wave rectified output. The Regulator section used here is configured with a series regulator LM78XX, the XX represents the output voltage and 78 series indicates the positive voltage regulator for power supply. The positive regulator works satisfactorily between the voltage XX+2 to 40 Volt DC. The output remains constant within this range of voltage. The output remains constant within this range of voltage.

Circuit connection: - In this we are using Transformer (0-12) Vac /1Amp, IC 7805 & 7812, diodes IN 4007, LED & resistors. Here 230V, 50 Hz ac signal is given as input to the primary of the transformer and the secondary of the transformer is given to the bridge rectification diode. The output of the diode is given as input to the IC regulator (7805 &7812) through capacitor (1000F/35v). The output of the IC regulator is given to the LED through resistors.

Circuit Explanations: - When ac signal is given to the primary of the transformer, due to the magnetic effect of the coil magnetic flux is induced in the coil (primary) and transfer to the secondary coil of the transformer due to the transformer action. Transformer is an electromechanical static device which transformer electrical energy from one coil to another without changing its frequency. Here the diodes are connected in a bridge fashion. The secondary coil of the transformer is given to the bridge circuit for rectification purposes.

11

During the +ve cycle of the ac signal the diodes D2 & D4 conduct due to the forward bias of the diodes and diodes D1 & D3 does not conduct due to the reversed bias of the diodes. Similarly during the ve cycle of the ac signal the diodes D1 & D3 conduct due to the forward bias of the diodes and the diodes D2 & D4 does not conduct due to reversed bias of the diodes. The output of the bridge rectifier is not a pure dc along with rippled ac is also present. VDC = 2Vm / Or , VDC = (Vm 2Vk) = (12 1.4) =10.6 VDC x 22 = 19.1V DC 17Vdc. To overcome this effect, a capacitor is connected to the o/p of the diodes (D2 & D3). Which removes the unwanted ac signal and thus a pure dc is obtained. We knew, Q=CxV C=Q/V =Ixt/V = 1Amp x 10msec/ 17 = 588.2F 1000F Here we need a fixed voltage, for that we are using IC regulators (7805 & 7812). Voltage regulation is a circuit that supplies a constant voltage regardless of changes in load current. This ICs are designed as fixed voltage regulators and with adequate heat sinking can deliver output current in excess of 1A. The output of the bridge rectifier is given as input to the IC regulator through capacitor with respect to GND and thus a fixed output is obtained.
Vmax to 78XX = +35Vdc

Vmin to 78XX = 78XX + 2V Imax = 1Amp DC.

12

The output of the IC regulator (7805 & 7812) is given to the LED for indication purpose through a series resistor. Imin to LED = 5mA Imax to LED = 30mA Then to find the value of series resistance by using the OHMs law, R1 = V1 / I = 5/5mA = 1K. R2 = V2 / I = 12 / 5mA =2.4K. 2.2K. Due to the forward bias of the LED, the LED glows ON state, and the output are obtained from the pin no-3. Finally that is fed to the corresponding sub section as a VCC with respect to GND.

7812

POWER SUPPLY
0-12Vac/1Am p

GND

VIN

VOUT

+12Vdc
2.2K

LED

7805
GND

230Vac 50Hz

VIN

VOUT

+5Vdc
1K

1N4007 x 4 1000uF
2

LED

GND

Fig.(4)-circuit diagram of power supply section

b) Heart Beat Detector:

In this sub section its aspect is to detect the heart beat for that an IR diode is taken as a source and photodiode is taken as a detector which detects the pumping of the blood. That output signal is very weak, further that output signal is further fed to the 2-stage op-amp which is configured as inverting amplifier with a gain of A=101 each.

13

Introduction
When the heart beats, a pressure wave moves out along the arteries at a few metres per second (appreciably faster than the blood actually flows). This pressure wave can be felt at the wrist, but it also causes an increase in the blood volume in the tissues, which can be detected by a plethysmograph. This word comes from the Greek "plethysmos" for increase and is a term for a "fullness" (i.e. change in volume) measuring device. Over the years, all sorts of Heath-Robinson devices have been used but described here is a photoelectric pulse plethysmograph, which is robust and easy to make and which will allow the beating of the heart to be recorded without the need to make direct electrical connections to the body.

Fig.(5)- Heart Beat detector Sensor The sensor consists of a light source and photo detector; light is shone through the tissues and variation in blood volume alters the amount of light falling on the detector. The source and detector can be mounted side by side to look at changes in reflected light or on either side of a finger or earlobe to detect changes in transmitted light. The infra red filter of the phototransistor reduces interference from fluorescent lights, which have a large AC component in their output

14

The IR diode emits IR waves which pass into the finger tip and those waves are again received by photo diode. This light is shone through the tissues and variation in blood volume alters the amount of light falling on the detector. By this no of pulses can be counted. The IR diode and the photo diode are connected in reverse bias. Amplifier The amplifier (fig. 6) uses an LM358 dual op-amp to provide two identical broadly-tuned band pass stages with gains of 100. Again, the type of op amp is not particularly critical, as long as it will work at 6V and drive the output rail to rail. The signal frequencies are boxed in by movement artefacts at the low end (generated by the peg moving and distorting the underlying tissues; light pegs are better) and at the top end by mains-hum interference. The circuit runs from a single 6 Volt battery and the output zero is offset by about 1 Volt by referring everything to an internal common line at a voltage set by a pair of forward-biased silicon diodes. This is convenient for interfaces with a 0-5Volt input. The potentiometer allows the overall gain to be adjusted so as to prevent clipping on large signals. Components are not critical but the two 2.2 F capacitors must be able to stand some reverse bias so they should be non-polarized or tantalum.

Figure 6: Pulse plethysmograph amplifier circuit

Two problems are common when using a pulse plethysmograph: movement will cause the trace to swing around wildly, so persuade the subject not to move as much and if the subject is very 15

cold (pale, pinched looking) the circulation at the extremities may be reduced to the point where there is very little signal. Calculating Heart Rate: Unlike many heart rate monitors, this set up will allow the calculation of beat-by-beat (instantaneous) heart rate. Using the cursor, note the times of two adjacent peaks, subtract the first from the second to give the time between the two beats (beat to beat interval) and express this in seconds. Divide this into 60 to obtain the instantaneous heart rate in beats per minute. Thus, for the trace in figure 5, the first peak is at 1052 ms and the second is at 2190 ms. The difference is 1138 ms or 1.138 s, which gives a rate of 52.7 beats per minute. The last peak is at 9206 ms, or 8.154 s after the first and as there are seven intervals between, so the average interval is 1.165 s and the average rate is 51.5 beats per minute.

Circuit operation:
The heart beat sensor contains following sections:I). IR LED. II). LDR and Amplifiers. III). Signal conditioning. The optical heart beat sensor is sensed by using a high intensity type IR LED and photodiode. The finger is placed between the IR LED and Photodiode. As Sensor a photo diode or a photo transistor or a LDR can be used. The skin may be illuminated with visible (red) using transmitted or reflected light for detection. The very small changes in reflectivity or in transmittance caused by the varying blood content of human tissue are almost invisible. Various noise sources may produce disturbance signals with amplitudes equal or even higher than the amplitude of the pulse signal. Valid pulse measurement therefore requires extensive preprocessing of the raw signal. The new signal processing approach presented here combines analog and digital signal processing in a way that both parts can be kept simple but in combination are very effective in suppressing disturbance signals. The setup described here uses a red LED for transmitted light illumination and a LDR as detector. With only slight changes in 16

the preamplifier circuit the same hardware and software could be used with other illumination and detection concepts. The detectors photo current (AC part) is converted to voltage and amplified by an operational amplifier (LM358) output is given to another non-inverting input of the same LM358; here the second amplification is done. A part of the filter output is fed through a signal conditioning using a transistor BC547 which is configured as a switch or inverter for a square pulse.

Vcc=+5V 680K 68 33K 2.2uF

8

680K 68K 2.2uF

8

68K

100nF

100nF 10K

470

PHOTODIODE

IR LED

68K

U1A 3 +

5 1

68K

U1B +

1.5K BC547 330

LM358
LED
4 4

Fig.7-heart beat detector

c) Signal Conditioning:
In this section its aspect is to design a circuit that output signal should be compatible with the controller, because the TTL/CMOS IC cannot produce sufficient current to drive the controller directly. Here in this section a transistor is taken as element which is configured as a switch or inverter. The output from the heart beat sensor output signal i.e. from TTL/CMOS IC or any other circuit must be compatible with the -controller, because the -controller can takes 5V as input voltage and gives a 5V as output voltage. That for we need a signal conditioning circuit as given in the below figure.

17

5v

10K 1.5K B C547

Data

out

Data

in

Signal

conditioning

Fig.8- signal conditioning

INTRODUCTION: The application of the transistors is not limited solely to the amplification of the signals. Through proper design transistors can be used as switches for computers and control applications. The network of figure-09 (a) can be employed as an inverter in computer logic circuitry. Note that the output voltage Vc is opposite to the applied to the base or input terminal. In addition note the absence of dc supply connected to the base circuit. The only dc source is connected to the collector or output side, and for computer applications is typically equal to the magnitude of the high side of the applied signal in this case 5V.

Vi 5v 0v t
IN Rb

Vcc = +5V Rc OUT Q1 BC547

Vc 5v 0v t

Fig.-9(a)

18

IC (mA)

IC sat = 6mA

IB = 80A IB = 60A IB = 40A IB = 20A IB = 10A IB = 0A VCE Vcc = 5V

Fig.-9(b)

OPERATION:
Proper design for the inversion process requires that the operating points switch from cut-off to saturation along the load line depicted in above figure 9(b). For our purposes we will assume that IC = ICEO = 0mA, when IB = 0A (an excellent approximation in light of improving construction techniques), as shown in above figure 9(b). In addition, we will assume that VCE = VCE sat = 0V. When Vi = 5v, the transistor will be ON and design must insured that the network is heavily saturated by a level of IB greater than that associated if the IB curve appearing near the saturation level. In the above figure 9(b), this requires that IB > 50A. The saturation level for the collector current for the circuit is defined by, IC = VCC / RC The level of IB in the active region just before saturation results can be approximated by the following equation, IB max IC sat / dc For the saturation level we must therefore insure that the following condition is satisfied: IB max >IC sat / dc For the network of the above figure 9(b), when Vi = 5v the resulting level of IB is IB = Vi 0.7 / RB = 5v 0.7 / 1.5k = 2866A 19

IC sat = VCC / RC = 5v / 10k = 0.5mA Testing the above equation gives: IB =2866A > IC sat / dc = 0.5mA / 300 which is satisfied. Certainly any level of IB greater than 2866A will pass through a Q- point on the load line that is very close to the vertical axis. Circuit operation: In the fig-5, whenever the base voltage is HIGH the transistor comes to saturation condition i.e. the emitter current flows to the collector which gives a low voltage at the output corresponding to GND. The output is taken from the collector junction through a current limiting resistance and the output signal is given to the - controller or any other circuit which needs a compatible (5V/0V) voltage. Similarly, whenever the base voltage is LOW the collector current flows from the collector junction of the transistor, which gives a high voltage at the output corresponding to Vcc. The output is taken from the emitter junction through a current limiting resistance and the output signal is given to the - controller or any other circuit which needs a compatible (5V/0V) voltage. Finally that output signal is fed to the counter pin of the controller as an input signal.

d) LED Indicators:
In this sub-section its aspect is to indicate heart beat pulse. Here transistor is taken as a driver which is configured as a transistor switch to remove the loading effect between the microcontroller to the op-amp. The indicator section consists of a light emitting diode and its driver circuit is designed on the basis of current required to glow the light emitting diode. Here the driver circuit is required for the following functionality.

1) The Microcontroller cannot provide adequate current for glowing the LED. The LEDs requires a current between 10mA to 20mA of current to glow. 20

2) The driver circuit provides current to the load from a separate source, so the load current used not pass through the Microcontroller. 3) The driver circuit activates the load on receipt of a logic signal from the Microcontroller and of the load in the absence of the signal as the current requirement is very less to glow a LED a single stage driver is sufficient to drive the load. The driver circuit is nothing other than a perfect a transistor switch. The driver transistor goes into saturation on receipt of base signal and drives into cut-off region, in absence of base signal. The driver designs around a BC548/BC547 transistor and designed for a working voltage of +5 V dc and 10mA current.

Rc= Vcc-VCEsat IC = 4.8K

= 5-0.2V 10mA

Ib=Ic/=10mA/200=5x10-5 A=0.5x10-6A =0.5A

As per the design a 0.5A current is sufficient to trigger the driver circuit. As this current is very small and to avoid mistriggering a base current of 100A is assumed VB-IBRB-VBE=0 IBRB = 5-0.7 RB = 5-0.7V/100A = 4.3/100 M = 0.043x10-6 = 43K On approximation 68K is connected by calculating back IB = 4.3/68K = 60 70A This is adequate to avoid mistriggering level also this amount of current can be drawn from the Microcontroller without any problem.

21

e) Mother board:
The motherboard of this project is designed with a MSC 51 core compatible micro controller. The motherboard is designed on a printed circuit board, compatible for the micro controller. This board is consisting of a socket for micro controller, input /output pull-up registers; oscillator section and auto reset circuit.

Fig.(10)- figure showing micro controller

Micro controller core processor: Introduction:

Despite its relatively old age, the 89C51 is one of the most popular Micro controller in use today. Many derivatives Micro controllers have since been developed that are based on--and compatible with--the 8051. Thus, the ability to program an 89C51 is an important skill for anyone who plans to develop products that will take advantage of Micro controller. Many web pages, books, and tools are available for the 89C51 developer. The 89C51 has three very general types of memory. To effectively program the 8051 it is necessary to have a basic understanding of these memory types. The memory types are illustrated in the following graphic. They are: On-Chip Memory, External Code Memory, and External RAM.

22

Fig.(11)-micro controller chip processor On-Chip Memory refers to any memory (Code, RAM, or other) that physically exists on the Microcontroller itself. On-chip memory can be of several types, but we'll get into that shortly. External Code Memory is code (or program) memory that resides off-chip. This is often in the form of an external EPROM. External RAM is RAM memory that resides off-chip. This is often in the form of standard static RAM or flash RAM. Code Memory Code memory is the memory that holds the actual 8051 program that is to be run. This memory is limited to 64K and comes in many shapes and sizes: Code memory may be found on-chip, either burned into the Microcontroller as ROM or EPROM. Code may also be stored completely off-chip in an external ROM or, more commonly, an external EPROM. Flash RAM is also another popular method of storing a program. Various combinations of these memory types may also be used--that is to say, it is possible to have 4K of code memory on-chip and 64k of code memory off-chip in an EPROM. When the program is stored on-chip the 64K maximum is often reduced to 4k, 8k, or 16k. This varies depending on the version of the chip that is being used. Each version offers specific capabilities and one of the distinguishing factors from chip to chip is how much ROM/EPROM space the chip has. However, code memory is most commonly implemented as off-chip EPROM. This is especially true in low-cost development systems and in systems developed by students. 23

Programming Tip: Since code memory is restricted to 64K, 89C51 programs are limited to 64K. Some assemblers and compilers offer ways to get around this limit when used with specially wired hardware. However, without such special compilers and hardware, programs are limited to 64K.

External RAM As an obvious opposite of Internal RAM, the 89C51 also supports what is called External RAM. As the name suggests, External RAM is any random access memory which is found off-chip. Since the memory is off-chip it is not as flexible in terms of accessing, and is also slower. For example, to increment an Internal RAM location by 1 requires only 1 instruction and 1 instruction cycle. To increment a 1-byte value stored in External RAM requires 4 instructions and 7 instruction cycles. In this case, external memory is 7 times slower! Whatever External RAM loses in speed and flexibility it gains in quantity. While Internal RAM is limited to 128 bytes (256 bytes with an 8052), the 8051 supports External RAM up to 64K.

Programming Tip: The 8051 may only address 64k of RAM. To expand RAM beyond this limit requires programming and hardware tricks. You may have to do this "by hand" since many compilers and assemblers, while providing support for programs in excess of 64k, do not support more than 64k of RAM. This is rather strange since it has been my experience that programs can usually fit in 64k but often RAM is what is lacking. Thus if you need more than 64k of RAM, check to see if your compiler supports it-- but if it doesn't, be prepared to do it by hand.

On-Chip Memory As mentioned at the beginning of this chapter, the 89C51 includes a certain amount of on-chip memory. On-chip memory is really one of two types: Internal RAM and Special Function Register (SFR) memory. The layout of the 89C51's internal memory is presented in the following memory map:

24

Fig.(12)- memory map of 89C51s internal memory As is illustrated in this map, the 8051 has a bank of 128 bytes of Internal RAM. This Internal RAM is found on-chip on the 8051 so it is the fastest RAM available, and it is also the most flexible in terms of reading, writing, and modifying its contents. Internal RAM is volatile, so when the 8051 is reset this memory is cleared. The 128 bytes of internal ram is subdivided as shown on the memory map. The first 8 bytes (00h - 07h) are "register bank 0". By manipulating certain SFRs, a program may choose to use register banks 1, 2, or 3. These alternative register banks are located in internal RAM in addresses 08h through 1Fh. We'll discuss "register banks" more in a later chapter. For now it is sufficient to know that they "live" and are part of internal RAM. Bit Memory also lives and is part of internal RAM. We'll talk more about bit memory very shortly, but for now just keep in mind that bit memory actually resides in internal RAM, from addresses 20h through 2Fh. The 80 bytes remaining of Internal RAM, from addresses 30h through 7Fh, may be used by user variables that need to be accessed frequently or at high-speed. This area is also utilized by the Microcontroller as a storage area for the operating stack. This fact severely limits the 8051s stack since, as illustrated in the memory map, the area reserved for the stack is only 80 bytes-and usually it is less since these 80 bytes has to be shared between the stack and user variables.

25

SFR Descriptions There is different special function registers (SFR) designed inside the 89C51 micro controller. In this micro controller all the input, output ports, timer interrupts are controlled by the SFRs. The SFR functionalities are as follows. This section will endeavor to quickly overview each of the standard SFRs found in the above SFR chart map. It is not the intention of this section to fully explain the functionality of each SFR--this information will be covered in separate chapters of the tutorial. This section is to just give you a general idea of what each SFR does. P0 (Port 0, Address 80h, Bit-Addressable): This is input/output port 0. Each bit of this SFR corresponds to one of the pins on the Microcontroller. For example, bit 0 of port 0 is pin P0.0, bit 7 is pin P0.7. Writing a value of 1 to a bit of this SFR will send a high level on the corresponding I/O pin whereas a value of 0 will bring it to a low level. Programming Tip: While the 8051 has four I/O port (P0, P1, P2, and P3), if your hardware uses external RAM or external code memory (i.e., your program is stored in an external ROM or EPROM chip or if you are using external RAM chips) you may not use P0 or P2. This is because the 8051 uses ports P0 and P2 to address the external memory. Thus if you are using external RAM or code memory you may only use ports P1 and P3 for your own use. SP (Stack Pointer, Address 81h): This is the stack pointer of the Microcontroller. This SFR indicates where the next value to be taken from the stack will be read from in Internal RAM. If you push a value onto the stack, the value will be written to the address of SP + 1. That is to say, if SP holds the value 07h, a PUSH instruction will push the value onto the stack at address 08h. This SFR is modified by all instructions which modify the stack, such as PUSH, POP, LCALL, RET, RETI, and whenever interrupts are provoked by the Microcontroller. Programming Tip: The SP SFR, on startup, is initialized to 07h. This means the stack will start at 08h and start expanding upward in internal RAM. Since alternate register banks 1, 2, and 3 as well as the user bit variables occupy internal RAM from addresses 08h through 2Fh, it is necessary to initialize SP in your program to some other value if you will be using the alternate register banks and/or bit memory. It's not a bad idea to initialize SP to 2Fh as the first instruction of every one of your programs unless you are 100% sure you will not be using the register banks and bit variables.

26

DPL/DPH (Data Pointer Low/High, Addresses 82h/83h): The SFRs DPL and DPH work together to represent a 16-bit value called the Data Pointer. The data pointer is used in operations regarding external RAM and some instructions involving code memory. Since it is an unsigned two-byte integer value, it can represent values from 0000h to FFFFh (0 through 65,535 decimal). Programming Tip: DPTR is really DPH and DPL taken together as a 16-bit value. In reality, you almost always have to deal with DPTR one byte at a time. For example, to push DPTR onto the stack you must first push DPL and then DPH. You can't simply plush DPTR onto the stack. Additionally, there is an instruction to "increment DPTR." When you execute this instruction, the two bytes are operated upon as a 16-bit value. However, there is no instruction that decrements DPTR. If you wish to decrement the value of DPTR, you must write your own code to do so. PCON (Power Control, Addresses 87h): The Power Control SFR is used to control the 8051's power control modes. Certain operation modes of the 8051 allow the 8051 to go into a type of "sleep" mode, which requires much, less power. These modes of operation are controlled through PCON. Additionally, one of the bits in PCON is used to double the effective baud rate of the 8051's serial port. TCON (Timer Control, Addresses 88h, Bit-Addressable): The Timer Control SFR is used to configure and modify the way in which the 8051's two timers operate. This SFR controls whether each of the two timers is running or stopped and contains a flag to indicate that each timer has overflowed. Additionally, some non-timer related bits are located in the TCON SFR. These bits are used to configure the way in which the external interrupts are activated and also contain the external interrupt flags which are set when an external interrupt has occurred. TMOD (Timer Mode, Addresses 89h): The Timer Mode SFR is used to configure the mode of operation of each of the two timers. Using this SFR your program may configure each timer to be a 16-bit timer, an 8-bit auto reload timer, a 13-bit timer, or two separate timers. Additionally, you may configure the timers to only count when an external pin is activated or to count "events" that are indicated on an external pin. TL0/TH0 (Timer 0 Low/High, Addresses 8Ah/8Ch): These two SFRs, taken together, represent timer 0. Their exact behavior depends on how the timer is configured in the TMOD SFR; however, these timers always count up. What is configurable is how and when they increment in value. 27

TL1/TH1 (Timer 1 Low/High, Addresses 8Bh/8Dh): These two SFRs, taken together, represent timer 1. Their exact behavior depends on how the timer is configured in the TMOD SFR; however, these timers always count up. What is configurable is how and when they increment in value. P1 (Port 1, Address 90h, Bit-Addressable): This is input/output port 1. Each bit of this SFR corresponds to one of the pins on the Microcontroller. For example, bit 0 of port 1 is pin P1.0, bit 7 is pin P1.7. Writing a value of 1 to a bit of this SFR will send a high level on the corresponding I/O pin whereas a value of 0 will bring it to a low level. SCON (Serial Control, Addresses 98h, Bit-Addressable): The Serial Control SFR is used to configure the behavior of the 8051's on-board serial port. This SFR controls the baud rate of the serial port, whether the serial port is activated to receive data, and also contains flags that are set when a byte is successfully sent or received. Programming Tip: To use the 8051's on-board serial port, it is generally necessary to initialize the following SFRs: SCON, TCON, and TMOD. This is because SCON controls the serial port. However, in most cases the program will wish to use one of the timers to establish the serial port's baud rate. In this case, it is necessary to configure timer 1 by initializing TCON and TMOD. SBUF (Serial Control, Addresses 99h): The Serial Buffer SFR is used to send and receive data via the on-board serial port. Any value written to SBUF will be sent out the serial port's TXD pin. Likewise, any value which the 8051 receives via the serial port's RXD pin will be delivered to the user program via SBUF. In other words, SBUF serves as the output port when written to and as an input port when read from. P2 (Port 2, Address A0h, Bit-Addressable): This is input/output port 2. Each bit of this SFR corresponds to one of the pins on the Microcontroller. For example, bit 0 of port 2 is pin P2.0, bit 7 is pin P2.7. Writing a value of 1 to a bit of this SFR will send a high level on the corresponding I/O pin whereas a value of 0 will bring it to a low level. Programming Tip: While the 8051 has four I/O port (P0, P1, P2, and P3), if your hardware uses external RAM or external code memory (i.e., your program is stored in an external ROM or EPROM chip or if you are using external RAM chips) you may not use P0 or P2. This is because the 8051 uses ports P0 and P2 to address the external memory. Thus if you are using external RAM or code memory you may only use ports P1 and P3 for your own use. 28

IE (Interrupt Enable, Addresses A8h): The Interrupt Enable SFR is used to enable and disable specific interrupts. The low 7 bits of the SFR are used to enable/disable the specific interrupts, where as the highest bit is used to enable or disable ALL interrupts. Thus, if the high bit of IE is 0 all interrupts are disabled regardless of whether an individual interrupt is enabled by setting a lower bit. P3 (Port 3, Address B0h, Bit-Addressable): This is input/output port 3. Each bit of this SFR corresponds to one of the pins on the Micro controller. For example, bit 0 of port 3 is pin P3.0, bit 7 is pin P3.7. Writing a value of 1 to a bit of this SFR will send a high level on the corresponding I/O pin whereas a value of 0 will bring it to a low level.

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Fig.(13)- hardware description of 80C51 micro controller

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Auto reset Circuit:

MICROCONTROLLER
39 38 37 36 35 34 33 32 1 2 3 4 5 6 7 8 P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 XTAL1 XTAL2 EA/VPP RST P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 P3.0/RXD P3.1/TXD P3.2/IN T0 P3.3/IN T1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD ALE/PROG PSEN 21 22 23 24 25 26 27 28 10 11 12 13 14 15 16 17 30 29

22pF 4 - 12Mhz

19 18 31 9

22pF

VCC =+5vdc

AT89C51

10uF RST

8.2k

Fig.(14)- auto reset circuit The auto reset circuit is a RC network as shown in the mother board circuit diagram. A capacitor of 1-10mfd is connected in series with a 8k2 resister the R-C junction is connected to the micro controller pin 9 which is reset pin. The reset pin is one when ever kept high( logic 1) the program counter (PC) content resets to 0000h so the processor starts executing the program from that location. Whenever the system is switched ON the mother board gets power and the capacitor acts as short circuit and the entire voltage appears across the resistor, so the reset pin get a logic 1 and the system get reset, whenever it is being switched ON.

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Pull-UP Resisters:

VCC =+5V

10k

PORT-0

39 38 37 36 35 34 33 32 1 2 3 4 5 6 7 8 19 18 31 9

P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 XTAL1 XTAL2 EA/VPP RST

P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 P3.0/RXD P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD ALE/PROG PSEN

21 22 23 24 25 26 27 28 10 11 12 13 14 15 16 17 30 29

AT89C51
Fig.(15)- AT89C51 showing connection of pull-up resisters

The PORT0 and PORT2 of the MCS-51 architecture is of open collector type so on writing logic 0 the pins are providing a perfect ground potential whereas on writing logic 1 the port pins behaves as high impedance condition so putting a pull-up resister enables the port to provide a +5volt (logic 1). Port1 and Port3 are provided with internal pull-ups. A pull-up resister is

normally a 10K resistance connected from the port pin to the Vcc (+5) volt. MICROCONTROLLER PROGRAM:$mod51 org 0000h ljmp main org 0003h ;mov ie, #10010000b ;acall scan

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;mov ie, #10010001b reti org 0023h ;mov ie, #00h ;mov ie, #10010000b reti org 0050h main: acall init clr 05 mov dptr,#msg1 acall acall acall acall msgtx delay delay sms2

nex: acall delay acall delay ;mov p0, #00h mov r0, #50h mov dptr, #msg3 nx4: clr a movc a, @a+dptr mov @r0, a jz xz1 inc r0 sjmp nx4 mov r0, #40h xz0: acall init mov ie, #10010000b xz1: jnb p3.2, xz1 xz2: jb p3.2, xz2 ;mov ie, #00h ;acall chk_1 ;cjne a, #'R', xz0 ;acall delay acall delay ;mov ie,#10010000b ;acall ch0 acall hbc acall delay acall sms1 ;acall fill ;mov r0, #40h sjmp xz0 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;SUB ROUTINES ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

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rec: jb ti,re1 mov a,sbuf mov @r0,a inc r0 clr ri ret re1: clr ti ret cc: sms1: mov dptr,#msg1 acall acall acall acall msgtx delay delay delay

mov dptr,#msg2 acall acall acall acall msgtx delay delay delay

;mov dptr,#msg3 mov r0, #50h nx6: mov a, @r0 jz ex5 acall tx sjmp nx6 ex5: ;acall msgtx acall delay acall delay acall delay ret sms2: mov dptr,#msg1 acall acall acall acall msgtx delay delay delay

mov dptr,#msg2 acall msgtx

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acall delay acall delay acall delay mov dptr,#msg7 acall acall acall acall ret init: mov p0, #0ffh mov p1, #0ffh mov p2, #0ffh ;setb p2.4 mov a,#38h ;intialise lcd 2 line 5*7 matrix acall cmd acall delay mov a,#0Eh ;display on curser on acall cmd acall delay mov a,#01 ;clear lcd acall cmd acall delay mov a,#06h ;shiftcurser right acall cmd mov a,#80h acall cmd mov dptr, #msg4 acall msgrd mov a,#0c0h acall cmd mov dptr, #msg5 acall msgrd setb p3.0 setb p3.1 setb p3.4 ;mov tmod,#20h mov tmod,#00100101b mov scon,#50h mov th1,#-3 mov ie,#10010000b setb tr1 clr tr0 clr ri clr ti ret hbc: mov tl0,#00h msgtx delay delay delay

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setb tr0 mov b, #02d acall delay_rp mov a,tl0 clr tr0 acall conv mov 63h, r4 mov 64h, r3 mov 65h, r2 mov a, #0cdh acall cmd mov a, r4 acall dat mov a, r3 acall dat mov a, r2 acall dat ;mul ab mov tl0, #00h ret delay_rp: setb psw.4 setb psw.3 w: y: t: s:

; 63

mov r0,#125d mov r1,#60d mov r2,#5d mov r3,#240d djnz r3,s djnz r2,t djnz r1,y djnz r0,w clr psw.3 clr psw.4 ret

ch0: ;mov a, #06h ;acall tx mov a, p2 acall conv mov 55h, r4 mov 56h, r3 mov 57h, r2 mov a, #0c5h ;ADC DATA BITS

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acall cmd mov a, r4 acall dat mov a, r3 acall dat mov a, r2 acall dat ret

msgrd: ag1: clr a movc a, @a+dptr jz exit acall dat inc dptr sjmp ag1 exit: ret

msgtx: ag2: clr a movc a, @a+dptr jz exi1 acall tx inc dptr sjmp ag2 exi1: ret tx: mov sbuf, a wait: jnb ti, wait ;acall delays clr ti ret cmd: ;acall ready mov p1,a

37

clr p3.5 clr p3.6 setb p3.7 acall delay_k clr p3.7 ret dat: ;acall ready mov p1,a setb p3.5 clr p3.6 setb p3.7 acall delay_k clr p3.7 ret

; P1: Data bus LCD

delay_k: setb psw.3 setb psw.4 mov r3, #200d l1: mov r4, #100d loop: djnz r4, loop djnz r3, l1 clr psw.3 clr psw.4 ret delays: setb psw.3 setb psw.4 mov r0, #125d xa31: mov r1, #60d xa21: mov r2, #10d xa11: djnz r2, xa11 djnz r1, xa21 djnz r0, xa31 clr psw.3 clr psw.4

delay: using 2 setb psw.3 setb psw.4 mov r0, #125d xa3: mov r1, #100d xa2: mov r2, #50d

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xa1: djnz r2, xa1 djnz r1, xa2 djnz r0, xa3 clr psw.3 clr psw.4 using 0 ret delay1: setb psw.3 setb psw.4 mov r7, #125d z01: mov r6, #100d y01: mov r5, #50d x02: djnz r5, x02 djnz r6, y01 djnz r7, z01 clr psw.3 clr psw.4 ret delay_adc: setb psw.3 setb psw.4 mov r7, #125d z1: mov r6, #100d y1: mov r5, #100d x2: djnz r5, x2 djnz r6, y1 djnz r7, z1 clr psw.3 clr psw.4 ret conv: ;mov a,r0 mov div add mov mov mov div add mov mov add mov ret b,#100d ab a, #30h r4, a a,b b, #10d ab a,#30h r3,a a,b a,#30h r2,a

39

org 0300h db 41h,54h,2bh,43h,4dh,47h,46h,3dh,31h,0dh db 0 msg2: db 41h,54h,2bh,43h,4dh,47h,53h,3dh,22h,'9437301863',22h,0dh db 0 msg3: db 'Heart Beats / min= ',1ah db 0 msg4: msg5: ;msg6: ;db 0 ;msg8: ;db 0 msg7: db 'The System Is Ready to accept command',1ah db 0 ;msg2: db 'AT+CMGF=1\n' ;db 0 ;msg3: db 'AT+CMGS=\"9437301863\"\n' db 0 ;msg4: db 'yes' db 0 ;msg5: db 1ah db 0 end db 'Over Speed Fault',1ah db ' Patient Monitor ' db 0 db ' db 0 HB/M ' msg1:

db 'Over Temperature Fault',1ah

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Crystal Oscillator The 8051 family microcontroller contains an inbuilt crystal oscillator, but the crystal has to be connected externally. This family of microcontroller can support 0 to 24MHz crystal and two numbers of decoupling capacitors are connected as shown in the figure. These capacitors are decouples the charges developed on the crystal surface due to piezoelectric effect. These

decoupling capacitors are normally between 20pf to 30pf. The clock generator section is designed as follows,

Fig.(16)- Crystal Oscillator The Microcontroller design consist of two parts 1. Hardware. 2. Software. HARDWARE: The controller operates on +5 V dc, so the regulated + 5v is supplied to pin no. 40 and ground at pin no. 20. The controller is used here need not required to handle high frequency signals, so as 4 MHz crystal is used for operating the processor. The pin no. 9 is supplied with a +5V dc through a push switch. To reset the processor .As prepare codes are store in the internal flash memory the pin no. 31 is connected to + Vcc. Software: Port-0 is taken as output port for the LCD data bits (p0.0--------------p0.7) Port-2 is taken as I/O port for the LCD control bits (P2.0-RS, P2.1-R/W & P2.2-EN).

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Port -3 is taken as output port from Heart beat and SIU P3.2 (INT0) is from mono-shot and P3.4 is for Heart beat. P3.0 (RxD) & P3.1 (TxD) is used as I/O port for the serial interface unit.

f) LCD Interface Unit:

In this sub section its aspect is to display the status of the body parameter (Temperature and Heart beat) through a alphanumeric display. Here a 2 line and 16 characters are taken as a LCD. Frequently, an 8050/8052 program must interact with the outside world using input and output devices that communicate directly with a human being. One of the most common devices attached to an 8051/8052 is an LCD display. Some of the most common LCDs connected to the 8050/8052 are 16x2 and 20x2 displays. This means 16 characters per line by 2 line and 20 characters per line by 2 lines, respectively. A LCD is a thin, flat display device made up of any number of color or monochrome pixels arrayed in front of a light source or reflector. It uses very small amounts of electric power, and is therefore suitable for use in battery powered electronic devices. Each pixel consists of s column of liquid crystal molecules suspended between two transparent electrodes, and two polarizing filters, the axes of polarity of which are perpendicular to each other. Without the liquid crystals between them, light passing through one would be blocked by the other. The liquid crystal twists the polarization of light entering one filter to allow it to pass through the other. More microcontroller devices are using smart LCD display to output visual information. Fortunately, a very popular standard exits which allows us to communicate with the vast majority of LCDs regardless of their manufacture. For an 8-bit data bus, the display requires a +5V supply plus 11 I/O lines. For a 4-bit data bus it only requires the supply lines plus seven extra lines. When the LCD display is not enabled, data lines are tri-state which means they are in a state of high impedance (as though they are disconnected) and this means they do not interface with the operation of the microcontroller when the display is not being addressed. In LCD we can put data at any location. For 16x2 LCD, the address locations are:

1. Ground 2. Vcc (+3.3 to +5V) 3. contrast adjustment (VE) 4. Register select (RS). RS=0:Command, RS=1:Data 42

5. Read/Write (R/W). R/W=0:Write,R/W=1:Read 6. clock (enable). Falling edge triggered 7. DB0 Data bus LSB 8. DB1 9. DB2 10. DB3 11. DB4 12. DB5 13. DB6 14. DB7- Data bus MSB 15. Backlight anode(+) 16. Backlight cathode (-) Signals to the LCD Enable (E): This line allows access to the display through R/W and RS lines. When this line is low, the LCD is disabled and ignores signals from R/W and RS. When (E) line is high, the LCD checks the state of the two control lines and responds accordingly. Read/Write (R/W): This line determines the direction of data between the LCD and microcontroller. When it is low, data is written to the LCD. When it is high, data is read from the LCD. Register Select (RS): With the help of this line, the LCD interprets the type of data on data lines. When it is low, an instruction is being written to the LCD. When it is high, a character is being written to the LCD. Logic status on control lines E 0 Access to LCD disabled 1 Access to LCD enabled R/W 0 Writing data to LCD 1 Reading data from LCD RS 0 Instructions 1 Character Writing & Reading the data from the LCD 43

 writing data to the LCD is done in several steps: 1) set R/W bit to low 2) set RS bit to logic 0 or 1 (instruction or character) 3) set data to data lines (if it is writing) 4) set E line to High 5) set E line to Low Read data from data lines (if it is reading): 1) Set R/W bit to High 2) set RS bit to logic 0 or 1 (instruction or character) 3) set data to data lines (if it is writing) 4) set E line to High 5) set E line to Low

Fig.(17)-LCD Display

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g) Serial Interface Unit:

In this sub section its aspect is to convert the TTL output standard from the controller to CMOS standard which will be compatible with the GSM Modem, for that a serial interface unit is required which will convert the TTL output standard to CMOS output standard and vice versa.

Fig.(18)-Serial Interface Unit

Introduction:
Serial port is a popular means of transmitting data between a computer and a peripheral device such as a programmable instrument or even another computer. Serial communication uses a transmitter to send data, one bit at a time, over a single communication line to a receiver. You can use this method when data transfer rates are low or you must transfer data over long distances. Serial communication is popular because most computers have one or more serial

45

ports, so no extra hardware is needed other than a cable to connect the instrument to the computer or two computers together.

Fig.(19): RS-232 Instrument,2: RS-232 Cable, 3: Serial Port

Serial communication requires that you specify the following four parameters:

The baud rate of the transmission The number of data bits encoding a character The sense of the optional parity bit The number of stop bits

Each transmitted character is packaged in a character frame that consists of a single start bit followed by the data bits, the optional parity bit, and the stop bit or bits. Fig.(20) shows a typical character frame encoding the letter m.

46

Fig.(20)- character frame Baud rate is a measure of how fast data are moving between instruments that use serial communication. RS-232 uses only two voltage states, called MARK and SPACE. In such a two-state coding scheme, the baud rate is identical to the maximum number of bits of information, including control bits that are transmitted per second.
Mark

is a negative voltage, and SPACE is positive. Fig.(20) shows how the idealized signal looks

on an oscilloscope. The following is the truth table for RS-232: Signal>3V=0 Signal>-3V=1 The output signal level usually swings between +12 V and -12 V. The dead area between +3 V and -3 V is designed to absorb line noise. A start bit signals the beginning of each character frame. It is a transition from negative (MARK) to positive (SPACE) voltage. Its duration in seconds is the reciprocal of the baud rate. If the instrument is transmitting at 9,600 baud, the duration of the start bit and each subsequent bit is about 0.104 ms. The entire character frame of eleven bits would be transmitted in about 1.146 ms. Data bits are transmitted upside down and backwards. That is, inverted logic is used, and the order of transmission is from least significant bit (LSB) to most significant bit (MSB). To interpret the data bits in a character frame, you must read from right to left and read 1 for negative voltage and 0 for positive voltage. This yields 1101101 (binary) or 6D (hex). An ASCII conversion table shows that this is the letter m.

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An optional parity bit follows the data bits in the character frame. The parity bit, if present, also follows inverted logic, 1 for negative voltage and 0 for positive voltage. This bit is included as a simple means of error handling. You specify ahead of time whether the parity of the transmission is to be even or odd. If the parity is chosen to be odd, the transmitter then sets the parity bit in such a way as to make an odd number of ones among the data bits and the parity bit. This transmission uses odd parity. There are five ones among the data bits, already an odd number, so the parity bit is set to 0. The last part of a character frame consists of 1, 1.5, or 2 stop bits. These bits are always represented by a negative voltage. If no further characters are transmitted, the line stays in the negative (MARK) condition. The transmission of the next character frame, if any, is heralded by a start bit of positive (SPACE) voltage.

Fig.(21)- MAX232

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RS-232 Waveforms
So far we have introduced RS-232 Communications in relation to the PC. RS-232 communication is asynchronous. That is a clock signal is not sent with the data. Each word is synchronized using it's start bit, and an internal clock on each side, keeps tabs on the timing.

Figure 22 : TTL/CMOS Serial Logic Waveform The diagram above, shows the expected waveform from the UART when using the common 8N1 format. 8N1 signifies 8 Data bits, No Parity and 1 Stop Bit. The RS-232 line, when idle is in the Mark State (Logic 1). A transmission starts with a start bit which is (Logic 0). Then each bit is sent down the line, one at a time. The LSB (Least Significant Bit) is sent first. A Stop Bit (Logic 1) is then appended to the signal to make up the transmission. The diagram shows the next bit after the Stop Bit to be Logic 0. This must mean another word is following, and this is it's Start Bit. If there is no more data coming then the receive line will stay in it's idle state(logic 1). We have encountered something called a "Break" Signal. This is when the data line is held in a Logic 0 state for a time long enough to send an entire word. Therefore if you don't put the line back into an idle state, then the receiving end will interpret this as a break signal. The data sent using this method, is said to be framed. That is the data is framed between a Start and Stop Bit. Should the Stop Bit be received as a Logic 0, then a framing error will occur. This is common, when both sides are communicating at different speeds. The above diagram is only relevant for the signal immediately at the UART. RS-232 logic levels uses +3 to +25 volts to signify a "Space" (Logic 0) and -3 to -25 volts for a "Mark" (logic 1). Any voltage in between these regions ( i.e, between +3 and -3 Volts) is undefined. Therefore this

49

signal is put through a "RS-232 Level Converter". This is the signal present on the RS-232 Port of your computer, shown below.

Figure 23 : RS-232 Logic Waveform

The above waveform applies to the Transmit and Receive lines on the RS-232 port. These lines carry serial data, hence the name Serial Port. There are other lines on the RS-232 port which, in essence are Parallel lines. These lines (RTS, CTS, DCD, DSR, DTR, RTS and RI) are also at RS-232 Logic Levels.

RS-232 Cabling
Devices that use serial cables for their communication are split into two categories. These are DCE and DTE. DCE are devices such as a modem, TA adapter, plotter, and so on, while DTE is a computer or terminal. RS-232 serial ports come in two sizes, the D-Type 25-pin connector and the D-Type 9-pin connector. Both of these connectors are male on the back of the PC. Thus, you require a female connector on the device. Table 1 shows the pin connections for the 9-pin and 25-pin D-Type connectors.

Fig. 24- D-Type 9-pin connector Function Signal PIN DTE DCE

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TxD Data RxD RTS CTS Handshake DSR DCD STR Common Other Com RI

3 2 7 8 6 1 4 5 9 Table 1

Output Input Output Input Input Input Output -Output

Input Output Input Output Output Output Input -Input

The DB-9 connector is occasionally found on smaller RS-232 lab equipment. It is compact, yet has enough pins for the core set of serial pins (with one pin extra). Note: The DB-9 pin numbers for transmit and receive (3 and 2) are opposite of those on the DB-25 connector (2 and 3). Be careful of this difference when you are determining if a device is DTE or DCE.

RS232 bit streams

The RS232 standard describes a communication method where information is sent bit by bit on a physical channel. The information must be broken up in data words. The length of a data word is variable. On PC's a length between 5 and 8 bits can be selected. This length is the net to information length of each word. For proper transfer additional bits are added for synchronization and error checking purposes. It is important, that the transmitter and receiver use the same number of bits. Otherwise, the data word may be misinterpreted, or not recognized at all. With synchronous communication, a clock or trigger signal must be present which indicates the beginning of each transfer. The absence of a clock signal makes an asynchronous communication channel cheaper to operate. Less line is necessary in the cable. A disadvantage is that the receiver can start at the wrong moment receiving the information. Resynchronization is then needed 51

which costs time. All data received in the resynchronization period is lost. Another disadvantage is that extra bits are needed in the data stream to indicate the start and end of useful information. These extra bits take up bandwidth. Data bits are sent with a predefined frequency, the baud rate. Both the transmitter and receiver must be programmed to use the same bit frequency. After the first bit is received, the receiver calculates at which moments the other data bits will be received. It will check the line voltage levels at those moments. With RS232, the line voltage level can have two states. The on state is also known as mark, the off state as space. No other line states are possible. When the line is idle, it is kept in the mark state. Start bit RS232 defines an asynchronous type of communication. This means, that sending of a data word can start on each moment. If starting at each moment is possible, this can pose some problems for the receiver to know which the first bit to receive is. To overcome this problem, each data word is started with an attention bit. This attention bit, also known as the start bit, is always identified by the space line level. Because the line is in mark state when idle, the start bit is easily recognized by the receiver. Data bits Directly following the start bit, the data bits are sent. A bit value 1 causes the line to go in mark state, the bit value 0 is represented by a space. The least significant bit is always the first bit sent. Parity bit For error detecting purposes, it is possible to add an extra bit to the data word automatically. The transmitter calculates the value of the bit depending on the information sent. The receiver performs the same calculation and checks if the actual parity bit value corresponds to the calculated value.

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Stop bits Suppose that the receiver has missed the start bit because of noise on the transmission line. It started on the first following data bit with a space value. This causes garbled date to reach the receiver. A mechanism must be present to resynchronize the communication. To do this, framing is introduced. Framing means, that all the data bits and parity bit are contained in a frame of start and stop bits. The period of time lying between the start and stop bits is a constant defined by the baud rate and number of data and parity bits. The start bit has always space value, the stop bit always mark value. If the receiver detects a value other than mark when the stop bit should be present on the line, it knows that there is a synchronization failure. This causes a framing error condition in the receiving UART. The device then tries to resynchronize on new incomming bits. For resynchronizing, the receiver scans the incomming data for valid start and stop bit pairs. This works, as long as there is enough variation in the bit patterns of the data words. If data value zero is sent repeatedly, resynchronization is not possible for example. The stop bit identifying the end of a data frame can have different lengths. Actually, it is not a real bit but a minimum period of time the line must be idle (mark state) at the end of each word. On PC's this period can have three lengths: the time equal to 1, 1.5 or 2 bits. 1.5 bits is only used with data words of 5 bits length and 2 only for longer words. A stop bit length of 1 bit is possible for all data word sizes.

RS232 physical properties

The RS232 standard describes a communication method capable of communicating in different environments. This has had its impact on the maximum allowable voltages etc. on the pins. In the original definition, the technical possibilities of that time were taken into account. The maximum baud rate defined for example is 20 kbps. With current devices like the 16550A UART, maximum speeds of 1.5 Mbps are allowed.

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Voltages The signal level of the RS232 pins can have two states. A high bit, or mark state is identified by a negative voltage and a low bit or space state uses a positive value. This might be a bit confusing, because in normal circumstances, high logical values are defined by high voltages also. The voltage limits are shown below.
RS232 voltage values

Level

Transmitter capable (V) +5 ... +15 -5 ... -15 -

Receiver capable (V) +3 ... +25 -3 ... -25 -3 ... +3

Space state (0) Mark state (1) Undefined

More information about the voltage levels of RS232 and other serial interfaces can be found in the interface comparison table. The maximum voltage swing the computer can generate on its port can have influence on the maximum cable length and communication speed that is allowed. Also, if the voltage difference is small, data distortion will occur sooner. For example, my Toshiba laptop mark's voltage is 9.3 V, compared to -11.5 V on my desktop computer. The laptop has difficulties to communicate with Mitsubishi PLC's in industrial environments with high noise levels where the desktop computer has no data errors at all using the same cable. Thus, even far beyond the minimum voltage levels, 2 volts extra can make a huge difference in communication quality. Despite the high voltages present, it is not possible to destroy the serial port by short circuiting. Only applying external voltages with high currents may eventually burn out the driver chips. Still then, the UART won't be damaged in most cases.

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Maximum cable lengths Cable length is one of the most discussed items in RS232 world. The standard has a clear answer, the maximum cable length is 50 feet, or the cable length equal to a capacitance of 2500 pF. The latter rule is often forgotten. This means that using a cable with low capacitance allows you to span longer distances without going beyond the limitations of the standard. If for example UTP CAT-5 cable is used with a typical capacitance of 17 pF/ft, the maximum allowed cable length is 147 feet. The cable length mentioned in the standard allows maximum communication speed to occur. If speed is reduced by a factor 2 or 4, the maximum length increases dramatically. Texas Instruments has done some practical experiments years ago at different baud rates to test the maximum allowed cable lengths. Keep in mind, that the RS232 standard was originally developed for 20 kbps. By halving the maximum communication speed, the allowed cable length increases a factor ten!
RS232 cable length according to Texas Instruments

Baud rate 19200 9600 4800 2400

Maximum cable length (ft) 50 500 1000 3000

Even parity Basically, the parity bit can be calculated in two ways. When even parity is used, the number of information bits sent will always contain an even number of logical 1's. If the number of high data bits is odd, a high value parity bit is added, otherwise a low bit will be used.

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Odd parity The odd parity system is quite similar to the even parity system, but in this situation, the number of high bits will always be odd.

RS-232 Level Converters

Almost all digital devices which we use require either TTL or CMOS logic levels. Therefore the first step to connecting a device to the RS-232 port is to transform the RS-232 levels back into 0 and 5 Volts. As we have already covered, this is done by RS-232 Level Converters. Two common RS-232 Level Converters are the 1488 RS-232 Driver and the 1489 RS-232 Receiver. Each package contains 4 inverters of the one type, either Drivers or Receivers. The driver requires two supply rails, +7.5 to +15v and -7.5 to -15v. As you could imagine this may pose a problem in many instances where only a single supply of +5V is present. However the advantages of these I.C's are they are cheap.

Above: (Figure 6) Pinouts for the MAX-232, RS-232 Driver/Receiver.

Right: (Figure 25) Typical MAX-232 Circuit.

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Another device is the MAX-232. It includes a Charge Pump, which generates +10V and -10V from a single 5v supply. This I.C. also includes two receivers and two transmitters in the same package. This is handy in many cases when you only want to use the Transmit and Receive data Lines. You don't need to use two chips, one for the receive line and one for the transmit. However all this convenience comes at a price, but compared with the price of designing a new power supply it is very cheap. There are also many variations of these devices. The large value of capacitors are not only bulky, but also expensive. Therefore other devices are available which use smaller capacitors and even some with inbuilt capacitors. (Note: Some MAX-232's can use 1 micro farad Capacitors). However the MAX-232 is the most common, and thus we will use this RS-232 Level Converter in our examples.

h) Mono-stable Multivibrator:
In this sub section its aspect is to generate a logic HIGH pulse whenever the data is available or received by the GSM Modem. Thus that signal is synchronized with the controller of timer or counter pin. Here the timer IC (NE555) is configured as a Monostable Multivibrator and is time period is determined by potentiometer VR1 and capacitor C. By adjusting potentiometer VR1, we can vary the time period.

Fig.(26)- monostable multivibrator 57

A monostable multivibrator (MMV) often called a one-shot multivibrator, is a pulse generator circuit in which the duration of the pulse is determined by the R-C network, connected externally to the 555 timer. In such a vibrator, one state of output is stable while the other is quasi-stable (unstable). For auto-triggering of output from quasi-stable state to stable state energy is stored by an externally connected capacitor C to a reference level. The time taken in storage determines the pulse width. The transition of output from stable state to quasi-stable state is accomplished by external triggering. The schematic of a 555 timer in monostable mode of operation is shown in figure.

Fig.(27)-555-timer-monostable-multivibrator

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Monostable Multivibrator Circuit details

Pin 1 is grounded. Trigger input is applied to pin 2. In quiescent condition of output this input is kept at + VCC. To obtain transition of output from stable state to quasi-stable state, a negativegoing pulse of narrow width (a width smaller than expected pulse width of output waveform) and amplitude of greater than + 2/3 VCC is applied to pin 2. Output is taken from pin 3. Pin 4 is usually connected to + VCC to avoid accidental reset. Pin 5 is grounded through a 0.01 u F capacitor to avoid noise problem. Pin 6 (threshold) is shorted to pin 7. A resistor R A is connected between pins 6 and 8. At pins 7 a discharge capacitor is connected while pin 8 is connected to supply VCC.

555 IC Monostable Multivibrator Operation

Fig.(28-)555 monostable-multivibrator-operation 59

For explaining the operation of timer 555 as a Monostable Multivibrator, necessary internal circuitry with external connections is shown in figure.

The operation of the circuit is explained below:

Initially, when the output at pin 3 is low i.e. the circuit is in a stable state, the transistor is on and capacitor- C is shorted to ground. When a negative pulse is applied to pin 2, the trigger input falls below +1/3 VCC, the output of comparator goes high which resets the flip-flop and consequently the transistor turns off and the output at pin 3 goes high. This is the transition of the output from stable to quasi-stable state, as shown in figure. As the discharge transistor is cutoff, the capacitor C begins charging toward +VCC through resistance RA with a time constant equal to RAC. When the increasing capacitor voltage becomes slightly greater than +2/3 VCC, the output of comparator 1 goes high, which sets the flip-flop. The transistor goes to saturation, thereby discharging the capacitor C and the output of the timer goes low, as illustrated in figure. Thus the output returns back to stable state from quasi-stable state. The output of the Monostable Multivibrator remains low until a trigger pulse is again applied. Then the cycle repeats. Trigger input, output voltage and capacitor voltage waveforms are shown in figure.

Monostable Multivibrator Design Using 555 timer IC

The capacitor C has to charge through resistance RA. The larger the time constant RAC, the longer it takes for the capacitor voltage to reach +2/3VCC.In other words, the RC time constant controls the width of the output pulse. The time during which the timer output remains high is given as tp = 1.0986 RAC

where RA is in ohms and C is in farads. The above relation is derived as below. Voltage across the capacitor at any instant during charging period is given as vc = VCC (1- e-t/RAC) Substituting vc = 2/3 VCC in above equation we get the time taken by the capacitor to charge from 0 to +2/3VCC. 60

So +2/3VCC. = VCC. (1 e-t/RAC) or t RAC loge 3 = 1.0986 RAC So pulse width, tP = 1.0986 RAC s 1.1 RAC The pulse width of the circuit may range from micro-seconds to many seconds. Finally that output signal is fed to the controller as a input signal to the interrupt (p3.2) pin of microcontroller

i) GSM Modem: GSM (Global System for Mobile Communication)Modem:

A modem (modulator-demodulator) is a device that modulates an analog carrier signal to encode digital information, and also demodulates such a carrier signal to decode the transmitted information. The goal is to produce a signal that can be transmitted easily and decoded to reproduce the original digital data. A GSM modem is a specialized type of modem which accepts a SIM card, and operates over a subscription to a mobile operator, just like a mobile phone. From the mobile operator perspective, a GSM modem looks just like a mobile phone. A dedicated GSM modem (external or PC Card) is usually preferable to a GSM mobile phone. This is because of some compatibility issues that can exist with mobile phones. For example, if you wish to be able to receive inbound MMS messages with your gateway, and you are using a mobile phone as your modem, you must utilize a mobile phone that does not support WAP push or MMS. This is because the mobile phone automatically processes these messages, without forwarding them via the modem interface. Similarly some mobile phones will not allow you to correctly receive SMS text messages longer than 160 bytes (known as concatenated SMS or long SMS). This is because these long messages are actually sent as separate SMS messages, and the phone attempts to reassemble the message before forwarding via the modem interface.

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Fig(29)-GSM Modem

Architecture of GSM network A GSM network is composed of several functional entities, whose functions and interfaces are specified. Figure 1 shows the layout of a generic GSM network. The GSM network can be divided into three broad parts. The Mobile Station is carried by the subscriber. The Base Station Subsystem controls the radio link with the Mobile Station. The Network Subsystem, the main part of which is the Mobile services Switching Center (MSC), performs the switching of calls between the mobile users, and between mobile and fixed network users. The MSC also handles the mobility management operations. Not shown are the Operations A GSM network is composed of several functional entities, whose functions and interfaces are specified. Figure shows the layout of a generic GSM network. The GSM network can be divided into three broad parts. Subscriber carries the Mobile Station. The Base Station Subsystem controls the radio link with the Mobile Station. The Network Subsystem, the main part of which is the Mobile services Switching Center (MSC), performs the switching of calls between the mobile users, and between mobile and fixed network users. The MSC also handles 62

the mobility management operations. Not shown is the Operations intendance Center, which oversees the proper operation and setup of the network. The Mobile Station and the Base Station Subsystem communicate across the Um interface, also known as the air interface or radio link. The Base Station Subsystem communicates with the Mobile services Switching Center across the A interface.

Fig 30- General architecture of a GSM network

Mobile Station: The mobile station (MS) consists of the mobile equipment (the terminal) and a smart card called the Subscriber Identity Module (SIM). The SIM provides personal mobility, so that the user can have access to subscribed services irrespective of a specific terminal. By inserting the SIM card into another GSM terminal, the user is able to receive calls at that terminal, make calls from that terminal, and receive other subscribed services. The mobile equipment is uniquely identified by the International Mobile Equipment Identity (IMEI). The SIM card contains the International Mobile Subscriber Identity (IMSI) used to identify the subscriber to the system, a secret key for authentication, and other information. The IMEI and the IMSI are independent, thereby allowing personal mobility. The SIM card may be protected against unauthorized use by a password or personal identity number. Base Station Subsystem: The Base Station Subsystem is composed of two parts, the Base Transceiver Station (BTS) and the Base Station Controller (BSC). These communicate across the standardized Abis

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interface, allowing (as in the rest of the system) operation between components made by different suppliers. The Base Transceiver Station houses the radio transceivers that define a cell and handles the radio-link protocols with the Mobile Station. In a large urban area, there will potentially be a large number of BTSs deployed, thus the requirements for a BTS are ruggedness, reliability, portability, and minimum cost. The Base Station Controller manages the radio resources for one or more BTSs. It handles radio-channel setup, frequency hopping, and handovers, as described below. The BSC is the connection between the mobile station and the Mobile service Switching Center (MSC). Network Subsystem The central component of the Network Subsystem is the Mobile services Switching Center (MSC). It acts like a normal switching node of the PSTN or ISDN, and additionally provides all the functionality needed to handle a mobile subscriber, such as registration, authentication, location updating, handovers, and call routing to a roaming subscriber. These services are provided in conjunction with several functional entities, which together form the Network Subsystem. The MSC provides the connection to the fixed networks (such as the PSTN or ISDN). Signalling between functional entities in the Network Subsystem uses signalling System Number 7 (SS7), used for trunk signalling in ISDN and widely used in current public networks. The Home Location Register (HLR) and Visitor Location Register (VLR), together with the MSC, provide the call-routing and roaming capabilities of GSM. The HLR contains all the administrative information of each subscriber registered in the corresponding GSM network, along with the current location of the mobile. The location of the mobile is typically in the form of the signaling address of the VLR associated with the mobile as a distributed database station. The actual routing procedure will be described later. There is logically one HLR per GSM network, although it may be implemented The Visitor Location Register (VLR) contains selected administrative information from the HLR, necessary for call control and provision of the subscribed services, for each mobile currently located in the geographical area controlled by the VLR. Although each functional entity can be implemented as an independent unit, all manufacturers of switching equipment to date implement the VLR together with the MSC, so that the geographical area controlled by the 64

MSC corresponds to that controlled by the VLR, thus simplifying the signalling required. Note that the MSC contains no information about particular mobile stations --- this information is stored in the location registers. The other two registers are used for authentication and security purposes. The Equipment Identity Register (EIR) is a database that contains a list of all valid mobile equipment on the network, where each mobile station is identified by its International Mobile Equipment Identity (IMEI). An IMEI is marked as invalid if it has been reported stolen or is not type approved. The Authentication Center (AuC) is a protected database that stores a copy of the secret key stored in each subscriber's SIM card, which is used for authentication and encryption over the radio channel.

Smart modem(GSM/GPRS) Analogics GSM Smart Modem is a multi-functional, ready to use, rugged and versatile modem that can be embedded or plugged into any application. The Smart Modem can be customized to various applications by using the standard AT commands. The modem is fully type-approved and can directly be integrated into your projects with any or all the features of Voice, Data, Fax, SMS, and Internet etc. Smart Modem kit contains the following items: 1. 2. 3. 4. 5. Analogics GSM/GPRS Smart Modem SMPS based power supply adapter. 3 dBi antenna with cable (optional: other types) Data cable (RS232) User Manual

Temperature Range: Operating temperature: from -200C to +550C Storage temperature: from -250C to +700C

Installing the modem: To install the modem, plug the device on to the supplied SMPS Adapter. Inserting/ Removing the SIM Card: 65

Make sure that the ejector is pushed out completely before accessing the SIM Card holder do not remove the SIM card holder by force or tamper it (it may permanently damage the SIM card holder). Place the SIM Card Properly as per the direction of the installation. It is very important that the SIM is placed in the right direction for its proper working condition.

Connecting External Antenna Connect GSM Smart Modem to the external antenna with cable end with SMA male. The Frequency of the antenna may be GSM 900/1800 MHz. The antenna may be (0 dbi, 3 dbi or short length L-type antenna) as per the field conditions and signal conditions. DC Supply Connection The Modem will automatically turn ON when connection is given to it. The following is the Power Supply Requirement: Connecting Modem to external devices: RS232 can be used to connect to the external device through the D-SUB/ USB (for USB model only) device that is provided in the modem.

Fig(31)-Circuit showing SMS based heart alert system

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5.FUTURE EXPANSION:
The Patient monitoring System is a useful application project. The project is designed here with is having limited facility, because of time cost limitations. This designed with an embedded microcontroller so have great extent of flexibility. The project can be expanded in the following direction. 1. The system designed here to monitor multiple channel for a single patient, it can be expanded to have multiple patient monitoring system. 2. The LCD display facility for different parameters can be added to this system to have a complete monitoring system. 3. This system can be interfaced to PC for storage of data and also at the receiver end A PC can be used for monitoring the system 4. A telephone or mobile can be interfaced for receiving an alarm in this connection.

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6.CONCLUSION:
The Patient monitoring System is designed and tested in the laboratory condition and found to be working satisfactorily. The response time for any fault in this design is approximately 1 sec. The system tolerance is well below the limits of experimental errors.

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7.REFERENCE:
1. National Center for Health Statistics.
Fast Stats: Heart Disease. 2004. http://www.cdc.gov/nchs/fastats/heart.htm 2. U.S. Department of Heath and Human Services. Vital and Heath Statistics. Series 10,Number 222. 2002. http://www.cdc.gov/nchs/data/series/sr_10/sr10_222.pdf 3. MEDICAL and HEALTH RELATED SCHEMATICS

http://circuitos.tripod.cl/schem/r24.gif 4. Filtering of ECG and Other electrophysiological signalsAlango solutions for sound sciencehttp://www.alango.com/biomedical/WhitePapers/AlangoBspTec100.pdf 5. MEDLINE PLUS MEDICAL ENCYCLOPEDIA..Holter Monitor

http://www.nlm.nih.gov/medlineplus/ency/article/003877.htm#visualContent
6. Tietze U and Schenk Ch: Measurement circuits. In Electronic Circuits Design and Application. 1990; 767-778. 7. Neuman MR: Biopotential amplifiers. In Webster JG, editor. Medical instrumentation application and design. John Wiley & Sons: New York, 1998; 233- 286. 8. Hamstra GH, Peter A and Grimbergen CA: Lowpower, low-noise instrumentation amplifier for physiological signals. Med Biol Eng Comput, 1984; 22: 272-274. 9. Dobrev D: Two-electrode low supply voltage electrocardiogram signal amplifier. Med Biol Eng Comput, 2004; 42: 272-276. 10. Amer MB: A design study of a bioelectric amplifier and improvement of its parameters. J Med Eng Technol, 1999; 23: 15-19. 11. Spinelli EM, Martinez NH and Mayosky MA: A single supply biopotential amplifier. Med Eng Phys, 2001; 23: 235-238. 12. Jefferson CB: Special-purpose OP amps. In Operational amplifiers for technicians. Breto publishers: 1983; 281-285.

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