Lovely Professional University,Punjab

Format For Instruction Plan [for Courses with Lectures and Labs

Course No CAP208

Cours Title INTRODUCTION TO COMPUTER ORGANIZATION AND ARCHITECTURE

Course Planner 13697 :: Anupama Singh

Lectures Tutorial Practical Credits 4 0 0 4

Text Book:

1 1. Author: Morris Mano, Title: Computer System Architecture, Publishers: Prentice Hall, Year of Publication: 2007

Other Specific Book: Other Reading Sr No Jouranls atricles as compulsary readings (specific articles, Complete reference) 2 Albert Paul Malvino, Donald P. Leach , Digital Principles and application, McGraw-Hill,1994 3 2. David A Patterson, Computer Architecture A Quantitative Approach, Pearson Education Asia. 4 J.P.Hayes, Computer System Architecture, Pearson Education Asia. Relevant Websites Sr. No. (Web adress) (only if relevant to the courses) Salient Features

Detailed Plan For Lectures

Week Number Lecture Number Lecture Topic Chapters/Sections of Pedagogical tool Textbook/other Demonstration/case reference study/images/anmatio n ctc. planned

Part 1
Week 1 Lecture 1 Data Representation: Number systems decimal, octal, hexadecimal, ->Reference :1,ch3.1 CA/Regular/CAP208/ Lecture 1

Approved for Spring Session 2011-12

Week 1

Lecture 2 Lecture 3 Lecture 4

Data Representation: Number systems decimal, octal, hexadecimal,

->Reference :1,ch3.1

CA/Regular/CAP208/ Lecture 2 CA/Regular/CAP208/ Lecture 3 CA/Regular/CAP208/ Lecture 4

Complement (r-1)s complement, rs complement, ->Reference :1,ch3.2 Fixed point representation, floating point representation,, ->Reference :1,ch3.3 ch3.2 ->Reference :1,ch3.3 ch3.4

Week 2

Lecture 5

Decimal codes, alphanumeric codes, Error detection ->Reference :1,ch3.5 codes ch3.6 Allocation of Homework(1st Academic Task) Digital Logic Circuits: Digital computers, Logic gates, , Boolean Algebra, Map Simplification Half Adder, Full Adder, Flip flops SR JK, D, T, Edge triggered flipflops, ->Reference :1,ch1.1 ch1.2 ->Reference :1,ch1.3 ->Reference :1,ch1.4 ->Reference :1,ch1.5 ch1.6 ->Reference :1,ch1.6

CA/Regular/CAP208/ Lecture 5 CA/Regular/CAP208/ Lecture 6 CA/Regular/CAP208/ Lecture 7 CA/Regular/CAP208/ Lecture 8 CA/Regular/CAP208/ Lecture 9 CA/Regular/CAP208/ Lecture 10 CA/Regular/CAP208/ Lecture 11 CA/Regular/CAP208/ Lecture 12 CA/Regular/CAP208/ Lecture 13

Lecture 6 Lecture 7 Lecture 8 Week 3 Lecture 9 Lecture 10

Lecture 11 Lecture 12 Week 4 Lecture 13

Sequential Circuits, Digital Components: Integrated ->Reference :1,ch1.7 circuits, ch2.1 Decoders NAND gate decoder, Encoders, Decoders NAND gate decoder, Encoders, ->Reference :1,ch2.2 ->Reference :1,ch2.2

Part 2
Week 4 Lecture 14 Lecture 15 Lecture 16 Week 5 Lecture 17 Lecture 18 Multiplexers, Demultiplexers, ->Reference :1,ch2.3 ->Reference :1,ch2.3 CA/Regular/CAP208/ Lecture 14 CA/Regular/CAP208/ Lecture 15 CA/Regular/CAP208/ Lecture 16 CA/Regular/CAP208/ Lecture 17 CA/Regular/CAP208/ Lecture 18 Approved for Spring Session 2011-12

Registers, Shift registers, Bidirectional Register with ->Reference :1,ch2.4 parallel load, ch2.5 Binary counters, Submission of HomeWok(1st Academic Task) Memory Unit RAM, ROM, Types of ROMs ->Reference :1,ch2.6 ->Reference :1,ch2.7

Week 5

Lecture 19 Lecture 20

Register Transfer and Micro-operations: Register transfer language, Register transfer, Bus and memory transfers three state bus buffers, Arithmetic micro-operations binary adder, binary adder-subtractor, binary incrementer, arithmetic circuit Test, 2nd Academic Task

->Reference :1,ch4.1 ch4.2 ->Reference :1,ch4.3 ->Reference :1,ch4.4 ->Reference :1,ch4.4 ->Reference :1,ch4.4 ->Reference :1,ch4.4

CA/Regular/CAP208/ Lecture 19 CA/Regular/CAP208/ Lecture 20 CA/Regular/CAP208/ Lecture 21 CA/Regular/CAP208/ Lecture 22 CA/Regular/CAP208/ Lecture 23 CA/Regular/CAP208/ Lecture 24 CA/Regular/CAP208/ Lecture 26 CA/Regular/CAP208/ Lecture 27 CA/Regular/CAP208/ Lecture 28

Week 6

Lecture 21 Lecture 22 Lecture 23 Lecture 24

Week 7

Lecture 25 Lecture 26

Logic micro-operations and its hardware ->Reference :1,ch4.5 implementation,Shift micro-operations and hardware implementation Logic micro-operations and its hardware implementation, Arithmetic Logic Shift unit,Hardware description languages ->Reference :1,ch4.6 ->Reference :1,ch4.7 ch4.8

Lecture 27 Lecture 28

MID-TERM Part 3
Week 8 Lecture 29 Basic Computer Organization and Design: Instruction Codes, Stored program organization, Allocation of Design Problem(3rd Academic Task) Computer registers, Common bus system, Computer instructions, Timing and Control, Instruction cycle, Memory reference instructions, Input output and interrupt, Input output and interrupt,complete design of basic computer Central Processing Unit: General register organization, control word, Stack organization, register stack,memory stack, ->Reference :1,ch5.1 CA/Regular/CAP208/ Lecture 29 CA/Regular/CAP208/ Lecture 30 CA/Regular/CAP208/ Lecture 31 CA/Regular/CAP208/ Lecture 32 CA/Regular/CAP208/ Lecture 33 CA/Regular/CAP208/ Lecture 34 CA/Regular/CAP208/ Lecture 35 CA/Regular/CAP208/ Lecture 36 Approved for Spring Session 2011-12

Lecture 30 Lecture 31 Lecture 32 Week 9 Lecture 33 Lecture 34 Lecture 35 Lecture 36

->Reference :1,ch5.2 ->Reference :1,ch5.3 ch5.4 ->Reference :1,ch5.5 ->Reference :1,ch5.6 ch5.7 ->Reference :1,ch5.7 ch5.9 ->Reference :1,ch8.1 ch8.2 ->Reference :1,ch8.3

Week 10

Lecture 37 Lecture 38 Lecture 39

Instruction formats three address, two address, one address, zero address instructions, Addressing modes Input-Output Organization: Input output interface,

->Reference :1,ch8.4 ->Reference :1,ch8.5

CA/Regular/CAP208/ Lecture 37 CA/Regular/CAP208/ Lecture 38

->Reference :1,ch11.2 CA/Regular/CAP208/ Lecture 39

Part 4
Week 10 Week 11 Lecture 40 Lecture 41 Lecture 42 Lecture 43 Lecture 44 Week 12 Lecture 45 Lecture 46 Lecture 47 Lecture 48 Week 13 Lecture 49 Lecture 50 Lecture 51 Lecture 52 I/O bus and interface modules I/O vs memory bus, Isolated vs Memory mapped I/O Asynchronous data transfer, handshaking, Programmed I/O, Interrupt-initiated I/O, Priority Interrupt Daisy chaining, parallel priority, priority encoder, interrupt cycle, DMA controller and transfer Submission of Design Problem (3rd Academic task) Memory Organization: Memory hierarchy, RAM, ROM chips, memory address map, Associative memory, Cache memory, Virtual memory ->Reference :1,ch11.2 CA/Regular/CAP208/ Lecture 40 ->Reference :1,ch11.2 CA/Regular/CAP208/ Lecture 41 ->Reference :1,ch11.2 CA/Regular/CAP208/ Lecture 42 ->Reference :1,ch11.3 CA/Regular/CAP208/ Lecture 43 ->Reference :1,ch11.4 CA/Regular/CAP208/ Lecture 44 ->Reference :1,ch11.5 CA/Regular/CAP208/ Lecture 45 ->Reference :1,ch11.5 CA/Regular/CAP208/ Lecture 46 ->Reference :1,ch11.5 CA/Regular/CAP208/ Lecture 47 ->Reference :1,ch11.6 CA/Regular/CAP208/ Lecture 48 ->Reference :1,ch12.1 CA/Regular/CAP208/ ch12.2 Lecture 49 ->Reference :1,ch12.2 CA/Regular/CAP208/ ch12.4 Lecture 50 ->Reference :1,ch12.5 CA/Regular/CAP208/ Lecture 51 ->Reference :1,ch12.6 CA/Regular/CAP208/ Lecture 52

Spill Over
Week 14 Lecture 53 Lecture 54 4 Multiplexer Virtual Memory Approved for Spring Session 2011-12

Details of homework and case studies

Homework No. Objective Topic of the Homework Nature of homework (group/individuals/field work Group Evaluation Mode Allottment / submission Week 8 / 11

Design problem 1 A design problem is an open-ended problem, the successful solutions of which should train students

A design problem is an open-ended problem, the successful solutions of which should train students to look up data-books, to integrate knowledge learnt in different parts of a course, to understand that most design problems require iterative methods, and to appreciate that optimization is a necessary tool of design. Basic Computer Organization and Design: Instruction Codes, Stored program organization, Computer registers, Common bus system, Computer instructions, Timing and Control, Instruction cycle, Memory reference instructions, Input output and interrupt, complete design of basic computer Central Processing Unit: General register organization, control word, Stack organization, register stack, memory stack, Instruction formats three address, two address, one address, zero address instructions, Addressing modes Input-Output Organization: Input output interface, I/O bus and interface modules, I/O vs memory bus, Isolated vs Memory mapped I/O Asynchronous data transfer, handshaking, Programmed I/O, Interrupt-initiated I/O, Priority Interrupt Daisy chaining, parallel priority, priority encoder, interrupt cycle, DMA controller and transfer Memory Organization: Memory hierarchy, RAM, ROM chips, memory address map, Associative memory, Cache memory, Virtual memory

Performance in the Design problem

Homework 1

The primary purpose of assigning Homework to students is to direct them to worthwhile practice at home.

Data Representation: Number systems decimal, octal, Individual hexadecimal, Complement (r-1)s complement, rs complement, Fixed point representation, floating point representation, Decimal codes, alphanumeric codes, Error detection codes,Digital Logic Circuits: Digital computers, Logic gates, Boolean Algebra, Map Simplification, Half Adder, Full Adder, Flip flops SR, JK, D, T, Edge triggered flipflops, Sequential Circuits

Performance in the Homework

2/5

Approved for Spring Session 2011-12

Test 1

No open book test shall be conducted for any course till the faculty members are trained in this process

Digital Components: Integrated circuits, Decoders NAND gate Individual decoder, Encoders, Multiplexers, Demultiplexers, Registers, Shift registers, Bidirectional Register with parallel load, Binary counters, Memory Unit RAM, ROM, Types of ROMs,Register Transfer and Micro-operations: Register transfer language, Register transfer, Bus and memory transfers three state bus buffers, Arithmetic micro-operations binary adder, binary adder-subtractor, binary incrementer, arithmetic circuit,Logic micro-operations and its hardware implementation, Shift microoperations and hardware implementation, Arithmetic Logic Shift unit, Hardware description languages

Performance in the Test

6/7

Scheme for CA:out of 100*

Component Homework,Test,Design problem Frequency 2 Total :Out Of 3 Each Marks Total Marks 10 10 20 20

* In ENG courses wherever the total exceeds 100, consider x best out of y components of CA, as explained in teacher's guide available on the UMS

Approved for Spring Session 2011-12