CHARACTERISTICS OF THE MOS CAPACITOR

The heart of the MOSFET is the MOS capacitor structure in Fig. 1. This is used to induce charge at the interface between the semiconductor and oxide, typically silicon dioxide (SiO2).
Metal electrode - "gate" Oxide VG TOX

The top electrode (gate) is formed of low-resistivity material, typically aluminium or heavily doped polysilicon (polycrystalline silicon). The thin oxide layer isolates the gate from the substrate or body (n- or ptype) which acts as the second electrode of the capacitor.

p-type silicon substrate or "body"

Figure 1 MOS capacitor structure on p-type silicon. The body has substantial resistivity and limited supply of holes and electrons and can thus be depleted of carriers; hence the capacitance of this structure is a nonlinear function of voltage. Figure 2 shows the conditions in the substrate immediately below the gate for three different bias conditions: accumulation, depletion, and inversion.

Figure 2 MOS capacitor operating in (a) accumulation, (b) depletion, and (c) inversion. Parameter VTN is called the threshold voltage and represents the voltage required to just begin formation of the inversion layer.

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1 Accumulation Region, Fig 2(a): Large negative charge on the gate is balanced by positively charged holes attracted to the Si-SiO2 interface directly below the gate. The hole density exceeds that in the original p-type substrate, and the surface is said to be operating in accumulation. This majority carrier accumulation layer is very shallow, effectively a charge sheet directly below the gate. 2 Depletion Region, Fig 2(b): As gate voltage is increased, holes are repelled from the surface. Eventually, the hole density near the surface is reduced below the majority-carrier level set by the substrate doping. This is called depletion and the region which is depleted of carriers, the depletion region. Positive charge on the gate is balanced by negative charge of the ionized acceptor atoms in the depletion layer. The depletion-region width wd can range from a fraction of a micron to tens of microns, depending on the applied voltage and substrate doping levels. 3 Inversion Region, Fig 2(c): As the gate voltage increases further, electrons are attracted to the surface. At a particular threshold voltage (VTN), the electron density exceeds the hole density, and the surface has inverted from the p-type polarity of the original substrate to an n-type inversion layer, or inversion region, effectively a charge sheet directly below the gate. Figure 3 shows variation of the capacitance of the NMOS structure with gate voltage. At voltages well below threshold, the surface is in accumulation, as in Fig. 2(a), and the capacitance is high, determined by the oxide thickness (TOX). As the gate voltage increases, the surface depletion layer forms as in Fig. 2(b), the effective separation of the capacitor plates increases, and the capacitance decreases steadily. The total capacitance can be modeled as the series combination of the fixed oxide capacitance Cox and the voltage dependent depletion-layer capacitance Cd, as in Fig. 3(b). The inversion layer forms at the surface as VG exceeds the threshold voltage VTN, as in Fig. 2(c), and the capacitance rapidly increases back to the value determined by the oxide layer thickness.

Figure 3 (a) Capacitance-voltage (C-V) characteristics for a MOS capacitor on a p-type substrate. (b) Series capacitance model for the C-V characteristic.
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