1) PROGRAM:Write a VHDL program to implement a half -adder using logic gates.

entity a1r is Port ( a : in STD_LOGIC; b : in STD_LOGIC; sum : out STD_LOGIC; carry : out STD_LOGIC); end a1r; architectureBehavioral of a1r is begin sum<=a xor b; carry<=a and b; endBehavioral;

2) PROGRAM:Write a VHDL program to implement a full adder using basic logic gates. entity a2r is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; sum : out STD_LOGIC; carry : out STD_LOGIC); end a2r; architecture Behavioral of a2r is begin sum<=(c and((not a and not b)or (a and b)))or(not c and((not a and b)or(a and not b))); carry<=(c and((not a and b)or (a and not b)))or(a and b); endBehavioral;

3) PROGRAM:Write a VHDL program to implement a Full Adder using half-adder. entity a21r is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; sumfinal :inout STD_LOGIC; carry_out : out STD_LOGIC); end a21r; architecture Behavioral of a21r is component halfadder port(x,y :in std_logic; sum,carry:outstd_logic); end component; component orgate port(x,y:in std_logic; n:out std_logic); end component; signal sum1,carry1,carryfinal:std_logic; begin out1: halfadder port map(a,b,sum1,carry1); out2:halfadder port map(sum1,c,sumfinal,carryfinal); out3:orgate port map(carry1,carryfinal,carry_out); endBehavioral; entityhalfadder is port (x,y : in bit ; sum,carry : out bit);

endhalfadder; architecture Behavioural of halfadder is begin sum<= x xor y; carry<= x and y; end Behavioural; entityorgate is port (x,y : in bit ; n : out bit); endorgate; architecture Behavioural of orgate is begin n<= x or y; end Behavioural;

4) PROGRAM:Write a VHDL program to implement a 4x1 mux using ?: statement. entity mulcond2 is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; d : in STD_LOGIC; sel : in STD_LOGIC_VECTOR (1 downto 0); x : out STD_LOGIC); end mulcond2; architectureBehavioral of mulcond2 is begin x<=a when sel="00"else x<=b when sel="01"else x<=c when sel="10"else x<=d ; endBehavioral;

5) PROGRAM:Write a VHDL program to implement a 4x1 mux using If-else statement. entity mul2rk is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; d : in STD_LOGIC; sel : in STD_LOGIC_VECTOR (1 downto 0); x : out STD_LOGIC); end mul2rk; architectureBehavioral of mul2rk is begin process(sel) begin ifsel="00"then x<=a; elsifsel="01"then x<=b; elsifsel="10"then x<=c; else x<=d; end if; end process; endBehavioral;

6) PROGRAM: Write a VHDL program to design a 4x1 mux using case statement. entity mul1r is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; d : in STD_LOGIC; x : out STD_LOGIC; sel : in STD_LOGIC_VECTOR (1 downto 0)); end mul1r; architectureBehavioral of mul1r is begin process(sel,a,b,c,d) begin CASE (sel) is when "00"=>x<=a; when "01"=>x<=b; when "10"=>x<=c; when others=>x<=d; end CASE; end process; endBehavioral;

7) PROGRAM: Write a VHDL program to implement a BCD to Gray converter. entitybcd is Port ( a : in STD_LOGIC_VECTOR (3 downto 0); b : out STD_LOGIC_VECTOR (3 downto 0)); endbcd; architectureBehavioral of bcd is begin b(3)<=a(3); b(2)<=a(3) xora(2); b(1)<=a(2) xora(1); b(0)<=a(1) xora(0); endBehavioral;

8) PROGRAM:Write a program to implement a J-K flip flop. entity jk1 is Port ( clk : in STD_LOGIC; reset : in STD_LOGIC; J : in STD_LOGIC; K : in STD_LOGIC; Q : out STD_LOGIC; QBAR : out STD_LOGIC); end jk1; architectureBehavioral of jk1 is signal state: std_logic; signal input: std_logic_vector(1 downto 0); begin input<=J & K; process(clk,reset) begin if(reset='1')then state<='0'; elsif(clk 'EVENT AND clk='1')then case (input) is when "11" => state<= not state; when "10" => state<= '1'; when "01" => state<= '0';

when others => null; end case; end if; end process; Q<= state; QBAR<= not state; endBehavioral;

9) PROGRAM:Write a program to implement a D flip-flop. entity dff1 is Port ( d,clk : in STD_LOGIC; reset : in STD_LOGIC; q : out STD_LOGIC); end dff1; architectureBehavioral of dff1 is begin process(clk,reset) begin if(reset='1')then q<='0'; elsif(clk 'event and clk='1')then q<=d; end if; end process; endBehavioral;

10) PROGRAM: Write a program to implement a 4-bit unsigned comparator. entity comp is Port ( a : in STD_LOGIC_VECTOR (3 downto 0); b : in STD_LOGIC_VECTOR (3 downto 0); less : out STD_LOGIC; greater : out STD_LOGIC; equal : out STD_LOGIC); end comp; architectureBehavioral of comp is begin process(a,b) begin if(a<b)then less<='1'; greater<='0'; equal<='0'; elsif(a>b)then less<='0'; greater<='1'; equal<='0'; elsif (a=b)then less<='0'; greater<='0'; equal<='1'; end if; end process;

endBehavioral;

11) PROGRAM:Write a VHDL program to implement a BCD counter. entity counter is Port ( clk : in STD_LOGIC; rst : in STD_LOGIC; count : out STD_LOGIC_VECTOR (3 downto 0)); end counter; architectureBehavioral of counter is TYPE state IS (zero, one, two, three, four, five, six, seven, eight, nine); SIGNAL pr_state, nx_state: state; BEGIN PROCESS (rst, clk) BEGIN IF (rst='1') THEN pr_state<= zero; ELSIF (clk'EVENT AND clk='1') THEN pr_state<= nx_state; END IF; END PROCESS; PROCESS (pr_state) BEGIN CASE pr_state IS WHEN zero => count<= "0000"; nx_state<= one; WHEN one => count<= "0001";

nx_state<= two; WHEN two => count<= "0010"; nx_state<= three; WHEN three => count<= "0011"; nx_state<= four; WHEN four => count<= "0100"; nx_state<= five; WHEN five => count<= "0101"; nx_state<= six; WHEN six => count<= "0110"; nx_state<= seven; WHEN seven => count<= "0111"; nx_state<= eight; WHEN eight => count<= "1000"; nx_state<= nine; WHEN nine => count<= "1001"; nx_state<= zero; END CASE;

END PROCESS; END Behavioral;

12) PROGRAM: Write a VHDL program to implement a four-bit adder. entity adder1 is Port ( a,b : in STD_LOGIC_VECTOR (3 downto 0); sum : out STD_LOGIC_VECTOR (3 downto 0); carry : out STD_LOGIC); end adder1; architectureBehavioral of adder1 is signal total: STD_LOGIC_VECTOR (4 downto 0); totalsum<=("0"& a)+b; sum<=totalsum(3 downto 0); carry<=totalsum(4); endBehavioral;

13) PROGRAM: Write a VHDL program to implement a 0 to 15 counter. entity count1 is Port ( clk,reset : in STD_LOGIC; led : out STD_LOGIC_VECTOR(3 downto 0)); end count1; architectureBehavioral of count1 is signal counter: std_logic_vector(3 downto 0); signalprescalar: std_logic_vector(25 downto 0); begin process(clk) begin if reset ='1' then counter<=(others =>'0'); prescalar<=(others =>'0'); elsif(clk 'event and clk='1')then ifprescalar<"10111110101111000010000000" then prescalar<=prescalar+1; elseprescalar<=(others=>'0'); counter<=counter+1; end if; end if; end process; led<=counter; endBehavioral;