LSI layout using hierarchical design with compaction

Liudvikas Abraitis and Arvydas Barila

A bottom up hierarchical design method for large scale integrated (LSI) circuit layout is suggested. Compaction of layout is used to obtain the 100% routing of connections at a high density of components. The hierarchical approach to layout design allows the realization of power buses and special nets by step shaped paths. Simultaneous design of two adjacent hierarchical levels/s used to achieve the opt/rod arrangement of exit points of blocks. computing, LSI layout, hierarchicaldesign, compaction Along with customary methods of LSI circuit layout design, other design approaches based on compaction of the layout tend to be widely used. The general principle of compaction was introduced by Akers 1 15 years ago. Since that time, various compaction methods have been developed and new ideas have been reported 2-4, mainly applied to symbolical LSI circuit layout design. However, their application has been limited due to the absence of a global compaction
a b

Figure 2(a). Step shapedpath and (b) step shapedpath after compaction
strategy. The methods based upon compaction ideas are

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Figure 1(a). Initial layout on 'expanded' chip and (b) final layout after compaction
Computer Department, KaunasPolitechnical Institute, V Juro 50-408, 233028 Kaunas, Lithuania SSR, USSR

used in an interactive manner in most cases. It is desirable to relate compaction with another urgent problem: that of achieving 100% routing of connections. Such a layout design process has been thoroughly analysed in Abraitis et a/s. The design method suggested by Abraitis et a/s involves component placement on the artificially expanded chip area, ensuring full routing of connections (see Figure 1(a)). Then compaction is performed, resulting in the layout having a minimum chip area (see Figure 1(b)). Fast and simple routing methods are used to achieve 100% routing. However, it is well known that results produced by these methods are not encouraging. An arrangement of components in two rows and the result of routing is shown in Figure 1(a). Obviously, compaction of such an initial layout does not promise good results. In order to improve the routing quality in the sense of path configuration and total path length, the initial routing is followed by rerouting. Rerouting enhances the efficiency of compaction. In Figure l(b) the final layout after rerouting and compaction is shown. Experimental investigation has shown that the method outlined above can be successfully applied in designing small integrated circuits (IC) only. In designing LSI circuit ,layout, it is time-consuming and therefore inefficient. Moreover, in the actual LSI circuit layout, paths of various width and so-called step shaped paths (see Figure 2(a)) are used for routing power buses and special connections. Although the processing of such connections causes no difficulties in initial routing, it becomes unrealistic in rerouting and compaction. It is difficult in the course of compaction to determine the necessarywidth of a path. As shown in Figure 2(b) the path segment width p, after compaction, equals 1 although, according to the electrical requirements, p should be equal to 2. This is due to the fact that not all the electrical requirements can be evaluated during compaction. The problem could be solved by way of complicated calculations performed during compaction, but this would be too timeconsuming. Therefore, in carrying out layout compaction, connection paths are required to be of equal width within a given net. Such a restriction makes the compaction process easier.

volume 18 number 7 september 1986 0010-4485/86/070367-04 $03.00 1986 Butterworth & Co (Publishers) Ltd 367

t.

OUTLINE

OF THE APPROACH

The approach proposed in this paper enables the achievement of the following goals (the suggested way of solving a corresponding problem is given in brackets): 100/; routing of connections (placement on artificially expanded area and initial routing) allowance of step shaped paths (hierarchical design) optimal arrangement of block exit points,(simultaneous design of blocks belonging to two adjacent hierarchical levels and rerouting)

c Figure 3(o). Block B(k + 1) layout after channel routing, (b) block B(k + 1) layout after rerouting and (c) block B(k + I) layout after compaction
minimization of chip area (compaction)

The present method consists of the following phases: initial layout of blocks B(k) or the first (k = 1) hierarchical level followed by rerouting of all nets initial layout of blocks B(k + 1) of the (k + 1)th level incorporating the layout of blocks B(h) of the hth hierarchical level into the initial layout of blocks B(k + 1 ); subsequent rerouting of nets in blocks B(h) and B(k + 1 ), at the same time a rearrangement of exit points of blocks B(k) is obtained compaction of the kth hierarchical level block layout The process is repeated similarly for (h + 1), (k + 2) and subsequent hierarchical levels. Finally, additional compaction of the block covering the whole circuit is performed. The path width of a net can be altered in this process only at the boundary of the block. Within the block, this width must remain constant. Such an approach is illustrated by an example shown in Figure 3. Figure 4 shows the evolution of the layout of the upper left block in Figure 3.

DESIGN M E T H O D
In this section the method will be described in more detail. First, assume a LSI circuit consisting of a component set E = (el, e2, , en) and a number of nets each connecting a subset of E.

Step 1
The set E is divided into separate subsets E~, i = 1, nl having pairwise empty intersections (the upper index indicates the hierarchical level). The size of each subset E~ is restricted: paths connecting the components of E~ should be of the same width. This restriction must be satisfied according to the electrical requirements imposed on the circuit. Criteria both of typification and maximum connectivity of components are also to be considered as secondary ones in the division process. The subsets E~, i = 1, nl having been determined, the initial layout of the first hierarchical level blocks B(1 ) is obtained. For this purpose the components of E~, i = 1, n~ are placed on the artificially expanded area. Then the initial channel routing of connections is performed to attain 100% routing (see Figure 4(a)). Further on, rerouting is applied to provide optimal conditions for compaction, as well as to

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12

13

13
Figure 5. Paths crossing the boundary of block B(k)
more optimal manner. As a rule, the strategy of strictly fixing the coordinates of exit points does not lead to acceptable results. Therefore, a kind of simultaneous design of the blocks belonging to two adjacent hierarchical levels is suggested. The block B(k) layouts from the library T k are included in the initial layout of blocks B(k + 1). Then, the rerouting of nets inside the blocks B(k + 1) is accomplished. The nets having exit points in B(k) are rerouted inside the block B(k + 1) including the area of blocks B(k), but excluding blocks of lower levels. As a result, the locations and the number of the block B(k) exit points may also be changed (see Figures 3(a), 3(b), 4(b) and 4(c)). In this way, the optimal arrangement of the blocks B(k) exit points in B(k + 1) can be obtained. Rerouting of nets with the path widths in blocks B(k) different from those in blocks B(k + 1) should be mentioned separately. Such nets should be routed so that the path widths within B(k) and B(k + 1) could be retained to be the same as before the rerouting (see Figure 3(b) and Figure 5). For this purpose, in the initial state, rerouting is carried out using wires having the same width as the wires in block B(k). Afterwards, the segments of wires belonging to the block B(k + 1) only, and not belonging to blocks B(k), are expanded until the necessary width is achieved. The capability for such expansion is ensured by using the rectangular cell map with the cell dimension equal to maximal wide width in the stage of initial layout. Figure 4(a) shows the initial (k + 1)th hierarchical level block layout which includes the k th level blocks. Recall that in the example, the layouts of blocks B(k) were identical before rerouting. After rerouting has been accomplished, the layouts of B(k) may appear changed (see Figure 3(b)). This would imply an increase in the size of the initial layout library T k. The library becomes then T k = { ~ } , i = 1, rn~, where m~ is the number of different layouts of B(k) satisfying the condition: m k ~ m ~ <~nk. In this step, the library T k+l = {tik+l }, i = 1, mk+1 of the initial layouts of blocks B(k + 1) is also formed.

11 13 "--I l 12

I1 t2

i3 13 d Figure V. Evolution of layout of block B(k) (a) ~nit~a/ layout, (b) layout after rerout/ng, (c) layout after rerout/ng within block B(k + I) and (d) f/na/ layout
improve the path configuration and to reduce the total path length. Rerouting is repeated successively for all nets by removing all the paths of a net and newly routing it once more (see Figure 4(a) and (b)). The step being completed, the library T 1 = {t~ ~, i = 1,mz, of initial layouts of blocks B(1 ) is created. In the given example (see Figure 3) the initial layouts of the first hierarchical level blocks are identical, ie ml = 1. The initial block layout is shown in Figure 4(b).

Step 2
In this step, the initial layout of blocks B(k + 1), k i> 1, of the (k + 1)th hierarchical level is designed. To this end, the subsets E~, i = 1, nk of the kth hierarchical level are combined into larger subsets E/k+l , i = 1, n ~ l . This gives a new partition of the set E, corresponding to the (k + 1)th hierarchical level. Similarly, as in the first hierarchical level, the size of subsets is restricted: paths of each single net should be of equal width within the block being designed. However, separate nets in the given block may have paths of different widths (see Figure 3(a)). These requirements also help to ensure the construction of blocks of approximately equal size. This is very important in hierarchical design, as it helps to achieve acceptable results in the subsequent hierarchical levels. The initial layout of blocks B(k + 1) is designed afterwards. For this purpose blocks B(k) are arranged in rows and the initial routing of connections is performed (see Figure 3(a)). As was previously mentioned, placement and initial routing are performed on an area necessary for the realization of all connections. However, in the routing, the real width of wires is already taken into account, ie power buses can be implemented by wires of appropriate width.

Step 4
To minimize the area of the layout of blocks B(k), the compaction procedure is invoked. This procedure yields the layout of B(k) in its final form, along with the corresponding library To = { ~ / } , i = 1, m~ (see Figure 4(d)). k After compaction the layout of each B(k) is substituted by the corresponding element from Tko. Further in the design process, the layouts of B(k) are not affected.

Step 3
The main goal of this step is the rearrangement of exit points of the blocks B(h) (see Figure 4(a), Iz, 12, 13). It makes it possible to connect blocks via exit points in a

Step 5
If the initial layout of the whole LSI circuit has not been

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completely designed then k is increased by one and steps 2 - 4 are repeated for a higher hierarchical level. Otherwise compaction occurs in the same way as in step 4 and the I/O pads of a chip are assigned. The final layout delivered by our method when two hierarchical levels are used is shown in Figure 3(c).

REFERENCES
1 Akers, S B, Geyer, J M and Roberts, D L 'IC mask layout with a single conductor layer' Proc. 7th Annual Design Automation Conf. San Francisco, USA (1970) pp 7-16 2 Dunlop, A E 'SLIM - t h e translation of symbolic layouts into mask data' J. DigitalSystems Vol V No 4 (1981) pp 429-451 3 Williams, J D 'STICKS - a graphical compiler for high level LSI design' Proc. National Computer Conference

CONCLUSIONS
The proposed method permits a library of standard cells to be used in any hierarchical level. Yet, in rerouting and compaction, such cells are to be considered as a blocks without affecting their internal structure. The application of the above method allows the achievement of 100% routing of all nets in a minimum chip area, and the optimal arrangement of the exit points of hierarchical blocks, as well as the realization of step shaped power buses.

(1978) pp 289-295 4 Schmidt, K H, Wach, W and Muller-Claser, K D 'A new method of VLSI conform design for MOS cells' Siemens Forsch.-u. Entwichl. - Ber. Bd. 12 No 4 (1983) pp 225-231 5 Abraitis, L, Blonskis, I and Kuzmicz, W 'The method of computer aided layout design for integrated circuits'
J. Design Automation and Fault-Tolerant Computing

Vol 3 No 3 (1979) pp 191-209

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