Salendra Govindarajulu et. al. / International Journal of Engineering Science and Technology Vol.

2(7), 2010, 2903-2917

Design of High Performance Dynamic CMOS Circuits in Deep Submicron Technology

SALENDRA.GOVINDARAJULU*1, DR. T.JAYACHANDRA PRASAD2
Associate Professor, Department of E.C.E, RGMCET, Nandyal, JNTU, A.P-INDIA, 2 Principal, RGMCET, JNTU,A.P-INDIA, *Corresponding Author E-mail address: rajulusg06@yahoo.co.in Abstract Technology scaling of transistor feature size has provided a remarkable advancement in silicon industry for the last three decades. The demand and popularity of portable electronics is driving designers to strive for small silicon area, higher speeds, low power dissipation and reliability. Compared to static CMOS logic, dynamic logic offers good performance. Wide fan-in logic such as domino circuits is used in high-performance applications. Dynamic domino logic circuits are widely used in modern digital VLSI circuits. These dynamic circuits are often favoured in high performance designs because of the speed advantage offered over static CMOS logic circuits. This paper compares static CMOS, domino (dynamic) logic design implementations of 16-bit Ripple carry adder, 16-bit Comparator and Linear Feedback Shift Register (LFSR) in terms of CMOS layout power consumption, delay, power delay product, area for 65 nm and 45 nm technologies. The techniques are compared by performing detailed transistor simulations on benchmark circuits using Microwind 3 and DSCH3 CMOS layout CAD tools. Key words: CMOS, Domino logic, Dynamic logic, Layout, Power consumption, Static logic. I.Introduction The power consumed in high performance microprocessors has increased to levels that impose a fundamental limitation to increasing performance and functionality [1][3]. If the current trend in increasing power continues, high performance microprocessors will soon consume thousands of watts. The power density of a high performance microprocessor will exceed the power density levels encountered in typical rocket nozzles within the next decade [2]. The generation, distribution, and dissipation of power are at the forefront of current problems faced by the integrated circuit industry [1][5]. The application of aggressive circuit design techniques which only focus on enhancing circuit speed without considering power is no longer an acceptable approach in most high complexity digital systems. Dynamic switching power, the dominant component of the total power consumed in current CMOS technologies, is quadratically reduced by lowering the supply voltage. Lowering the supply voltage, however, degrades circuit speed due to reduced transistor currents. Threshold voltages are scaled to reduce the degradation in speed caused by supply voltage scaling while maintaining the dynamic power consumption within acceptable levels [1][5]. At reduced threshold voltages, however, subthreshold leakage currents increase exponentially. Energy efficient circuit techniques aimed at lowering leakage currents are, therefore, highly desirable. Domino logic circuit techniques are extensively applied in high performance microprocessors due to the superior speed and area characteristics of domino CMOS circuits as compared to static CMOS circuits [7][8]. However, deep sub micrometer (DSM) domino logic circuits utilizing low power supply and threshold voltages have decreased noise margins [9][11]. As on-chip noise becomes more severe with technology scaling and increasing operating frequencies, error free operation of domino logic circuits has become a major challenge [9], [10], [11]. With advancements in large scale integration, millions of transistors can be placed in single chip for implementation of complex circuits, as a result of placing so many transistors in such a small space, major problems of heat dissipation, power consumption have come in to the picture. Static logic requires more above drawbacks. Thus in this paper, these are implemented using domino logic. The static logic and domino logic implementations are compared by simulation in deep submicron technology using MICROWIND3 CAD tool. The organization of the paper is as follows. A brief review of the sources of power dissipation in CMOS circuits is provided in Section II. In Section III various techniques on benchmark circuits for power reduction are proposed. In Section IV simulation and implementation results are presented. Finally, conclusions are presented in Section V.
1

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Salendra Govindarajulu et. al. / International Journal of Engineering Science and Technology Vol. 2(7), 2010, 2903-2917 II. Sources of Power Dissipation The power consumed by CMOS circuits can be classified into two categories: A. Dynamic Power Dissipation For a fraction of an instant during the operation of a circuit, both the PMOS and NMOS devices are on simultaneously. The duration of the interval depends on the input and output transition (rise and fall) times. During this time, a path exists between VDD and Gnd and a short-circuit current flows. However, this is not the dominant factor in dynamic power dissipation. The major component of dynamic power dissipation arises from transient switching behaviour of the nodes. Signals in CMOS devices transition back and forth between the two logic levels, resulting in the charging and discharging of parasitic capacitances in the circuit. Dynamic power dissipation is proportional to the square of the supply voltage. In deep sub-micron processes, supply voltages and threshold voltages for MOS transistors are greatly reduced. This, to an extent, reduces the dynamic power dissipation. B. Static Power Dissipation This is the power dissipation due to leakage currents which flow through a transistor when no transactions occur and the transistor is in a steady state. Leakage power depends on gate length and oxide thickness. It varies exponentially with threshold voltage and other parameters. Reduction of supply voltages and threshold voltages for MOS transistors, which helps to reduce dynamic power dissipation, becomes disadvantageous in this case. The subthreshold leakage current increases exponentially, thereby increasing static power dissipation. III. Circuit Techniques A. Ripple Carry Adder (16 bit): Full adder: A full adder is a logical circuit that performs an addition operation on three binary digits. The full adder produces sum and carry values, which are both binary digits. These are used in multipliers; multipliers are used in digital filters. Fig1 shows Full adder circuit. Table1 shows truth table of full adder.

Fig1: 1-bit Full adder

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Table 1: Truth table of 1-bit Full adder

A B Cin C0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 1 0 1 1 1

S 0 1 1 0 1 0 0 1

Fig2: Schematic symbol for 1-bit Full adder

Ripple carry adder: It is possible to create logical circuit using multiple full adders to add N (pre case 16) bit numbers. Each full adder inputs a Cin (Carry input) which is the Cout (Carry output) of previous adder. This kind of adder is ripple carry adder since each carry bit ripples to the next full adder. Fig3 shows N-bit Ripple Carry Adder structure.

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Fig3: N bit Ripple carry adder Structure

B. 16 Bit Comparator: Binary comparators or digital comparators compare digital signals at their input terminals and produces output depending upon the condition of the inputs. For example A is grater, equal or smaller to input B. A comparator is a circuit which compares the relative magnitudes of two numbers. If A and B are two input binary numbers to the comparator, Comparator compares and gives the output as logic 1 when A>=B. Fig4 shows the static comparator circuit. Fig5 is the schematic symbol of 1-bit comparator. Table2 shows the truth table of comparator. Fig6 shows N-bit comparator structure.

Fig4: Schematic symbol of 1bit Comparator Table2: Truth table of Comparator

Cin 0 0 0 1 1 1 1

Ai 0 0 1 0 0 1 1

Bi 0 1 0 0 1 0 1

Cout 0 0 1 1 0 1 1

Decision A<=B A<B A>B A>B A<=B A>B A>B

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Fig5: N bit comparator structure

C. Linear Feed Back Shift Register: LFSR is a shift register when clocked moves the signal through from one flip flop to next. Some of the outputs are combined in XOR configuration to form feed back mechanism. A LFSR can be formed by performing XOR on the outputs of two or more of the flip flop together and feeding those outputs back into the input of one of the flip flops as shown in Fig.

Fig6: Linear Feed Back Shift Register

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Fig 7: Structure of Master-Slave D Flip Flop

The initial value of the LFSR is called the SEED. The sequence of values produced by the register is completely determined by its current or previous state likewise, because the register has finite numbers of possible states, it must be eventually enter a repeating cycle. However, a LFSR with a well chosen feed back function can produce a sequence of bits which appears random in nature. The list of bits position that affects the next state is called the tap sequence.
Table3: Pattern Generated by LFSR

Clk Pulse 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

FF1 OUTPUT 0 0 0 1 0 0 1 1 0 1 0 1 1 1 1 1 0

FF2 OUTPUT 1 0 0 0 1 0 0 1 1 0 1 0 0 1 1 1 1

FF3 OUTPUT 1 1 0 0 0 1 0 0 1 1 0 1 1 0 1 1 1

FF4 OUTPUT 1 1 1 0 0 0 1 0 0 1 1 0 0 1 0 1 1

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Salendra Govindarajulu et. al. / International Journal of Engineering Science and Technology Vol. 2(7), 2010, 2903-2917 The logic hardware of LFSR contains D flipflop, 2 input OR gate, 2 input XOR gate and inverters. The most imp component of LFSR Design is D flip flop. Applications of LFSR 1. Used in BIST (Built in Self Test). 2. In Cryptography it is used to generate public and private Keys. 3. In Communications for generating Pseudo Random Numbers generation. IV. Design and Layout Aspects: Static logic and Dynamic logic (Domino logic) : The largest difference between static logic and dynamic logic is that in dynamic logic, a clock signal is used. Dynamic logic is over twice as fast as normal logic; it uses only fast N transistors. Static logic is slower because it uses slow P transistors to compute logic. Dynamic logic is harder to work, but if we need the speed there is no other choice. Dynamic logic requires two phases, the first phase is set up phase or pre charge phase, in this phase the output is unconditionally go to high (no matter the values of the inputs A and B).The capacitor which represents the load capacitance of this gate becomes charged. During the evaluation phase, CLK is high. Popular implementation of dynamic logic is domino logic. Domino logic is a CMOS based evaluation of the dynamic logic techniques which are based on the either PMOS or NMOS transistors. It was developed to speed up the circuits. The dynamic gate outputs connect to one inverter, in domino logic. In domino logic, cascade structure consisting of several stages, the evaluation of each stage ripples the next stage evaluation, similar to a domino falling one after the other. Once fallen, the node states cannot return to 1 (until the next clk cycle), just as dominos, once fallen, cannot stand up. The structure is hence called domino CMOS logic. Fig8 shows static implementation of Ripple carry adder. Fig9 shows domino Ripple carry adder. Fig10 shows layout of 16-bit Ripple carry adder with static logic. Fig11 is the layout of 16-bit ripple carry adder with domino logic. Fig12 shows 16-bit static comparator. Fig13 is the domino 16bit comparator. Fig14 is the layout of static comparator. Fig15 is the layout of domino comparator.

Fig8: Domino logic

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Fig9:16 bit Ripple carry adder (Static logic)

Fig10: 16-bit Domino Ripple carry adder

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Fig11: Layout of 16bit RC adder (Static logic)

Fig12: Layout of 16bit RC (Domino Logic)

Fig13:16-bit static comparator

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Fig14: 16 bit Domino Comparator

Fig15: Layout of Static Comparator

Fig16: Layout of Domino Comparator

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Fig17: Simulation of Static LFSR

Fig18: Simulation of Domino LFSR

V. Simulation Results Table4 shows Microwind3 simulation results for 16-bit Ripple carry adder. Table5 shows the simulation results for the 16-bit Comparator. These compare static and domino logic implementations regarding Power dissipation, delay, power delay product and area for 65 nm and 45 nm technologies. Table6 shows the simulation results of LFSR.

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Table4: 16-bit Ripple carry Adder

Techniques

Power (w) 65nm 45nm 26 14.4 14.4 11.9

Delay (ns) 0.365 0.060 0.105 0.052

PDP X (10-15) (Watt-sec) 9.5 0.87 1.515 0.62

Area (m2) 5229 1748 5253 1707

Static logic

Domino logic

65nm 45nm

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Table5: 16-bit Comparator

Techniques

Power (w) 65nm 45nm 65nm 45nm 43.558 23..980 6.609 3.821

Delay (ns) 0.105 0.044 0.073 0.075

PDP X (10-15) (Watt-sec) 4.57 1.055 0.4824 0.2865

Area (m2) 2281 729 1972 662

Static logic Domino logic

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Table6: LFSR

Techniques

Power (w) 45nm 45nm 45nm 15.550 26.462 9.646

Delay (ns) 0.046 0.048 0.061

PDP X (10-15) (Watt-sec) 0.7153 1.270 0.588

Area (m2) 307 319 501

NANDGATES Static logic Domino logic

VI. Conclusions In this project, an attempt has been made to design 2input AND, 2input OR, 2input XOR, D Flip Flop which are the basic building blocks for the benchmark circuits 16 bit Ripple carry adder,16 bit Comparator, Linear Feed Back Register. The proposed circuits have offered an improved performance in power dissipation when compared with standard static circuits. In this work, it can be concluded that 16 bit Ripple carry adder, 16bit Comparator and LFSR can be best implemented using domino logic. In the domino logic for 16 bit Ripple carry adder power delay product at 65nm is 1.515X (10-15) watt-sec, at 45nm 0.68X (10-15) watt-sec., 16 bit comparator power delay product at 65nm is 0.4824X (10-15) watt-sec, at 45nm is 0.2865X (10-15) watt-sec. In the domino logic for LFSR power delay product at 45nm is 0.588X (10-15) watt-sec References
[1] [2] [3] [4] [5] [6] [7] [8] S. Borkar, Obeying moores law beyond 0.18 micron, in Proc. IEEE Int. ASIC/SOC Conf., Sept. 2000, pp. 2631. R. Ronen et al., Coming challenges in microarchitecture and architecture,Proc. IEEE, vol. 89, pp. 325339, Mar. 2001. M. T. Bohr, Nanotechnology goals and Challenges for electronic applications, IEEE Trans.Nanotechnol., vol. 1, pp. 5662, Mar. 2002. D. J. Frank et al., Device scaling limits of Si MOSFETs and their application dependencies, Proc. IEEE, vol. 89, pp. 259288, Mar. 2001. R. K. Krishnamurty, A. Alvandpour, V. De, and S. Borkar, High-performance and low-power challenges for sub-70 nm microprocessor circuits,in Proc. IEEE Custom Integrated Circuits Conf., May 2002, pp.125128. S. Mutoh et al., 1-V power supply high-speed Digital circuit technology with multithreshold- voltage CMOS, IEEE J. Solid-State Circuits, vol.30, pp. 847854, Aug. 1995. V. Kursun and E. G. Friedman, Domino logic with dynamic body Biased keeper, in Proc. Eur. Solid- State Circuits Conf., Sept. 2002, pp.675678. Variable threshold voltage keeper for contention reduction in dynamic circuits, in Proc. IEEE Int. ASIC/SOC Conf., Sept. 2002, pp.314318.

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[9] [10] [11] [12] [13] [14] [15] [16] [17] S. Borkar, Low Power Design Challenges for the Decade, Proceedings of the IEEE/ACM Design Automation Conference, pp. 293296, June 2001. P. Srivastava, A. Pua, and L. Welch, .Issues in the Design of Domino Logic Circuits, Proceedings of the IEEE Great Lakes Symposium on VLSI, pp. 108-112, February 1998. G. Balamurugan and N. R. Shanbhag, .Energy- efficient Dynamic Circuit Design in the Presence of Crosstalk Noise,. Proceedings of the IEEE International Symposium on Low Power Electronics and Design, pp. 24-29, August 1999. S.Govindarajulu, T.Jayachandra Prasad, Low power,Energy-efficient Domino Logic Circuits, IJRTE, vol.2, No.7, Nov.2009, pp.3033, Academy Publishers, ACEEE, Finland. S.Govindarajulu, T.Jayachandra Prasad, Low-Power, High Performance Dual Threshold Voltage CMOS Domino Logic Circuits, published in ICRAES, 8th & 9th Jan2010, pp-109-117,KSR College of Engg., Tiruchengode, India. S.Govindarajulu, T.Jayachandra Prasad, Robust, Energy-efficient Reduced Swing Domino Logic Circuits, IJRTE, vol.3, No.4, pp.129-133, May.2010, Academy Publishers, ACEEE, Finland, in Press S.Govindarajulu, T.Jayachandra Prasad, Considerations of Performance Factors in CMOS Designs, ICED 2008, Dec.1-3 ,Penang, Malaysia, IEEE Xplore. S.Govindarajulu, T.Jayachandra Prasad, ,Energy-efficient Reduced swing Domino Logic Circuits in 65 nm Technology, IJEST, Vol. 2(6), 2010, pp.2248-2257. S.Govindarajulu, T.Jayachandra Prasad, ,Temperature Variation Insensitivein Energy-efficient CMOS Circuits Design in 65 nm Technology, IJEST, Vol. 2(6), 2010, pp. 2140-2147.

Biographical Notes
1

Salendra.Govindarajulu:- He is working as an Associate Professor in the Dept. of Electronics & Communication Engg. at RGMCET, Nandyal, Andhra Pradesh, India. He presented more than 13 International/National Technical Papers. He is a Life Member of ISTE, New Delhi. His interest includes Low Power VLSI CMOS design.

Dr.T.Jayachandra Prasad:- He is working as a Principal and Professor in the Dept. of Electronics & Communication Engg. at RGMCET, Nandyal Andhra Pradesh, India. He presented more than 40 International/National Technical Papers. He is Life Member in IE (I), CALCUTTA, Life Member in ISTE, NEW DELHI, Life Member in NAFEN, NEW DELHI, and IEEE Member. His interest includes Digital Signal Processing.

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