HW-AFX-SP3-1500 2000 Manua V1.7

Nu Horizons Electronics
Spartan3 1500 / 2000 Evaluation Platform
HW-AFX-SP3-1500 / 2000
Nu Horizons Electronics Spartan3 1500 / 2000 Evaluation
Platform
User Guide and Reference Manual
Revision 1.7
January 10, 2006
This document describes the HW-AFX-SP3-1500 / 2000 development board provided by Nu Horizons Electronics Corp. No warranty is given for the suitability of this design for
any purpose other than prototyping and functional operation. Nu Horizons Electronics assumes no liability with respect to the use of the board nor liability for the use of the
circuitry inside the Xilinx FPGA. The information contained in this document is subject to change without notice.
Table of Contents:
1.0
Introduction........................................................................................................... 5
Figure1: Nu Horizons Electronics Spartan3 1500 / 2000 Evaluation Board Block

Diagram .......................................................................................................................... 6
2.0
Evaluation Board Contents.................................................................................. 7
3.0
Board Overview .................................................................................................... 7
LEDs................................................................................................................................... 7
Table 1: LED Pin Connections to XC3S1500 / 2000...................................................... 8
Pushbuttons ....................................................................................................................... 8
Table 2: Pushbutton Pin Connections to XC3S1500 / 2000........................................... 8
4x24 Character LCD Display........................................................................................... 8
Table 3: LCD PIN Connections XC3S1500 / 2000...................................................... 8
4x24 Character LCD Display Read/Write Timing Chart ............................................. 9
Figure 2: 4x24 Character LCD Display Read/Write Waveforms................................... 9
PLL Clock Multiplier ..................................................................................................... 10
Figure 3: ICS511 PLL Clock Multiplier Circuit .......................................................... 10
Figure 4: U54 Oscillator Socket................................................................................... 10
Table 4: Clock PIN Connections XC3S1500 / 2000 .................................................. 10
Table 5 Clock Output Table....................................................................................... 11
Programmable Frequency Synthesizer......................................................................... 11
Table 6: M Divide Function Table ............................................................................... 11
Table 7: N Output Divider Function Table .................................................................. 11
Figure4: ICS84021 Frequency Divider........................................................................ 12
Table 8: ICS84201 Clock Signal XC3S1500 / 2000 .................................................. 12
RS-232-C Interface ......................................................................................................... 12
Table 9: RS-232 Port 1 Pins XC3S1500 / 2000......................................................... 12
Table 10: RS-232 Port 2 Pins XC3S1500 / 2000....................................................... 12
Figure 5: RS232 Port 1 & 2.......................................................................................... 13
Table 11: RS232 Speed Select Jumper Settings............................................................ 13
CAN 2.0B High Speed Transceiver ............................................................................... 13

Figure 6: CAN 2.0B Bus Controller & High-Speed Transceiver ................................. 14
Table 12: L9616 Connections....................................................................................... 14
Table 13:J11 CAN ASC Settings................................................................................... 14
Figure 7: CAN Interface ............................................................................................... 15
PS2 Interface ................................................................................................................... 15
Table14: PS2 Port Interface XC3S1500 / 2000......................................................... 15
Figure 8: PS2 Port Interface ........................................................................................ 15
14bit Linear CODEC...................................................................................................... 16
Figure9: STw5093 Circuit Diagram............................................................................. 16
Table 15: Audio CODEC FPGA Signal Connections XC3S1500 / 2000 .................. 16
Analog to Digital Converter........................................................................................... 17
Table16: LTC1865L ADC SPI Interface XC3S1500 / 2000 ...................................... 17
Table 17: LTC1865L ADC Signal Input Header / Jumper Settings ............................. 17
Digital to Analog Converter........................................................................................... 18
Table18: LTC1654 DAC SPI I/F .................................................................................. 18
Table 19: LTC1654 DAC Signal Input Header ............................................................ 18
SDRAM Interface ........................................................................................................... 19
Table 21: SDRAM PIN I/F............................................................................................ 19
NBT SSRAM Interface (Alternative Memory Not Included on standard build) .. 20
Table 22: SSRAM PIN I/F ............................................................................................ 20
Flash Interface................................................................................................................. 21
Table 23: Flash PIN I/F XC3S1500 / 2000 ............................................................... 21
Test Point Headers 3.3V ................................................................................................. 22
Table 24: J24 3.3V Test Point Header PIN Connections XC3S1500 / 2000............. 22
Table 27: PD Test Points Connections......................................................................... 23
LVDS Test Point Header................................................................................................ 24
Table 28: J23 LVDS PIN Connections ......................................................................... 24
10/100 Ethernet Media Access Controller .................................................................... 25

Table 29: SMSC 91C111 FPGA Pin Connections XC3S1500 / 2000 ....................... 25
10/100 Ethernet Physical Interface................................................................................ 26
Table 30: ICS1893 Pin Connections XC3S1500 / 2000 ............................................ 26
Linear Technology High Speed Analog to Digital Interface....................................... 26
Table 31: LTC High Speed ADC Evaluation Board Part Numbers ............................. 26
Figure 12: LTC Evaluation Board................................................................................ 27
Linear Technology High Speed ADC Interface Connections ..................................... 27
Table32: J29 LTC ADC Interface XC3S1500 / 2000 ................................................ 27
Figure 13: J29 Circuit Diagram................................................................................... 28
Intersil High Speed Digital to Analog Interface........................................................... 29
Table 33: Intersil Evaluation Board Part Numbers ..................................................... 29
Intersil High Speed DAC Interface Connections ......................................................... 29
Table 34: J27 Intersil DAC Interface XC3S1500 / 2000 ........................................... 29
Figure14: J27 Circuit Diagram.................................................................................... 30
Table 35: J28 Intersil DAC Interface XC3S1500 / 2000 ........................................... 30
Graphical LCD Interface ............................................................................................... 31
Table 36: J31 LCD I/F Connections XC3S1500 / 2000 ............................................ 32
Agilent Soft Touch Probe Interface .............................................................................. 33
Figure 17: Agilent E5394A Soft Touch Probe Connector Diagram ............................ 33
Programming Interface .................................................................................................. 34
Table 37: Cable III Interface ........................................................................................ 34
Table 38: Cable IV Interface ........................................................................................ 34
Operating and Storage Environments .......................................................................... 34
Regulatory Compliance (FCC Part 15 Class B, and Part 68)..................................... 34
Scope
This document defines the configuration of jumpers and the function of various
components of the baseline board level hardware elements that comprise the
HW-AFX-SP3-1500 / 2000 evaluation platform.
1.0
Introduction
The Spartan3-1500 / 2000 evaluation platform is a very flexible testing platform that
allows the engineer to evaluate the Xilinx XC3S1500 / 2000 FPGA in a typical
application. Block diagram is provided, Figure 1.
The distinctive features of the board include.
Based on the Spartan 3 - 1.5 Million Gate FPGA

o XC3S1500-4 FG676C
2 Channel A/D Converter
o Linear Tech LTC1865L
16bit 150Ksps
2 Channel D/A Converter
o Linear Tech LTC1654
14bit 8us Conversion Time
2 - 4M X 16 SDRAM 128Mb
o ISSI42S16400
32Mb Flash 2Mb X 16
o ST M29W320DB
4 X 24 Character LCD Interface
PS2 Port Interface
2 - RS232 Serial Ports
CAN 2.0B Physical Layer
o ST L9616
Graphics LCD Interface
o Logic Product Display Kit Compatible
10/100 Ethernet Phy.
o ICS1893BF
10/100 Ethernet MAC
o SMSC 91C111
16bit LVDS I/F with Clock & Control
Audio Codec
o STw5093 14bit Linear CODEC
ICS511 PLL Clock Multiplier
o 20MHz Crystal
ICS84021 PLL Clock Multiplier
o 20MHz Clock Crystal
50 MHz clock Oscillator
o Secondary Oscillator Socket Provided
XCF08 Platform Flash for Configuration
8 LEDs
4 Push Buttons
73 - 3.3V Test/Expansion Pin Headers
Agilent E5404A Soft Touch Pro Probe
Applications:
Microblaze Soft Processor Development
DSP System Development
Industrial Systems Development
Universal Prototyping Platform
Figure1: Nu Horizons Electronics Spartan3 1500 / 2000 Evaluation Board Block Diagram
2.0
3.0
Evaluation Board Contents

HW-AFX-SP3-1500 / 2000 Development Board
Documentation CD
AC Power Supply
Board Overview
Power Supply
The HW-AFX-SP3-1500 / 2000 board can be powered from an external power supply,
two power connectors are provided. (J17 DC Barrel Jack, J16 - Vertical Header 0.1)
External power supply must reside between 6 and 9 Volts
Regulators on the board supply:
5.0V/750mA
3.3V/3A
2.5V /800mA LVDS I/F
1.2V/2A - VccInt
1.8V / 2.5V/ 3.3V 750mA Adjustable
+12 & -12V /75mA
Power Status LED

There are two power status LEDs that provide status for the 3.3V and 3.3V ANA voltage
levels.
LED9 3.3V ANA Analog voltage level
LED11 3.3V Digital supply voltage.
LEDs
Eight LEDs are provided for display outputs. LED cathodes are driven directly from the
FPGA via 470-ohm resistor, and the anodes are connected directly to 3.3V supply.
:
7
LED Position
LED 1
LED 2
LED 3
LED 4
LED 5
LED 6
LED 7
LED 8
XC3S1500 / 2000 PIN

M6
M7
M8
N2
N3
N4
N5
N6
Table 1: LED Pin Connections to XC3S1500 / 2000
Pushbuttons
Four pushbuttons are provided for circuit input.
Pushbutton Position
PB_SW1
PB_SW2
PB_SW3
PB_SW4
XC3S1500 / 2000 PIN

W22
W24
W25
W26
Table 2: Pushbutton Pin Connections to XC3S1500 / 2000
4x24 Character LCD Display

The HW-AFX-SP3-1500 / 2000 board includes a 4x24 Character LCD display. The LCD
display has an integrated LCD controller/driver from Microtips Technology (MTCS20400XFGNSAY). The following chart details the LCD connections to the XC3S1500
/ 2000.
LCD PIN
LCD_RS
LCD_RW
LCD_EN
LCD_DATA0
LCD_DATA1
LCD_DATA2
LCD_DATA3
LCD_DATA4
LCD_DATA5
LCD_DATA6
LCD_DATA7
BACKL_ON
XC3S1500 / 2000
T19
T20
T21
T22
T23
T25
T26
U20
U22
U23
U24
Y25
Table 3: LCD PIN Connections XC3S1500 / 2000
4x24 Character LCD Display Read/Write Timing Chart
Figure 2: 4x24 Character LCD Display Read/Write Waveforms
PLL Clock Multiplier

The HW_AFX_SP3-1500 / 2000 Evaluation Platform board provides the user with a
20MHz clock crystal Y1 in conjunction with an ICS511 PLL clock multiplier for circuit
evaluation. Also an 8-pin oscillator socket, U9, is also provided for customers to install
their own clock oscillator.
Figure 3: ICS511 PLL Clock Multiplier Circuit
Figure 4: U54 Oscillator Socket
Clock Signal
PLL_CLK
MAIN_CLK
XC3S1500 / 2000 Pin

AE14
AF14
Table 4: Clock PIN Connections XC3S1500 / 2000
10
Table 5 Clock Output Table
Programmable Frequency Synthesizer

The Spartan 3 1500 / 2000 Evaluation Board utilizes the ICS84021 frequency
synthesizer to supply the high frequency clock to the Intersil Digital to Analog converter
evaluation board and the XC3S1500 / 2000 FPGA. The ICS84021 features a fully
integrated PLL and therefore requires no external components for setting the loop
bandwidth. A fundamental crystal is used as the input to the on chip oscillator. The
output of the oscillator is fed into the phase detector. A 25MHz crystal provides a 25MHz
phase detector reference frequency. The VCO of the PLL operates over a range of
620MHz to 780MHz. The output of the M divider is also applied to the phase detector.
The programmable features of the ICS84021 support a parallel input to program the M
divider and N output divider. The M value and the required values of M0 through M8 are
shown in table 6 and N0 N1 values are shown in table 7.
VCO MHz
625
700
775
M Divide M8-256 M7-128
25
28
31
0
0
0
M6-64
M5-32
0
0
0
0
0
0
0
0
0
M4-16
1
1
1
M3-8
M2-4
M1-2
1
1
1
0
1
1
0
0
1
M0-1
1
0
1
Table 6: M Divide Function Table

N1
N0
0
0
1
1
N Value
0
1
0
1
3
4
5
6
Table 7: N Output Divider Function Table
11
Output Min/ MHz Output Max/MHz
206.7
155
124
103.3
260
195
156
130
Figure4: ICS84021 Frequency Divider
ICS84021 Clock Signal

PLL_CLK_FPGA
XC3S1500 / 2000 Pin

C14
Table 8: ICS84201 Clock Signal XC3S1500 / 2000
RS-232-C Interface
The Spartan3 - 1500 / 2000 Evaluation Board uses two ST Microelectronics ST3237
level converters to generate the required RS-232-C voltage levels. Both interfaces are
wired as DCE ports and have selectable speed jumper, figure 3 details the jumper and
circuit. Pin definitions listed bellow in Table 6 & 7.
RS232 I/F
LV_RX_DATA
LV_TX_DATA
LV_RTS
LV_DCE_READY
LV_CTS
XC3S1500 / 2000 PIN

V20
U26
U25
V22
V21
Table 9: RS-232 Port 1 Pins XC3S1500 / 2000
RS232 I/F
LV_RX_DATA2
LV_TX_DATA2
LV_RTS2
LV_DCE_READY2
LV_CTS2
XC3S1500 / 2000 PIN

AB14
AA12
AF16
AD25
AD17
Table 10: RS-232 Port 2 Pins XC3S1500 / 2000
12
Figure 5: RS232 Port 1 & 2
RS232 Speed Select Jumper

J1 1 & 2
J1 2 & 3
J2 1 & 2
J2 2 & 3
Speed Selected
1Mbps
250Kbps
1Mbps
250Kbps
Table 11: RS232 Speed Select Jumper Settings
CAN 2.0B High Speed Transceiver

The Spartan3 1500 / 2000 Evaluation Board includes the ST Microelectronics L9616
high speed CAN bus transceiver for implementing and designing with the CAN 2.0B bus
controller. Nu Horizons offers a BOSCH compliant CAN 2.0B bus controller that
connects to the OPB bus of the Xilinx MicroBlaze soft processor is Figure 4 is a block
diagram of the implementation of the CAN 2.0B bus controller and the L9616 high speed
transceiver.
13
Figure 6: CAN 2.0B Bus Controller & High-Speed Transceiver
The L9616 is a bidirectional transceiver for signal conditioning and processing in

connection with a CAN controller. Data rates of up to 1MEGABAUD are supported
using either shielded or non-shielded pair of lines. Table 9 details the physical
connections to the XC3S1500 / 2000 FPGA.
CAN High Speed Transceiver
XC3S1500 / 2000 Pin
1 CAN_TX0
AB23
4 CAN_RX0
Y26
Table 12: L9616 Connections
J11 ASC Speed Select Jumper

J11 1 & 2
J11 Open
Speed Selected
<= 250Kbps
<= 1Mbps
Table 13:J11 CAN ASC Settings
14
Figure 7: CAN Interface
PS2 Interface
The Spantan3 1500 / 2000 Evaluation Board includes the physical interface for the 6
pin mini PS2 port connector JR1.
PS2 Pin
1 PS2_DATA
5 PS2_CLK
XC3S1500 / 2000
V23
V24
Table14: PS2 Port Interface XC3S1500 / 2000
Figure 8: PS2 Port Interface
15
14bit Linear CODEC

The ST Microelectronics STw5093 high performance Audio CODEC is included with the
Spartan3 1500 / 2000 Evaluation Board. STw5093 offers a number of programmable
functions accessed through a serial control channel. The PCM interface supports both
non-delayed (normal and reverse) and delayed frame synchronization modes. STw5093
can be configured either as a 14-bit linear or as an 8-bit companded PCM coder.
Additionally to the CODEC/FILTER function, STw5093 includes a Tone/Ring/DTMF
generator, a side-tone generation, and a buzzer driver output. Figure 6 details the
schematic interface.
Figure9: STw5093 Circuit Diagram
STw5093
XC3S1500 / 2000 PIN
23 COD_AUXCLK
N7
30 MCLK
N8
29 COD_FS
G15
28 COD_DR
F15
27 - COD_DX
E15
STw5093
XC3S1500 / 2000 PIN
20 COD_CCLK
B15
25 COD_CO
A15
22 COD_CI
H14
21 COD_CS
T8
Table 15: Audio CODEC FPGA Signal Connections XC3S1500 / 2000
16
Analog to Digital Converter

The Spartan3 - 1500 / 2000 Evaluation Board includes Linear Technologies LTC1865L
16 bit 150ksps Analog to Digital Converters (ADCs). The ADC can be used in ratio
metric applications or with external references. The high impedance analog inputs and
the ability to operate with reduced spans down to 1V full scale allow direct connection to
signal sources in many applications, eliminating the need for external gain stages.
LTC1865L
SPI_AD_ SDI
SPI_AD_ SDO
AD_CONV_ST
SPI_AD_ SCK
XC3S1500 / 2000 PIN

M3
M2
R21
M5
Table16: LTC1865L ADC SPI Interface XC3S1500 / 2000
Analog to Digital Converter Signal Input Header / Jumper Settings

LTC1865L
ADC_CH0
ADC_CH1
ADC_CH0 Potentiometer
Jumper / Connector / Pin

J10 1 - 2 Closed / J9 / Pin 1
NA / J9 / Pin 2
J10 2 3 Closed / J9 / Pin 1
Table 17: LTC1865L ADC Signal Input Header / Jumper Settings
Figure 10: Analog to Digital Circuit

17
Digital to Analog Converter

The Spartan3 - 1500 / 2000 Evaluation Board includes Linear Technologies LTC1654L
14 bit, 8us conversion rate Digital to Analog Converters (DAC). The LTC1654 is a dual,
rail-to-rail voltage output, 14-bit digital-to-analog converter (DAC) which includes
output buffer amplifiers and a flexible serial interface. The LTC1654 has two
programmable speeds: a FAST and SLOW mode with 1LSB settling times of 3.5ms or
8ms respectively and supply currents of 750mA and 450mA in the two modes. The
LTC1654 also has shutdown capability, power-on reset and a clear function to 0V.
LTC1654
SPI_DAC_CLOCK
SPI_DAC_MOSI
SPI_DAC_MISO
DAC_LD
XC3S1500 / 2000 PIN

R19
R20
H1
D1
Table18: LTC1654 DAC SPI I/F
Digital to Analog Converter Signal Input Header / Jumper Settings

LTC1654
VoutA
VoutB
Connector / Pin
J5 / Pin 2
J5 / Pin 3
Table 19: LTC1654 DAC Signal Input Header
Figure 4 LTC1654 DAC Circuit
18
SDRAM Interface
The Spartan3 1500 / 2000 Evaluation Board is provided with two ISSI42S16400
4X1MX16 SDRAM that interfaces with the XC3S1500 / 2000 FPGA. The ISSI42S16400
is organized as 1,048,576 bits x 16-bits x 4 bank and is a fully pipelined architecture. Pin
connections are listed in table 21.
SDRAM PIN
SDRAM_D0
SDRAM_D1
SDRAM_D2
SDRAM_D3
SDRAM_D4
SDRAM_D5
SDRAM_D6
SDRAM_D7
SDRAM_D8
SDRAM_D9
SDRAM_D10
SDRAM_D11
SDRAM_D12
SDRAM_D13
SDRAM_D14
SDRAM_D15
SDRAM_D16
SDRAM_D17
SDRAM_D18
SDRAM_D19
SDRAM_D20
SDRAM_D21
SDRAM_D22
SDRAM_D23
SDRAM_D24
SDRAM_D25
SDRAM_D26
SDRAM_D27
SDRAM_D28
1500 / 2000 PIN

L19
L20
L21
L22
L23
L25
L26
M19
M20
M21
M22
M24
M26
N19
N20
N21
N22
N23
N24
N25
D25
H24
K21
M25
N26
P19
P20
P21
P22
Table 21: SDRAM PIN I/F
19
SDRAM PIN
SDRAM_D29
SDRAM_D30
SDRAM_D31
SDRAM_A0
SDRAM_ A1
SDRAM_ A2
SDRAM_ A3
SDRAM_A4
SDRAM_A5
SDRAM_A6
SDRAM_A7
SDRAM_A8
SDRAM_A9
SDRAM_A10
SDRAM_A11
CKE
CLK
UDQM0
SDRAM BA0
SDRAM BA1
SDRAM BA2
SDRAM BA3
LDQM0
/WE
/CAS
/RAS
/CS
LDQM1
UDQM1
1500 / 2000 PIN

P23
P24
P25
J20
J21
J22
J23
J24
J25
K20
K22
K23
K24
K25
K26
H20
H21
AC18
D26
E23
E24
G26
AA19
H26
H23
H22
H25
AC19
AD18
NBT SSRAM Interface (Alternative Memory Not Included on

standard build)
The Spartan3 1500 / 2000 Evaluation Board is available with a GSI GS8320V32
Synchronous 1M x 32 SRAM for high speed memory applications such as DSP. The
platform can be order with the SSRAM or the SDRAM. The signals are shared with the
SDRAM interface and are called out bellow.
SSRAM PIN
SSRAM_D0
SSRAM_D1
SSRAM_D2
SSRAM_D3
SSRAM_D4
SSRAM_D5
SSRAM_D6
SSRAM_D7
SSRAM_D8
SSRAM_D9
SSRAM_D10
SSRAM_D11
SSRAM_D12
SSRAM_D13
SSRAM_D14
SSRAM_D15
SSRAM_D16
SSRAM_D17
SSRAM_D18
SSRAM_D19
SSRAM_D20
SSRAM_D21
SSRAM_D22
SSRAM_D23
SSRAM_D24
SSRAM_D25
SSRAM_D26
SSRAM_D27
SSRAM_D28
SSRAM_D29
SSRAM_D30
SSRAM_D31
1500 / 2000 PIN

L19
L20
L21
L22
L23
L25
L26
M19
M20
M21
M22
M24
M26
N19
N20
N21
N22
N23
N24
N25
D25
H24
K21
M25
N26
P19
P20
P21
P22
P23
P24
P25
Table 22: SSRAM PIN I/F
20
SSRAM PIN
SSRAM_A0
SSRAM_ A1
SSRAM_ A2
SSRAM_ A3
SSRAM_A4
SSRAM_A5
SSRAM_A6
SSRAM_A7
SSRAM_A8
SSRAM_A9
SSRAM_A10
SSRAM_A11
SSRAM_A12
SSRAM_A13
SSRAM_A14
SSRAM_A15
SSRAM_A16
SSRAM_A17
SSRAM_A18
SSRAM_A19
FT
CLK
BA#
BB#
BC#
BD#
GW#
G#
BW#
E1#
1500 / 2000 PIN

J20
J21
J22
J23
J24
J25
K20
K22
K23
K24
K25
K26
R25
U21
AB24
C23
B23
F21
E21
C22
P26
H21
D26
F23
F24
G26
H26
H23
H22
H25
Flash Interface
The Spartan3 1500 / 2000 Evaluation Board includes a 32Mb Flash, configurable as x8 or
x16 via the Byte Pin, the flash aids in the development of Microblaze soft processor
cores from Xilinx.
The memory is divided into blocks that can be erased independently so it is possible to
preserve valid data while old data is erased. Each block can be protected independently to
prevent accidental Program or Erase commands from modifying the memory. Program
and Erase commands are written to the Command Interface of the memory. An on-chip
Program/Erase Controller simplifies the process of programming or erasing the memory
by taking care of all of the special operations that are required to update the memory
contents. The following table details the pin connections between the Spartan3 1500 /
2000 and the Flash.
Flash PIN
1 A15
2 A14
3 A13
4 A12
5 A11
6 A10
7 A9
8 A8
9 A19
10 A20
11 - /WE
12 - /RP
13 NC
14 /WP
15 R/B Flash Ready
16 A18
17 A17
18 A7
19 - A6
20 A5
21 A4
22 A3
1500 / 2000 PIN

AF21
AF20
AF19
AF15
AE24
AE23
AE22
AE21
Y17
AD22
AC16
AB17
Flash PIN
23 A2
24 A1
25 A0
26 - /CE
28 - /OE
29 - DQ0
30 DQ8
31 DQ1
32 DQ9
33 DQ2
34 DQ10
35 DQ3
36 DQ11
38 DQ4
39 DQ12
40 DQ5
41 DQ13
42 DQ6
43 DQ14
44 DQ7
45 DQ15
47 - /BYTE
48 A16
AC17
AB21
AF24
AF23
AE20
AE19
AE15
AD23
AD21
Table 23: Flash PIN I/F XC3S1500 / 2000
21
1500 / 2000 PIN

AD15
AC21
AC20
AB20
AB16
AB22
Y18
AC22
Y19
W14
AA15
Y14
AA16
AA14
AA17
W15
AA18
W16
AA20
Y16
AB15
AF17
AF22
Test Point Headers 3.3V

The Spartan3 1500 / 2000 Evaluation Board has 73, 3.3V test point interface for user
input, connector J24, J25, J32 & Test Pins PD1 PD15 interface directly to the
XC3S1500 / 2000.
J24 Position
1 LV_I/O_0
3 LV_I/O_2
5 LV_I/O_4
7 LV_I/O_6
9 LV_I/O_8
11 LV_I/O_10
13 LV_I/O_12
15 LV_I/O_14
17 LV_I/O_16
19 LV_I/O_18
21 - LV_I/O_20
23 - LV_I/O_22
25 - LV_I/O_24
27 - LV_I/O_26
29 - LV_I/O_28
31 - LV_I/O_30
33
35
1500 / 2000 PIN

AB8
AF10
AE10
AD9
R24
AB19
W23
AC25
AB25
W21
V25
Y21
Y23
AA24
G21
G23
3.3V
3.3V
J24 Position
2 LV_I/O_1
4 LV_I/O_3
6 LV_I/O_5
8 LV_I/O_7
10 LV_I/O_9
12 LV_I/O_11
14 LV_I/O_13
16 LV_I/O_15
18 LV_I/O_17
20 LV_I/O_19
22 - LV_I/O_21
24 - LV_I/O_23
26 - LV_I/O_25
28 - LV_I/O_27
30 - LV_I/O_29
32 - LV_I/O_31
34
36
1500 / 2000 PIN

AF11
AE11
AE9
AD8
AB18
AA25
AC26
AB26
AA26
W20
Y20
Y22
AA23
G20
G22
G25
GND
GND
Table 24: J24 3.3V Test Point Header PIN Connections XC3S1500 / 2000
J25 Position
1 LV2_I/O_0
3 LV2_I/O_2
5 LV2_I/O_4
7 LV2_I/O_6
9 LV2_I/O_8
11 LV2_I/O_10
13 LV2_I/O_12
15 LV2_I/O_14
17 LV2_I/O_16
19 LV2_I/O_18
21 LV2_I/O_20
23 LV2_I/O_22
25 LV2_I/O_24
27 LV2_I/O_26
29 LV2_I/O_28
31 LV2_I/O_30
33
35
1500 / 2000 PIN

D8
D9
B9
B11
A3
A6
C8
E13
H11
F7
G14
D14
A22
D16
F14
C15
+12V
-12V
J25 Position
2 LV2_I/O_1
4 LV2_I/O_3
6 LV2_I/O_5
8 LV2_I/O_7
10 LV2_I/O_9
12 LV2_I/O_11
14 LV2_I/O_13
16 LV2_I/O_15
18 LV2_I/O_17
20 LV2_I/O_19
22 LV2_I/O_21
24 LV2_I/O_23
26 LV2_I/O_25
28 LV2_I/O_27
30 LV2_I/O_29
32 LV2_I/O_31
34
36
22
1500 / 2000 PIN

E8
E9
C9
A11
A5
C4
C12
H12
B3
G10
E14
A14
A23
E18
F20
C17
GND
GND
J32 Position
XC3S1500 / 2000 PIN
J32 Position
2000 PIN
1 EXP_SLOT_I/O_30
E2
2 EXP_SLOT_I/O_31
3 EXP_SLOT_I/O_32
E4
4 EXP_SLOT_I/O_33
5 EXP_SLOT_I/O_34
F2
6 EXP_SLOT_I/O_35
7 EXP_SLOT_I/O_36
F4
8 EXP_SLOT_I/O_37
9 EXP_SLOT_I/O_38
G2
10 EXP_SLOT_I/O_39
11 - EXP_SLOT_I/O_40
G5
G7
H3
H6
J3
J4
XC3S1500 /
E3
F1
F3
G1
G4
G6
H2
H4
J2
J4
J6
PD#
1
2
3
4
5
6
7
8
LOCATION/CONNECTION
PD#
J31 PIN 2
J31 PIN 55
1500 / 2000 AA19
1500 / 2000 AC18
1500 / 2000 AC19
1500 / 2000 AD18
1500 / 2000 AD19
GND
9
10
11
12
13
14
15
Table 27: PD Test Points Connections
23
LOCATION/ CONNECTION
1500 / 2000 AE16

GND
1500 / 2000 AE17
GND
1500 / 2000 AE18
GND
1500 / 2000 AF17
LVDS Test Point Header

The Spartan3 1500 / 2000 Evaluation Board has 20 LVDS pairs available for high-speed
communications; the arraignment is 8TX pairs, 8RX pairs, 1RX control, 1TX control,
1RX clock and 1TX clock.
J23 Position
1500 / 2000 PIN
1 LVDS_CNT_TX0_P
E10
3 LVDS_CNT_TX0_N
F10
5 LVDS_I/O_TX_0_P
A4
7 LVDS_I/O_TX_0_N
B4
9 LVDS_I/O_TX_1_P
B5
11 LVDS_I/O_TX_1_N
C5
13 LVDS_I/O_TX_2_P
D6
15 LVDS_I/O_TX_2_N
E6
17 LVDS_I/O_TX_3_P
B6
19 LVDS_I/O_TX_3_N
C6
21 - LVDS_I/O_TX_4_P
D7
23 - LVDS_I/O_TX_4_N
E7
A7
B7
A8
B8
F9
G9
37 LVDS_CN_CLK_P
F8
39 LVDS_CN_CLK_N
G8
J23 Position
1500 / 2000 PIN
2 LVDS_I/O_RX_0_P
C10
4 LVDS_I/O_RX_0_N
D10
6 LVDS_I/O_RX_1_P
F11
8 LVDS_I/O_RX_1_N
G11
10 LVDS_I/O_RX_2_P
D11
12 LVDS_I/O_RX_2_N
E11
14 LVDS_I/O_RX_3_P
H13
16 LVDS_I/O_RX_3_N
G12
18 LVDS_I/O_RX_4_P
E12
20 LVDS_I/O_RX_4_N
F12
22 - LVDS_I/O_RX_5_P
A12
24 - LVDS_I/O_RX_5_N
B12
G13
F13
A10
B10
34 LVDS_CNT_RX0_P
D13
36 - LVDS_CNT_RX0_N
C13
38 LVDS_CN_CLK2_P
A13
40 LVDS_CN_CLK2_N
B13
Table 28: J23 LVDS PIN Connections
24
10/100 Ethernet Media Access Controller

The Spartan3 1500 / 2000 Evaluation Board includes the SMSC LAN91C111 10/100
Ethernet MAC with integrated 802.3 Physical Layer, for twisted pair applications. The
bus interface is accessed as a 32bit I/O slave along with a slave DMA type data path that
accepts burst transfers.
LAN91C111
SMSC_DATA_0
SMSC_DATA_1
SMSC_DATA_2
SMSC_DATA_3
SMSC_DATA_4
SMSC_DATA_5
SMSC_DATA_6
SMSC_DATA_7
SMSC_DATA_8
SMSC_DATA_9
SMSC_DATA_10
SMSC_DATA_11
SMSC_DATA_12
SMSC_DATA_13
SMSC_DATA_14
SMSC_DATA_15
SMSC_DATA_16
SMSC_DATA_17
SMSC_DATA_18
SMSC_DATA_19
SMSC_DATA_20
SMSC_DATA_21
SMSC_DATA_22
SMSC_DATA_23
SMSC_DATA_24
SMSC_DATA_25
SMSC_DATA_26
SMSC_DATA_27
SMSC_DATA_28
SMSC_DATA_29
SMSC_DATA_30
SMSC_DATA_31
1500 / 2000 PIN

AB6
AB7
AB9
AB10
AB11
AC6
AC7
AC8
AC9
AC10
AC11
AD4
AD5
AD6
AD10
AD12
AE4
AE5
AE6
AE8
AF4
AF6
AF8
U3
U5
U6
U7
V2
V3
V4
V5
V6
LAN91C111
SMSC_Addr_0
SMSC_Addr_1
SMSC_Addr_2
SMSC_Addr_3
SMSC_Addr_4
SMSC_Addr_5
SMSC_Addr_6
SMSC_Addr_7
SMSC_Addr_8
SMSC_Addr_9
SMSC_Addr_10
SMSC_Addr_11
SMSC_Addr_12
SMSC_Addr_13
SMSC_Addr_14
SMSC_nBE0
SMSC_nBE1
SMSC_nBE2
SMSC_nBE3
RESET_N
SMSC_ARDY
SMSC_INTR
SMSC_nLDEV
SMSC_nRD
SMSC_nWR
SMSC_nCS
SMSC_AEN
LCLK
W/Nr
RDYRTN
CYCLE
nADS
Table 29: SMSC 91C111 FPGA Pin Connections XC3S1500 / 2000
25
1500 / 2000 PIN

AF13
P2
P3
P4
P5
P6
P7
P8
R1
R3
R5
R6
R7
R8
T1
T2
T4
T5
T6
Y12
AA13
AF5
AF12
AA11
P4
AE12
Y10
R20
T7
U2
R24
R26
10/100 Ethernet Physical Interface

The Spartan3 1500 / 2000 Evaluation Board includes a 10/100 Ethernet Physical
Interface for implementing an on chip Ethernet Media Access Controller. The
ICS1893BF incorporates Auto-MDIX feature that automatically corrects crossover errors
in plant wiring.
ICS1893 Signal
RXD3
RXD2
RXD1
RXD0
RXDV
RXCLK
RXER
COL
CRS
10/100
1500 / 2000 Pin

AB5
AB12
AB13
AC5
AC13
AE13
AA6
AA7
AA8
H7
ICS1893 Signal
TXD3
TXD2
TXD1
TXD0
TXCLK
TXEN
MDIO
MDC
ICS_RESET_n
1500 / 2000 Pin

Y11
Y9
Y8
W13
W11
W12
AA10
AA9
Y13
Table 30: ICS1893 Pin Connections XC3S1500 / 2000
Linear Technology High Speed Analog to Digital Interface

The Spartan3 1500 / 2000 Evaluation Board includes the physical interface to the
Linear Technology high-speed A/D evaluation acquisition boards. The family includes
the following converter evaluation boards.
Eval Board Part #
520B-A
520B-B
520B-C
520B-D
520B-E
520B-F
520B-G
520B-H
520B-I
520B-J
520B-K
ADC PART #
LTC1748
LTC1748
LTC1745
LTC1746
LTC1747
LTC1747
LTC1742
LTC1742
LTC1741
LTC1741
LTC1743
RESOLUTION
14 Bit
14 Bit
12 Bit
14 Bit
12 Bit
12 Bit
14 Bit
14 Bit
12 Bit
12 Bit
12 Bit
SAMPLE RATE
80Msps
80Msps
25Msps
25Msps
80Msps
65Msps
65Msps
65Msps
65Msps
65Msps
50Msps
Table 31: LTC High Speed ADC Evaluation Board Part Numbers
26
INPUT FREQUENCY
Ain < 40MHz

Ain > 40MHz
Ain < 40MHz
Ain < 40MHz
Ain < 40MHz
Ain > 40MHz
Ain < 40MHz
Ain > 40MHz
Ain < 40MHz
Ain > 40MHz
Ain < 40MHz
Figure 12: LTC Evaluation Board
Linear Technology High Speed ADC Interface Connections

LTC A/D Interface
1500 / 2000 PIN LTC A/D Interface
1500 / 2000 PIN
D0 EXP SLOT_I/O_66
M1
D8 EXP SLOT_I/O_58
K6
D1 EXP SLOT_I/O_65
L7
D9 EXP SLOT_I/O_57
K5
D2 EXP SLOT_I/O_64
L6
D10 EXP SLOT_I/O_56
K4
D3 EXP SLOT_I/O_63
L5
D11 EXP SLOT_I/O_55
K3
D4 EXP SLOT_I/O_62
L4
D12 EXP SLOT_I/O_54
K2
D5 EXP SLOT_I/O_61
L2
D13 EXP SLOT_I/O_53
K1
D6 EXP SLOT_I/O_60
L1
OF EXP SLOT_I/O_52
J7
D7 EXP SLOT_I/O_59
K7
CLK_ADC
AD13
Table32: J29 LTC ADC Interface XC3S1500 / 2000
27
Figure 13: J29 Circuit Diagram
28
Intersil High Speed Digital to Analog Interface

The Spartan 3 - 1500 / 2000 Evaluation Board includes the interface to Intersil high speed
DACs ISL5x29EVAL1 evaluation cards for developing high performance DSP
applications such as Quadrature Transmit with an IF Range 0 80MHz and Medical/Test
Instrumentation and Equipment. Table 8 details the available evaluation platforms from
Intersil.
Intersil Part Number
ISL5629EVAL1
ISL5729EVAL1
ISL5829EVAL1
ISL5929EVAL1
Number of bits
2x8
2x10
2x12
2x14
Clock Speed
210MHz
210MHz
210MHz
210MHz
Table 33: Intersil Evaluation Board Part Numbers
Intersil High Speed DAC Interface Connections

Intersil DAC Signal
Q_Data_0 - EXP_SLOT_I/O_29
CLK - EXP_SLOT_I/O_23
XC3S1500 / 2000 Pin

E1
D2
AC2
AA2
W3
U4
P1
AC1
AB4
AB3
AB2
AB1
AA5
AA4
R2
Table 34: J27 Intersil DAC Interface XC3S1500 / 2000
29
Figure14: J27 Circuit Diagram
Intersil DAC Signal

I_Data_0 - EXP_SLOT_I/O_14
CLK - EXP_SLOT_I/O_8
XC3S1500 / 2000 Pin

AA3
AA1
Y7
Y6
Y5
Y2
Y1
W7
W6
W5
W4
W2
W1
V7
Y4
Table 35: J28 Intersil DAC Interface XC3S1500 / 2000
30
Graphical LCD Interface

The Spartan3 1500 / 2000 Evaluation Board interfaces directly to the Logic Product
Developments Display Kits, to review the available Display Kits reference
http://www.logicpd.com/eps/peripherals.php
The Spartan3 1500 / 2000 Evaluation Board has a 2x30 pin 0.100" header (J31) that
connects all of the LCD signals directly from the evaluation boards FPGA. Depending on
your specific display, only a few of the LCD signals may be needed. Table details the
physical connections to the XC3S1500 / 2000 FPGA. Figure details the connector circuit.
31
J31- LCD I/F

1500 / 2000 Pin
LCD_MOD
D21
LCD_SPL
E20
LCD_SPS
B21
LCD_CLK_RETURN
G19
LCD_VEEEN
B22
LCD_DON
B20
LCD_CLK
B14
HSYNC
G18
VSYNC
D17
LCD_REV
C21
LCD_HRLP
B16
LCD_PSAVE
A21
LCD_CLS
A16
LCD_VDDEN
LCD_MDISP
D20
LCD_PWM
H15
RED0
F19
J31-LCD I/F
BLUE5
BLUE4
BLUE3
BLUE2
BLUE1
BLUE0
GREEN5
GREEN4
GREEN3
GREEN2
GREEN1
GREEN0
RED5
RED4
RED3
RED2
RED1
Table 36: J31 LCD I/F Connections XC3S1500 / 2000
32
1500 / 2000 Pin

E16
F16
G16
H16
A17
B17
E17
F17
G17
B18
C18
F18
A19
B19
C19
D19
E19
Agilent Soft Touch Probe Interface

The Spartan3 1500 / 2000 Evaluation Board includes the Agilent Soft Touch Probe,
E5394A which is a 34-channel single-ended soft touch connectorless probe compatible
with all Agilent logic analyzers that have a 40-pin pod connector. It is capable of
acquiring data at the maximum rates of the logic analyzer it is connected to.
AGILENT SOFT TOUCH PROBE

FOOTPRINT
U66
LV2_I/O_1
LV2_I/O_3
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
LV2_I/O_5
LV2_I/O_7
LV2_I/O_9
LV2_I/O_11
LV2_I/O_13
LV2_I/O_15
LV2_I/O_17
LV2_I/O_19
LV2_I/O_21
LV2_I/O_23
LV2_I/O_25
LV2_I/O_27
LV2_I/O_29
LV2_I/O_31
GND
D0
D2
D1
D3
GND
GND
D4
D6
D5
D7
GND
GND
CK 1+
D8
GND/NC
D9
GND
GND
D10
D12
D11
D13
GND
GND
D14
D0
D15
D1
GND
GND
D2
D4
D3
D5
GND
GND
D6
GND/NC
D7
CK2 +
GND
GND
D8
D10
D9
D11
GND
GND
D12
D14
D13
D15
GND
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
LV2_I/O_0
LV2_I/O_2
LV2_I/O_4
LV2_I/O_6
LV2_I/O_8
LV2_I/O_10
LV2_I/O_12
LV2_I/O_14
LV2_I/O_16
LV2_I/O_18
LV2_I/O_20
LV2_I/O_22
LV2_I/O_24
LV2_I/O_26
LV2_I/O_28
LV2_I/O_30
AGILENT E5404A
GND
GND
Figure 17: Agilent E5394A Soft Touch Probe Connector Diagram
33
Programming Interface
The Spartan3 1500 / 2000 Evaluation Board supports JTAG configuration by the Xilinx
JTAG Cable III (Connector J3) and Cable IV (Connector J4). Table 14 and 15 detail the
physical pin connections to the XC3S1500 / 2000 FPGA.
Programming Status LED
LD10 Programming status LED Done Pin going high, confirming configuration of the
FPGA.
Cable III J3
3 TCK
4 TDO
5 TDI
6 - TMS
XC3S1500 / 2000 PIN

B24
D24
C1
A24
Table 37: Cable III Interface
Cable IV J4
6 - TCK
8 - TDO
10 TDI
4 - TMS
XC3S1500 / 2000 PIN

B24
D24
C1
A24
Table 38: Cable IV Interface
Operating and Storage Environments

Temperature
The HW-AFX-SP3-1500 / 2000 development board can be safely stored at temperatures
ranging from -20 85 C. The HW-AFX-SP3-1500 / 2000 development board will
operate reliably in an ambient temperature of 0 - 70 C.
Humidity
The HW-AFX-SP3-1500 / 2000 development board is reliable in storage and operating in
a relative humidity of 10% to 95% non-condensing for the appropriate temperature
ranges listed above.
Regulatory Compliance (FCC Part 15 Class B, and Part 68)

This product is sold as an evaluation platform only. No EMI testing was performed.
34

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Nu Horizons Electronics

Spartan3 1500 / 2000 Evaluation Platform

Figure1: Nu Horizons Electronics Spartan3 1500 / 2000 Evaluation Board Block

Evaluation Board Contents.................................................................................. 7

Board Overview .................................................................................................... 7

CAN 2.0B High Speed Transceiver ............................................................................... 13

10/100 Ethernet Media Access Controller .................................................................... 25

Based on the Spartan 3 - 1.5 Million Gate FPGA

Evaluation Board Contents

2.5V /800mA LVDS I/F

1.8V / 2.5V/ 3.3V 750mA Adjustable

+12 & -12V /75mA

Power Status LED

XC3S1500 / 2000 PIN

Table 1: LED Pin Connections to XC3S1500 / 2000

XC3S1500 / 2000 PIN

Table 2: Pushbutton Pin Connections to XC3S1500 / 2000

4x24 Character LCD Display

Table 3: LCD PIN Connections XC3S1500 / 2000

4x24 Character LCD Display Read/Write Timing Chart

Figure 2: 4x24 Character LCD Display Read/Write Waveforms

PLL Clock Multiplier

Figure 3: ICS511 PLL Clock Multiplier Circuit

Figure 4: U54 Oscillator Socket

XC3S1500 / 2000 Pin

Table 4: Clock PIN Connections XC3S1500 / 2000

Table 5 Clock Output Table

Programmable Frequency Synthesizer

M Divide M8-256 M7-128

Table 6: M Divide Function Table

Table 7: N Output Divider Function Table

Output Min/ MHz Output Max/MHz

Figure4: ICS84021 Frequency Divider

ICS84021 Clock Signal

XC3S1500 / 2000 Pin

Table 8: ICS84201 Clock Signal XC3S1500 / 2000

XC3S1500 / 2000 PIN

Table 9: RS-232 Port 1 Pins XC3S1500 / 2000

XC3S1500 / 2000 PIN

Table 10: RS-232 Port 2 Pins XC3S1500 / 2000

Figure 5: RS232 Port 1 & 2

RS232 Speed Select Jumper

Table 11: RS232 Speed Select Jumper Settings

CAN 2.0B High Speed Transceiver

Figure 6: CAN 2.0B Bus Controller & High-Speed Transceiver

The L9616 is a bidirectional transceiver for signal conditioning and processing in

J11 ASC Speed Select Jumper

Table 13:J11 CAN ASC Settings

Figure 7: CAN Interface

Table14: PS2 Port Interface XC3S1500 / 2000

Figure 8: PS2 Port Interface

14bit Linear CODEC

Figure9: STw5093 Circuit Diagram

Table 15: Audio CODEC FPGA Signal Connections XC3S1500 / 2000

Analog to Digital Converter

XC3S1500 / 2000 PIN

Table16: LTC1865L ADC SPI Interface XC3S1500 / 2000

Analog to Digital Converter Signal Input Header / Jumper Settings

Jumper / Connector / Pin

Table 17: LTC1865L ADC Signal Input Header / Jumper Settings

Figure 10: Analog to Digital Circuit

Digital to Analog Converter