New Structure for Adder with Improved Speed, Area

and Power


Fatemeh Karami H.
Department of Electrical and Computer Engineering
Isfahan University of Technology
Isfahan 84156-83111, Iran
f.karamihorestani@ec.iut.ac.ir
Ali K. Horestani
School of Electrical and Electronic Engineering
The University of Adelaide
Adelaide, SA 5005, Australia
akarami@eleceng.adelaide.edu.au


Abstract Adders are the main parts of processing circuits and
play an important role in all mathematical operations like
subtraction, multiplication, division, etc. Carry Look ahead
Adder (CLA) is one of the fastest adder structures that is widely
used in the processing circuits. In this article a new structure for
adder is proposed. The results show that compared to the
previous common Modified Carry Look ahead Adder (MCLA)
structure, the proposed structure has very smaller on-chip area
and delay and also it has lower power consumption. Using the
proposed structure a 64-bit adder is designed and results are
presented. The circuit is designed in TSMC 0.18m CMOS
technology with 1.8v power supply and simulated with HSPICE.
Keywords-component; Ripple Carry Adder, Carry Look ahead
Adder, Delay, Area.
I. INTRODUCTION
Addition is one of the most important operations in
processors and digital computer systems and adder units are the
basic and the most frequently used parts in almost all
arithmetic processors [1], [2]. So adders speed plays a critical
role in determining processors speed. Improving the
performance of adders will enhance behavior of the processors
speed and consequently all the computation processes [1], [3].
Among several types of adders, Ripple Carry Adder (RCA)
is the most widely used structure [4], [5]. There are several
factors that contribute to the adder delay, among them the carry
generation delay and the delay of its propagation from less
significant stages to higher significant stages are the most
important ones [1]. Some techniques based on carry generation
method, such as Carry Select, Carry Skip and Carry Look
ahead techniques have been introduced to improve the speed of
Ripple Carry Adder. However, in all cases there is a tradeoff
between speed and on-chip area. Carry Look ahead Adder is
much faster than the two other adders [6], [7]. However, this
adder occupies a larger on-chip area than others due to the
extra space which is occupied by carry anticipating blocks [6].
Considering the advantages and disadvantages of RCA and
CLA the purpose of this paper is to propose a new structure to
achieve higher operation speed in a much smaller on-chip area.
The proposed structure slightly improves the power
consumption as well.
II. RIPPLE CARRY ADDER AND CARRY LOOK AHEAD ADDER
STRUCTURES
A. Ripple Carry Adder
Fig. 1 depicts Ripple Carry Adder. This adder, which is the
simplest Binary Adder is constructed by cascading full adder
blocks [8]. In this adder A
i
and B
i
are bits to be added and C
i
is
carry bit from previous block, which is of lower significance.
Each block has two outputs, S
i
which is summation of A
i
and
B
i
, and carry C
i+1
which is passed to the next stage. S
i
and C
i+1

are computed by (1) and (2). Carry C
i
has to be passed from all
stages with smaller index (less significant stages) to produce
summation and carry bits for higher indexed stage (higher
significant stage). Therefore, computational delay to produce S
i

and C
i
is increased rapidly with the increase of their index.
Carry Look ahead Adder was proposed to address this issue
[9]. In order to avoid the carry propagation delay, in CLA,
carries of all stages are produced separately in parallel by using
P and G signals that will be explained in next section. When
the adder inputs are loaded in parallel, all the G
i
and P
i
signals
will be generated at the same time. In fact the carry-look ahead
units improve the speed of carry generation and propagation by
computing each carry bit independently and in parallel with
other carry bits. In this case, the delay of carry producing will
not propagate to higher stages [10].


Figure 1. Ripple Carry Adder block diagram


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. . . . . . . .
i i i i i i i i i i i i i
i i i
S A B C A B C A B C A B C
A B C
' ' ' ' ' '
= + + +
=
(1)

1
. . .
i i i i i i i
C A B A C B C
+
= + + (2)

B. Carry Look ahead Adder
Fig. 2 shows a sample of CLA structure which is called
Simplified Carry Look ahead Adder (SpCLA) [11]. In this
structure, Propagate signal (P) and Generate signal (G) are
produced to increase the speed of carry computation. These
two signals are given by (3) and (4). [11] also introduced a
Modified Carry Look ahead Adder (MCLA) in order to
decrease the delay and consequently to improve the adders
speed.
i i i
P A B = (3)

i i i
G A B = (4)

The modified version of CLA is different from SpCLA
structure in the last gate of producing path of the generate
signal (G). In fact, modified version uses NAND gate instead
of AND gate at the end of the G generating path and thus G
signal is yielded. MCLA contains two parts; arithmetic adder
circuits (Computational units) and carry look-ahead circuits.
Computational units are identical for all adder units, so called
Metamorphosis of Partial Full Adder (MPFA). MPFA units are
responsible for generation of G
i
, P
i
and S
i
.

Fig. 3 shows a unit
of MPFA. MPFA unit in each stage has three inputs, A
i
, B
i
and
C
i
, and three outputs, S
i
, P
i
and
i
G
, where i is the index of stage
and A
i
, B
i
, C
i
, and S
i
are bits of augend, addend, carry, and sum
at stage i, respectively [11]. The carry of the (i)
th
stage which is
also the input carry of the (i+1)
th
stage can be calculated by
outputs of (i)
th
stage using (5).
( )
( ) 1
. .
i i i i
C G P C
+
'
'
'
= (5)
From equation (5), the carry output of each stage can be
calculated from equations (6) to (9) where C
0
is the initial input
carry of the adder.
( )
( ) 1 0 0 0
. . C G P C
'
'
'
= (6)
( ) ( )
( ) 2 1 1 0 1 0 0
. . . . . C G P G P P C
'
'
'
'
= (7)
( ) ( ) ( )
( ) 3 2 2 1 2 1 0 2 1 0 0
. . . . . . . . . C G P G P P G P P P C
'
' ' '
'
= (8)
( ) ( )
( ) ( )
3 3 2 3 2 1
4
3 2 1 0 3 2 1 0 0
. . . . . .
. . . . . . . .
G P G P P G
C
P P P G P P P P C
'
| | ' '
|
=
|
' '
\ .
(9)

Figure. 2 4-bit SpCLA structure. It contains four MPFA blocks. Carries signals are generated using P and G' signals. P and
G signals are used to produce C4 which is the carry out of 4-bit adder.


Figure.3 Metamorphosis of partial full adder
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Group Propagate (P
G
) and Inverse Group Generate (G'
G
)
signals are defined as (10) and (11).
3 2 1 0
. . .
G
P P P P P = (10)

3 3 2 3 2 1 3 2 1 0
. . . . . .
G
G G P G P P G P P P G = + + + (11)

Output carry signal of 4
th
block (C
4
) can be simplified as
(12).

4 0
.
G G
C G P C = + (12)

Other carries in each 4-bit adder block will be computed in
a same way [12], [13].
Since all inputs of adder stages (A
i
, B
i
, C
i
) are loaded to
MPFA blocks in parallel and in a same time, all P and G
signals are produced almost simultaneously. So, carry signals
are generated in Look ahead Carry Units (LCU) independently
and approximately in the same time and also with more speed
compare to Ripple Carry Adder [14].
III. PROPOSED STRUCTURE
As it is mentioned in the previous section, Ripple Carry
Adder has the advantage of consuming a small on-chip area but
it suffers from long carry propagation delay. On the order hand
Carry Look ahead adder benefits from much less carry
propagation delay but it consume much larger on-chip area.
Compared to CLA, this paper proposes a new adder, which
has higher speed and occupy smaller on-chip area.
In the proposed structure, (4i)
th
carries are the only carries
which are produced by Look ahead Carry Units and other
carries (C
4i+1
, C
4i+2
, C
4i+3
) are produced in the same way as
Ripple Carry Adder. Removing these LCUs results in reduction
of the loading on the P and G signals in each LCU block, and
faster production of P and G signals on the (4i)
th
carries.
Consequently summation signals speed and therefore adders
speed is increased. Also, on-chip area is significantly decreased
because the extra blocks for prediction of other carries are
removed. Simulation results also show that the power
consumption is slightly decreased.
Since proposed structure is a combination of RCA and
CLA structures it is called Ripple-Carry Look ahead Adder
(RCLA).
Critical path, path with maximum delay from inputs to
outputs, which dictates the speed of the circuit, is the path of
S
63
signal generation [12]. Generating paths of signals S
57
~S
63

and C
64
(over flow bit of 64-bit adder) also can have noticeable
delay. Therefore we compare two structure, proposed and
MCLA structure, for some end bits of the adder in worst case
condition. Figure 4 shows the waveforms of summation


a: Wave forms of the summation and carry out signals respectively in falling and rising
edges. S63 signal has maximum delay.
b: Wave forms of the summation and carry out signals respectively in rising and falling
edges. S63 signal has maximum delay.
Figure. 4 Wave forms of the summation and carry out (S57~S63 and C64 ) of MCLA structure in two states, rising and
falling edges. As it is shown, compared to the other outputs in worst case condition, S63 signal has maximum delay in
rising edge. Therefore the total delay of MCLA is related to it.
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signals S
57
~S
63
and C
64
of the MCLA structure in two states;
rising and falling edges in worst case. As it can be seen in the
figure, compared to the other summation signals S
63
signal has
more delay. Consequently, S
63
determines the total delay of this
64-bit adder and demonstrate the adders speed. Compared to
other signals, C
64
has very small delay because it is predicted
with LCUs. In order to compare the adders delay in the new
structure with delay of MCLA, Figure 5 shows the waveforms
of summation signals and carry overflow of the new structure
in worst case. It is clear that although in the proposed adder, S
63

generating path still is the critical path, it has much less delay
compared to the S
63
in MCLA in the same state.
IV. RESULTS
In order to compare the speed of MCLA and the proposed
structure, both circuits are designed in TSMC 0.18m CMOS
technology with 1.8v power supply and simulated with
HSPICE.Table. 1 shows the delay of last bits of summation as
well as carry over flow (S
63
and C
64
). As can be seen in the
table, maximum delay is related to S
63
, which is 2.19 ns in
MCLA structure compared to 2.02 ns in the proposed structure,
which shows 7.8% improvement in the speed of the new
proposed structure.
Table 2 compares the power consumption in MCLA to that
in the proposed structures. It also expresses the total number of
transistors used in each of the two structures, which represents
the total consumed on-chip area for each structure. Number of
transistors used in the new structure is 3872. Compared to the
MCLA with 4288 transistors, this number shows about 10%
decrease. So it can be concluded that compare to MCLA, the
proposed adder can be implemented in a 10% smaller on- chip
area.
In order to compare both parameters, speed and area,
simultaneously, parameter is defined as a product of delay
and total number of transistors [15]. In the same way,
parameter can be defined to be the product of delay, total
number of transistors and Power consumption. These values
are given in table. 3.
V. CONCLUSION
Adder units are the main part of processing systems. They
are often located in the critical path of the circuits. Therefore
their performance has a significant impact on processing
system performance. Since adder units are repetitively used in
processing and computer systems, on-chip area is another very
important factor of a high performance adder. Carry Look
ahead Adder is wildly used in processing and computing
systems because of its high speed compared to other types of
Figure. 5 Wave forms of the summation and carry out (S57~S63 and C64 ) of proposed structure in two states, rising and
falling edges. As it is shown, compared to the other outputs in worst case condition, S63 signal has maximum delay in
rising edge. Therefore the total delayof new structure is related to it.
a: Wave forms of the summation and carry out signals in respectively falling and rising edges.
S63 signal has maximum delay
b: Wave forms of the summation and carry out signals respectively in rising and falling
edges. S63 signal has maximum delay.
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adders such as ripple carry adder. However, it suffers from
consumption of a relatively large on-chip area, which is
basically due to Carry Look ahead blocks. In this article a new
method for add operations has been presented and based on
that a 64-bit adder has been designed and simulated. Results
show that the proposed structure can be implemented with 10
percent fewer transistors and consequently uses about 10% less
on-chip area compared to common MCLA while it is 7.8
percent faster than MCLA. Simulations also show that average
power consumption of the proposed structure is improved
about 2.1 percent with respect to MCLA. In conclusion,
compared to a 64-bit MCLA, the proposed adder benefits from




higher speed, smaller on-chip area and lower power
consumption.

ACKNOWLEDGMENT
The authors wish to acknowledge Mahmood Noruzi and
Zahra Shaterian for their assistance.

REFERENCES

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vol. 2.
Original MCLA Proposed Structure
N= Total number of
transistors
4288
3872
(10% decrease)
Pave (mw) 0.435
0.426
(2.1% decrease)
Original MCLA Proposed Structure
= d N 9391 7820
= d N Pave 4085 3332
Original MCLA Proposed Structure
d
e
l
a
y

S63
Rising Edge 2.19 ns 2.02 ns
Falling Edge 2.094 ns 1.894 ns
C64
Rising Edge 0.957 ns 0.915 ns
Falling Edge 0.795 ns 0.752 ns
d= Maximum Delay 2.19 ns 2.02 ns (7.8% decrease)

TABLE I. THE DELAY OF LAST BIT OF SUMMATION AND CARRY OVER FLOW (S63 AND C64) IN
64-BIT MCLA AND PROPOSED STRUCTURES. AS CAN BE SEEN, MAXIMUM DELAY IS RELATED TO S63 IN
BOTH MCLA AND PROPOSED STRUCTURE AND THE NEW PROPOSED STRUCTURE HAS 7.8%
IMPROVEMENT IN THE SPEED RATHER THAN MCLA.
TABLE II. COMPARISON OF POWER CONSUMPTION IN MCLA TO
THAT IN THE PROPOSED STRUCTURES. THIS TABLE ALSO EXPRESSES
THE TOTAL NUMBER OF TRANSISTORS USED IN EACH OF THE TWO
STRUCTURES. IT CAN BE CONCLUDED THAT COMPARE TO MCLA,
THE PROPOSED ADDER CAN BE IMPLEMENTED IN A 10% SMALLER
ON- CHIP AREA.
TABLE III. PARAMETER | IS DEFINED IN ORDER TO COMPARE
BOTH PARAMETERS, SPEED AND AREA, SIMULTANEOUSLY IN THE
SAME WAY, PARAMETER CAN BE DEFINED TO BE THE PRODUCT
OF DELAY, TOTAL NUMBER OF TRANSISTORS AND POWER
CONSUMPTION.
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[13] B. Lee and V. Oklobdzija, "Optimization and speed improvement
analysis of carry-lookahead adder structure," Twenty-Fourth Asilomar
Conference on Signals, Systems and Computers, 1990, p. 918.
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Multiplication for Cryptography", International Workshop on Signal
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