JOURNAL OF COMPUTING, VOLUME 4, ISSUE 5, MAY 2012, ISSN 2151-9617 https://sites.google.com/site/journalofcomputing WWW.JOURNALOFCOMPUTING.

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Simulation of different levels of Redundant-NOC topologies

Reza Kourdy Department of Computer Engineering Islamic Azad University, Khorramabad Branch, Iran Mohammad Reza Nouri rad Department of Computer Engineering Islamic Azad University, Khorramabad Branch, Iran

Abstract Networks on chips (NoCs) have been introduced as a remedy for the growing problems of current interconnects in VLSI chips. Being a relatively new domain in research, simulation tools for NoCs are scarce. To fill the gap, we use network simulator NS-2 for simulating NoCs, especially at high level chip design. The huge library of network elements along with its flexibility to accommodate customized designs, NS-2 becomes a viable choice for NoCs. We have used NS-2 to simulate our prototype of a fault tolerant protocol for NoCs. We simulated our NoC architecture using the widely used network simulator ns-2 and have obtained good performance. Index Terms integrated circuit (IC), Systems-on-chip (SOC), MPSoC, Topologies. Network on Chip (NOC), Reliability, Redundant-

1 INTRODUCTION

oore's law predicts that by 2008, it will be possible to integrate over a billion transistors on a single chip. Current core based on SOC methodologies will not respond to the needs of the billion transistor era. Network on Chip (NOC), a new chip design paradigm concurrently proposed by many research groups[1],[2],[3] is expected to be an important architectural choice for future SOCs. The proposed NOC architectures offer a general but fixed communication platform which can be reused for a large number of SOC designs. A concept of computer network in layers based on the classical OSI reference model is used by all of proposed NOC architectures. We predict that NOC architecture would facilitate reuse at various levels of system design, thus reducing the time to design and test. However, NOC research is still in its infancy. A higher-level modelling will give us the insight of knowing more about its architecture. We would use the tool, Network Simulator ns-2 [4],[5] which has been extensively used in the research for design and evaluation of public domain computer network, to evaluate various design options for NOC architecture, including the design of router, communication protocol, routing algorithms. This paper reports some experimental results based on the simulation of NOC using ns-2. In the following, we give a brief overview of our NOC architecture and introduction to ns-2. In section II, we describe how various aspects of our NOC architecture was modelled using ns-2. Chip integration has reached a stage where a complete system can be placed on a single chip. The integration has been made possible because of the rapid developments in the field of VLSI design. These chips, commonly termed as System on a chip (SoC), are primarily used in embed-

ded systems. While designing an SoC, a vendor may use a library of cores designed by external designers in addition to using cores from in-house libraries. Cores are basically predesigned models of complex functions termed as Intellectual Property Blocks (IP Blocks), Virtual Components (VC) or simply micros. One key issue in the SoC design is heterogeneity; components of various vendors with significantly distinct characteristics lie on the same chip, making the design process even more complex [6]. According to the International Technology Roadmap for Semiconductors (ITRS) before the end of this decade, chips will be designed with billions of transistors [7]. Such a development means that in near future we will have Application Specific Integrated Circuits (ASIC) that will comprise of hundreds of heterogeneous components integrated together to provide full functionality of an application. However, development of such chips is not an easy task as the number of transistors increases on-chip, so does the complexity of integrating them. Studies have shown that buses are unable to scale effectively beyond a certain number of communicating resources, hence, becoming a bottleneck toward the billion transistor chip [8]. To cope with the inefficiency of buses, VLSI researchers, having explored the areas of parallel computing and computer networks, came up with a novel packet based interconnect architecture for future SoCs Network on a chip (NoC). The idea is to connect different resources on a chip through a network where communication takes place using packets instead of connecting the resources via dedicated wires. NS-2 is an open source, object-oriented and discrete event driven network simulator written in C++ and OTcl.

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Its a very common and widely used tool to simulate small and large area networks. Due to similarities between NoCs and networks, NS-2 has been a choice of many NoC researchers to simulate and observe the behavior of a NoC at a higher abstraction level of design. It has a huge variety of protocols and various topologies can be created with little effort. Moreover, customized protocols for NoCs can easily be incorporated into NS-2. The parameters for routers and links can easily be scaled down to reflect the real situation on a chip. Based on this fact, we have successfully simulated a hundred node 2D mesh based NoC using our reliable protocol for safe delivery of packets. Due to the high integration of circuits in networks on chip, increasing the number of dimensions is very important. In this paper simulation of some an efficient topologies is described. A higher-level modeling and simulation is required to evaluate various options in a NOC architecture. In this paper, ns-2 was used for carrying out some simulation experiments on the model of NOC-S for this purpose. In recent years, digital integrated circuit (IC) designers have been devoting an increasing amount of effort to optimizing the global interconnect fabric in complex digital chips. Innovation in semiconductor manufacturing techniques has enabled the feature size scaling that we have seen from one technology node to the next. As the dimensions of individual devices have been continually shrinking, their switching speeds have been increasing, thus allowing IC designers to create faster circuits and chips. Similarly, device scaling has made it possible to fit more devices on a single chip without increasing the die area, making system-on-chip (SoC) design and parallel processing systems common. Digital ICs typically incorporate more functionality than ever before. However, during this time the scaling of on-chip wires has introduced a new complexity to digital design. The network-on-chip (NoC) research area has emerged to address the top level on-chip interconnect issue. A NoC, at times used synonymously in this work with the more general term, interconnection network, is considered to be a system of functional units that are equipped with routers to form nodes, which are connected with physical wires. Message passing is performed by the routers over the physical links to allow the concurrent processing of data by the functional units. At present, large application specific integrated circuit (ASIC) chips, SoCs, multi-core processors, and all communication intensive ICs stand to benefit from NoCs. NoC design is very challenging; accurate and fast full system power and performance estimation is complicated problem, and NoC design involves making many difficult decisions which have complex or unintuitive effects on power, performance, and area tradeoffs. The proposed work is a methodology and simulation platform which will allow an NoC architect to explore the vast design space efficiently, and provide him with the information needed to create an optimal on-chip network for a specific application..

2 NOC ARCHITECTURAL EVALUATION

Given the enormous NoC design space, an efficient technique is needed to investigate the many design tradeoffs that exist at the interconnection network and circuit design levels. The major contribution of this work is a methodology by which system architects can effectively evaluate the tradeoffs associated with NoC design, so that they have the necessary information to make design decisions. A good summary of the present status ofNoC design is provided by Agarwal [9]. The authors address NoC topologies, router architecture, routing protocol, switching techniques, flow control, virtual channels, buffering, error correction, transmission lines, network interface, quality of service, arbitration, applications, design methodologies, serial/parallel links, interconnect optimization, and other topics. In the next sections we will address a subset of these areas.

3 NS-2 NETWORK SIMULATOR

NS-2 is an object-oriented, discrete event driven network simulator developed at UC Berkely and written in C++ and OTcl [22]. NS-2 is a very common tool used for simulating local and wide area networks. It implements network protocols such as TCP and UPD; traffic source behavior such as FTP, Telnet, Web, CBR and VBR; router queue management mechanism such as Drop Tail, RED and CBQ; routing algorithms such as Dijkstra, and a lot more. NS-2 also implements multicasting and some of the MAC layer protocols for LAN simulations. The simulator is open source, hence, allowing anyone and everyone to make changes to the existing code, besides adding new protocols and functionalities to it. This makes it very popular among the networking community which can easily evaluate the functionality of their new proposed and novel designs for network research. The simulator is developed in two languages: C++ and OTcl. C++ is used for detailed implementations of protocols like TCP or any customized ones. TCL scripting, on the other hand, is the front-end interpreter for NS-2 used for constructing commands and configuration interfaces. For example, if you want to develop a new routing protocol, you have to write it in C++ and add it into the NS-2 library. In order to check the functionality of this protocol, you use TCL scripting through which you can create the required topology, define parameters for links and nodes, and perform simulations to realize your own protocol in action. Besides above-mentioned functionality of NS-2, a Network AniMator (NAM) is also provided with NS2 in order to visualize and interact with the system at run-time. Finally, graphs can be created from the produced results to evaluate and analyze the performance of the system. Discrete event driven network simulator written in C++ and OTcl. Its a very common and widely used tool to simulate small and large area networks. Due to similarities between NoCs and networks, NS-2 has been a choice of many NoC researchers to simulate and observe the behavior of a NoC at a higher abstraction level of design. It has a huge variety of protocols and various topologies

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can be created with little effort. Moreover, customized protocols for NoCs can easily be incorporated into NS-2. The parameters for routers and links can easily be scaled down to reflect the real situation on a chip. Based on this fact, we have successfully simulated a hundred node 2D mesh based NoC using our reliable protocol for safe delivery of packets. As we will see in section 4 that we are not the only ones to use NS-2 for simulating a NoC. The purpose of this paper is to show the network community the similarities that exist between general networks and NoCs and show how NS-2 is facilitating the NoC designers to realize new design paradigms for this novel communication architecture. Furthermore, we hope that this paper would motivate network researchers to make a valuable contribution toward NoCs, hence opening a new dimension of research.

4.2. The 3mr-NOC In the 3mr-NOC (three modular redundancy-Network on chip) topology each resource connects to 2 switces. Figures 2 to 4, show different views of the 3mr-NOC.

4. SIMULATION RESULTS
In this section, simulation results are presented. We have simulated different levels of GFS-Noc(general fat-stack Network-On-Chip) topologies by independent resources which they have recursive structure by using NS-2 simulator. Each of the topologies is simulated in different size. Figures of simulation are shown below.

Fig.2. the first view of 3mr-NOC Topology

4.1. The 2mr-NOC In the 2mr-NOC(2 modular redundancy-Network on chip) topology each resource connects to 2 switces. Figures 1 shows simulation of the 2mr-NOC

Fig.3. the 2nd view of 3mr-NOC Topology

Fig.4. the 2nd view of 3mr-NOC Topology Fig.1. the 2mr-NOC Topology

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4.3. The 4mr-NOC In the 4mr-NOC (quadruple modular redundancy Network on chip) topology each resource connects to 4 switces. Figures 5 to 7, show different views of the 3mr-NOC.

Fig.7. the 3rd view of 4mr-NOC Topology

4.4. The 5mr-NOC In the 5mr-NOC (quintuple modular redundancy Network on chip) topology each resource connects to 5 switces. Figures 8 to 9, show different views of the 5mrNOC.

Fig.5. the first view of 4mr-NOC Topology

Fig.8. the first view of 5mr-NOC Topology

Fig.9. the 2nd view of 5mr-NOC Topology Fig.6. the 2nd view of 4mr-NOC Topology

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4.5. The 6mr-NOC In the 6mr-NOC (sextuple modular redundancy Network on chip) topology each resource connects to 6 switces. Figures 10 to 12,show different views of the 6mr-NOC.

REFERENCES
[1] M. Sgroi, et al, "Addressing the System-on-a-Chip Interconnect Woes Through Communication-based Design", 38th Design Automation Conference, June, 2001. [2] Luca Benini, Giovanni De Micheli, "Network on Chips: A new SoC Paradigm", IEEE computer, Jan., 2002. [3] Shashi Kumar, et. al, "A Network on Chip Architecture and Design Methodology", IEEE Computer Society Annual Symposium on VLSI, Pittsburgh,Pennsylvania, USA, April 2002. [4] LBNL Network Simulator, http://wwwnrg.ee.lbl.gov/ns/ [5] The network simulator - ns-2, available at http://www.isi.edu/nsnam/ns/ [6] Rochit Rajsumman, ``System-on-a-chip: Design and Test'', Artech House Publishers, 2000. [7] L. Benini and G. De Michelli, `Networks on Chip: A new paradigm for component-based MPSoC design'', Multiprocessors Systems on Chips, edited by A. Jerrraya and W. Wolf, Morgan Kaufman, 2004, pp. 4980. [8] Ahmed Jerraya, Hannu Tenhunen and Wayne Wolf, ``Multiprocessor System-on-chips'', Magazine, IEEE Computer, July 2005 (Vol. 38, No. 7), pp. 36-40. [9] A. Agarwal, C. Iskander, and R. Shankar, Survey of Network on Chip (NoC) Architectures & Contributions, Journal of Engineering, Computing and Architecture, vol. 3, no. 1, 2009

Fig.10. the 1st view of 6mr-NOC Topology

Fig.11. the 2nd view of 6mr-NOC Topology

Reza Kourdy received his B.Sc. degree in Computer Engineering and his M.Sc. degree in Computer Architecture both from Azad University of Arak, Iran, in 2002 and 2007, respectively. His research interests include Network-On-Chip Architecture and Fault-tolerance.

Fig.12. the 3rd view of 6mr-NOC Topology

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Mohammad Reza Nouri Rad received his B.Sc. Degree in Computer Engineering Software from Azad University of Najafabad, Iran, in 2001, and his M.Sc. Degree in Computer Software from Azad University of Arak, Iran, in 2010. His research interests include NetworkOn-Chip Architecture and Network Security. He is Program Committee of following conferences : WICT 2011 CSNT 2011 CICN 2011 SocProS 2011 CSNT 2012 CICN 2012 BIC-TA 2012