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JOURNAL OF COMPUTING, VOLUME 4, ISSUE 5, MAY 2012, ISSN 2151-9617 https://sites.google.com/site/journalofcomputing WWW.JOURNALOFCOMPUTING.

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Improvement NOC Reliability by NOC-7MR (NOC-septuple-Modular-Redundancy)


Reza Kourdy Department of Computer Engineering Islamic Azad University, Khorramabad Branch, Iran Mohammad Reza Nouri rad Department of Computer Engineering Islamic Azad University, Khorramabad Branch, Iran

AbstractA new chip design paradigm called Network on Chip (NOC) offers a promising architectural choice for future systems on chips. NOC architectures offer a packet switched communication among functional cores on the chip. NOC architectures also apply concepts from computer networks and organize on-chip communication among cores in layers similar to OSI reference model. A fault tolerant network on chip (FT-NoC) system with redundant architecture for reliable applications is proposed. Applying different types of redundancy on chip increases reliability, efficiency and effectiveness of the NoC and, at large, the aircraft control system itself.. Index Terms integrated circuit (IC), Systems-on-chip (SOC), Network on Chip (NOC), fault tolerance, very large scale integration (VLSI) and deep submicron domain (DSM).

1 INTRODUCTION

he International Technology Roadmap for Semiconductors (ITRS) predicts that before the end of this decade single Systems on Chip (SoC) could embed 4 billion transistors using 50nm technology, operating at 10GHz each ( Benini and De Micheli, 2002) . These advancements raise problems in the communication and interconnection infrastructure between the components inside the chip, hence new architectures and scalable design approaches are needed. In order to cope with the growing needs of the interconnected infrastructure the Network on Chip (NoC) concept has been introduced which benefits computer systems by providing higher levels of performance and reliability. Such computers are now a mandatory component in the design of automatic control units for aviation systems. The Network on Chip system is a collection of computational resources connected together through a network inside the chip and communicate using packets. The communication architecture consists of interconnected switches each connected to a resource which can be a processor core, a memory block, or even a custom designed hardware which is generally called Intellectual Property (IP) Block (Ning, et al. 2007). For avionics and aircraft control systems, IP blocks can be sensors, analogue to digital converters (ADC), etc. One of the main advantages of NoC systems is the separation of computation and communication in these systems. The communication units are Network Interfaces (NI) and switches. NI act as the middle layer and transform streams of bits from the computational resources into packets before sending them to a router or switch and vice versa.

2 NOC TOPOLOGY
Network topology defines the placement and interconnection of nodes inside the NoC area and determines the bandwidth and latency of a network (Salminen et al. 2008). The most common topologies are identified as the 2D Mesh and Torus due to their grid-type shapes and regular structure (Hu et al. 2008). These are the most appropriate topologies and formations for a two dimensional layout on a chip when an application specific topology is not considered. These selected topologies are based on the routing hop count, redundancy overhead in number of links in case of link failure, link lengths, energy consumption over the links and switches, and finally area usage over the silicon surface. The Torus topology introduces long wires (link redundancy) among the last nodes to complete the shape of the topology. Employing long wires in very large scale integration (VLSI) and deep submicron domain (DSM) systems increases the capacitance among wires, influences the inductance of links, and results in development of crosstalk over links. The other promising topology formation for FT-NoC is the application specific architecture. Generally speaking, interconnection networks are difficult to design. The vast design space leaves the system architect with many difficult design decisions to make, all of which impact each other. Furthermore, the suitability of a specific NoC design is dependent on what is the highest priority in the power/performance/area tradeoff, all of which depend on the typical traffic pattern over the network. Therefore, a good NoC design is often applica-

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tion specific. While most interconnection networks have the same basic components, there are a number of decisions that must be addressed before the actual hardware can be designed. Most importantly, wemust focus on selecting a topology, routing algorithm, and flow control combination. The network topology dictates the arrangement of the nodes of the NoC, and the links that connect them. Direct network topologies are ones in which each node has a dedicated router. Some examples include the more basic ring, star, and fully-connected networks, and the basic crossbar circuit. More common direct networks are those belonging to the family of 2D and 3D meshes, tori, hypercubes, and cube connected cycles networks. Alternatively, in an indirect network a node is either a router or a processing element. A message passed between processing elements goes through one or more router nodes before arriving at its destination processing element. The (fat) tree networks, butterfly, and clos networks are all common indirect networks. There are many options, but in this work we will focus on 2D and 3D mesh and torus networks, the flattened butterfly, and fully connected networks. A fully connected network is not pictured, but is one in which every node is directly connected to every other node. Each of these topologies can have a concentration of 1, where each processing element has its own dedicated NoC router, or higher than 1, where multiple processing elements are grouped with a single router. We consider the concentration of the network to be the total number of processing elements divided by the number of routers. These topologies represent a good tradeoff of the network metrics in which we are interested. These are the most incrementally expandable networks, and they maintain high bisection widths and have good path diversity with reasonable cost. The flattened butterfly especially has a low network diameter, and since it is based on a clos network, has path diversity unlike traditional butterfly networks [1].

3 USES OF NOCS
There are several ways interconnection networks can improve communication performance in chips. NoCs can be used as a direct replacement for top level interconnect in complex ASICs. Instead of consuming routing resources with dedicated wires for every cross-chip signal, and designing around the issues mentioned earlier, ASICs can be partitioned into a regular array of tiles. Dedicated wires can then be used for local interconnections that fall completely within a tile, and global interconnections that cross tile boundaries are replaced with a centralized interconnection network; this concept is referred to as packet-routed tiles. Through carefully developed wire delay and power consumption models, it may be possible to arrive at an exact tile size for a given technology where the power consumption is minimized; this is the point at which as tile size shrinks the incremental power savings from moving

local dedicated wire communication to the interconnection network no longer outweighs the overhead of the additional router hardware needed [2]. By multiplexing global signals over the shared links of an interconnection network, reasonable power savings are possible. At present, dedicated wires or bus architectures are predominantly used to allow communication between high level modules in SoCs and multi-core processing chips. Though there is no clear cut difference between some hierarchical buses being implemented today and interconnection networks, the growing number of blocks that must communicate on-chip, and the demands on the performance of that communication, are quickly making present common interconnection fabrics obsolete. The microprocessor industrial design view is that the parallel processing trend in processor architectures will likely continue. The industry standard buses today will not be able to provide the degree of connectivity needed by the many-core systems of the future, especially with the bandwidth to memory that will be required [3]. As an indication of this we can consider the state-of-the-art in floating point processor performance, the 65 nm 80 tile NoC processor at Intel that performs over 1.0 TeraFLOPS at 4.27 GHz while consuming 97 W. The 810 2D mesh NoC has one floating point core, with two pipelined floating point multiply-accumulate units, and one router per node. The packet-switched network has a bisection bandwidth of 2 Tb/s. The fully functioning chip utilizes over 100 million transistors in 275 mm2 [4]. Similarly, the increasing complexity of SoC designs will also require NoC based communication to efficiently accommodate the amount of traffic. The bus protocols typically used in SoC designs have restrictive limits on the number of clients that can use it to communicate. Connecting each SoC module to a router to form an NoC node brings uniformity to global interconnect through well controlled electrical parameters, simplifying chip timing. This can save power, while also facilitating the design of higher performance circuits with lower latency and higher bandwidth. Additionally, design becomes very modular, to the point where creating new chips is a matter of swapping in and out the functional units of the nodes. Given standardized interfaces, from one design to the next many of the functional units will be reusable, as would be the interconnection network, drastically cutting down on the time and cost of the redesign and verification of low level blocks [5].

4 FAULT TOLERANCE AND REDUNDANCY


Fault tolerance is a particular technique that enables the building of systems that maintain the expected service despite the presence of errors caused by hardware faults within the system itself. The use of redundancy increases the reliability of the system but also affects its performance and increases the application costs (power usage and area consumption). A balanced trade off among these factors must therefore be considered for maximum performance and high level of fault tolerance.

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4.1 Fault Classification Faults are classified in three major groups: design faults, manufacturing faults, and operational faults (Weaver and Austin, 2001). Operational faults, based on their frequency and probability of occurrence, are divided into permanent, intermittent, and transient (Ali et al. 2007). They may also be caused by different environmental, operational, and technological processes (De Micheli and Benini, 2006) . A major concern in a fault tolerant NoC design is the tolerance and redundancy of the system against permanent and transient faults caused during operation. Transient faults or malfunctions occur regularly and can be tolerated even at the instruction level (Schagaev, 2008). An example is when some area of the chip experiences an internal failure with permanent effect. However, both types of fault cannot be easily correlated to any specific operational, environmental or technological condition. 4.1 Redundancy Classification Redundancy in computer systems can be classified in terms of time, information and structure (Schagaev and Zalewski, 2001). Any of these redundancy types can be applied to system hardware or system software to protect the system against various types of faults and to increase the reliability of the system. Information redundancy can be realized by introducing coding techniques for parity check into the data stream and packets. Implementation of redundant hardware for simultaneous execution of same data on various channels and comparing the outcomes is a frequent type of structural redundancy. 4.1 Fault Tolerance in NoC using Redundancy There are several potential forms of fault tolerance implementations in NoC systems. Segmentation of the communication and computational infrastructure of NoC systems, one of its core concepts, provides inherent solutions to the reliability problems among different components and areas of systems. For information redundancy, information may be prioritized based on the attention needed by the network infrastructure for the safety and integrity of data into three classes: latency critical, data streams and miscellaneous information (Bjerregaard and Mahadevan, 2006). Each group has its own type of coding technique for parity check. Most common faults in the structure of the system are noise concerns, technology delays and fabrication faults in the manufacture of NoC integrated circuits (IC) (De Micheli and Benini, 2006) . The self-calibrating method was a solution to tolerating the gate delay (Worm et al. 2005). For noise concerns, packet encoding and redundant transmission of information has been introduced. Inserting extra links and wires would tolerate the manufacturing faults but would compromise the performance and energy consumption considerations inside a NoC IC.

5 SIMULATION DETAILS
A network simulator is used to evaluate the concept for a typical communications scenario that must support several classes of traffic having a range of QoS requirements.We would use the tool, Network Simulator ns-2 [6],[7] which has been extensively used in the research for design and evaluation of public domain computer network, to evaluate various design options for NOC architecture, including the design of router, communication protocol, Routing algorithms. NS-2 is an open source, object-oriented and discrete event driven network simulator written in C++ and OTcl. It is a very common and widely used tool to simulate small and large area networks [8]. In this study, we have modeled our NoC architecture concepts with the widely used network simulator ns-2 [9]. This tool has been widely applied in research related to the design and evaluation of computer networks and to evaluate various design options for NoC architectures [10], including the design of routers, communication protocols, etc.

6 SIMULATION RESULTS
In this section, we present the Simulation of NOC7MR(NOC-septuple-Modular-Redundancy) and we survey the ability and flexibility of ns2 in NOC-Redundancy simulations. Mapping an application, which is described by a parameterized task graph, on to NoC is a key research problem in NoC design. Mesh topology has been used in a variety of interconnection network applications especially for NoC design. However, the septupleModular-Redundancy network has not been studied yet as the underlying topology for NoCs. Figures 1 to 6 show different views of the 7mr-NOC.

Fig.1. the first view of 7mr-NOC Topology

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Fig.2. the 2nd view of 7mr-NOC Topology

Fig.5. the 5th view of 7mr-NOC Topology

Fig.3. the 3rd view of 7mr-NOC Topology

Fig.6. the 6th view of 7mr-NOC Topology

Fig.4. the 4th view of 7mr-NOC Topology

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REFERENCES
[1] J. Kim, J. Balfour, and W. Dally, Flattened Butterfly Topology for On-Chip Networks,in Proc. 40th Annual IEEE/ACM International Symposium on Microarchitecture MICRO 2007, J. Balfour, Ed., 2007, pp. 172182. [2] S. Heo and K. Asanovic, Replacing global wires with an on-chip network: a power analysis, in Proc. International Symposium on Low Power Electronics and Design ISLPED 05,K. Asanovic, Ed., 2005, pp. 369374. [3] S. Borkar, Thousand Core Chips-A Technology Perspective, in Proc. 44th ACM/IEEE Design Automation Conference DAC 07, 2007, pp. 746749. [4] S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS, IEEE J. Solid-State Circuits, vol. 43, no. 1, pp. 2941, 2008. [5] W. Dally and B. Towles, Route packets, not wires: on-chip interconnection networks, in Proc. Design Automation Conference, B. Towles, Ed., 2001, pp. 684689. [6] LBNL Network Simulator, http://wwwnrg.ee.lbl.gov/ns/ [7] The network simulator - ns-2, available at http://www.isi.edu/nsnam/ns/ [8] M. Ali, M. Welzl, A. Adnan, F. Nadeem , " Using the NS-2 Network Simulator for Evaluating Network on Chips (NoC)". [9] www.isi.edu/nsnam/ns [10] R. Lemaire, F. Clermidy, Y. Durand, D. Lattard, and A. Jerraya, Performance Evaluation of a NoC-Based Design for MC-CDMA Telecommunications Using NS-2, in The 16th IEEE International Workshop on Rapid System Prototyping, Jun. 2005, pp. 2430. Mohammad Reza Nouri Rad received his B.Sc. Degree in Computer Engineering Software from Azad University of Najafabad, Iran, in 2001, and his M.Sc. Degree in Computer Software from Azad University of Arak, Iran, in 2010. His research interests include NetworkOn-Chip Architecture and Network Security. He is Program Committee of following conferences : WICT 2011 CSNT 2011 CICN 2011 SocProS 2011 CSNT 2012 CICN 2012 BIC-TA 2012

Reza Kourdy received his B.Sc. degree in Computer Engineering and his M.Sc. degree in Computer Architecture both from Azad University of Arak, Iran, in 2002 and 2007, respectively. His research interests include Network-On-Chip Architecture and Fault-tolerance.