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Naveen Kumar1, Sandeep Verma2 Rajesh Mehra3

1,2 3

M.E. Student

Associate Professor

Department of Electronics & Communication Engineering, NITTTR, Chandigarh,,

Abstract : This paper presents routing in VLSI chips which is broken into two distinct processes : Global routing & Detailed routing. We have provided a brief review of these routing techniques & their implementation. In VLSI design flow after placement, the routing process determines the precise paths for nets on the chip layout to interconnect the pins on the circuit blocks or pads at the chip boundary. These precise paths of nets must satisfy the design rules provided by chip foundries to ensure that the designs can be correctly manufactured. Routing is to complete all the required connections to achieve 100% routability otherwise, the chip would not function well and may even fail. There are routing problems due to constraints on the number of wires that can pass through the channel.

Keywords : Global, Detailed, Routing, nets, VLSI.

1. INTRODUCTION: Routing is an important step in the design of integrated circuits (ICs). It generates wiring to interconnect pins of the same signal, while obeying the manufacturing design rules. Two approaches are used i.e. Global and Detailed routing. Global routing first partitions the routing region into tiles and decides tile-to-tile paths for all nets while attempting to optimize some given objective function (e.g., total wire length and circuit timing). Then, guided by the paths obtained in global routing, detailed routing assigns actual tracks and vias for nets. Figure 1 illustrates the process of Global routing Detailed routing[1]. Fig. 1(a) contains the information about the exact locations of blocks, pins of blocks, and I/O pads at chip regions. Fig. 1(b) illustrates some globalrouting paths. Fig. 1(c) shows a result of detailed routing, which determines the exact route for each net by searching within the tile-to-tile path.

Fig. 1 Routing problem (a) Given placement result with fixed locations of blocks and pins, (b) Global routing, (c) Detailed routing. [1]

2. GLOBAL ROUTING: The input to the global router is a floorplan that includes the locations of all the fixed and flexible blocks; the placement information for flexible blocks; and the locations of all the logic cells. The goal of global routing is to provide complete instructions to the detailed router on where to route every net. The global routing emphasizes on:
a. b. c.

Minimizing the total interconnect length. Maximizing the probability that the detailed router will complete the routing. Minimizing the critical path delay.

It can be achieved by two approaches namely Sequential and Concurrent routing. I. Sequential Routing

One of the approach for global routing picks up each net in turn and calculates the shortest path using tree algorithms also known as Sequential routing[2]. As this algorithm proceeds, some channels will become more congested since they hold more nets than others. There are two different ways that a global router handles this congestion problem. Using order-independent and order-dependent routing. In the former global router proceeds by routing each net, independent of crowdedness in the channels. Selection of a particular net is made independent of the routing order, the channel assignment will remain same. After assigning all the interconnects to the channels, then global router returns to those channels that are the most crowded and it reassigns some interconnects to the less crowded channels. Alternatively, in the latter approach a global router can consider the number of interconnects already placed in various channels as it proceeds. In this case the global routing is order dependent, However the routing is still sequential, but now the order of processing the nets will affect the results. Iterative improvement may be applied to the solutions found from both orderdependent and order-independent algorithms. For the better approach for these deficiencies, sequential routing often applies a heuristic net ordering and conducts a rip-up and re-route process to refine the solution. There are some popular net-ordering schemes[1] as follows:

(1) Order the nets in the ascending order according to the number of pins within their bounding boxes. (2) Order the nets in the ascending or descending order of their lengths if routability is the most critical issue. Research shows that routing shorter nets first often leads to better routability. (3) Order the nets on the basis of their timing criticality.

1 2 2

1 2




Fig. 2 Routing for different net orderings, (a) One layer routing case with two two-pin nets 1 and 2, (b) Net ordering of 1 followed by 2 and it is inferior solution, (c) A better solution by net ordering 2 followed by 1.

Fig. 2(a) shows a simple one-layer routing case with two two-pin nets 1 and 2. If one choose net ordering as routing 1 followed by 2, net 2 may get blocked by net 1 and requires long wirelength for complete routing (fig. 2(b)). If routing of net 2 is done first followed by net 1, better result with shorter length can be obtained (fig. 2(c)). II. Concurrent routing

The major drawback of the sequential approach is that it suffers from the net ordering problem. In any net ordering scheme, it is more difficult to route the nets that are processed later, because they are subjected to more blockages. In addition, if the sequential routing fails to find a feasible solution, it is not clear whether this is because of no existing feasible solution or because of a poor selection of net order. Moreover, when the sequential routing does find a feasible solution, we do not know whether or not this solution is optimal or how far it is from the optimal solution. One popular concurrent approach is to formulate global routing as a 0-1 integer linear programming (0-1 ILP) algorithm. There are new or improved routers developed for global routing NTHU-Route[6], FGR , MaizeRouter, BoxRouter, Archer, FastRoute, and NTUgr. 3. DETAILED ROUTING Given global-routing paths, Detailed routing determines the exact tracks and vias for nets. Here, we discuss the two most popular types of Detailed routing: Channel routing and Switchbox

routing. In this routing is done based on the plan which the tool has made in Global routing for those wires which were not actual in global route becomes actual wires now in detail route. Here it searches and repair iterations to make it actual and free from DRC violations. 3.1. Channel routing

Channel routing[5] is a special case of the routing problem in which wires are connected within the routing channels. To apply channel routing, a routing region is define which is usually decomposed into routing channels. The inputs to a channel routing problem are two channel boundaries, the upper boundary and the lower boundary, with pin (terminal) numbers on columns of the channel boundaries. The pin number represents its unique net ID; pins of the same number belong to the same net and thus must be interconnected. A channel is a rectangular region with pins on two opposite (usually the longer) sides and no pins on the other(usually the shorter) sides. There are two types of channels Horizontal and vertical. Horizontal channel is a channel with pins on the top and bottom boundaries (Fig. 3). A vertical channel is a channel with pins on the left and right boundaries. These are routed first followed horizontal channels, this is because of the locations of fixed pin connections for the horizontal channel are determined only after the vertical channel has been routed.

Fig. 3 Channel routing for horizontal channel[5]

3.2 Switchbox routing A Switchbox[8] is the intersection of horizontal and vertical channels (fig. 4). Due to the fixed dimensions, switchbox routing shows less flexibility and is more complex than channel routing. As the entry points of the wires are fixed, the problem is one of finding routes inside the switchbox. A switchbox is a rectangular routing region (routing area) which is located between circuit blocks that are to be connected[3]. A horizontal row is called a track and a vertical wire is named column. The number of tracks defines the width of the switchbox. Furthermore, pins are allowed to be located on all side of the switchbox and represent the connection points on circuit blocks.

Fig. 4 Switchbox routing for horizontal and vertical channels[5]

Switchbox routing uses several algorithms such as Parallex approach[4] Packer algorithm, Parallel genetic algorithm, Evolutionary algorithm[8] etc. 4. CONCLUSION We have studied various routing methodologies which have significant role in VLSI chip design. So complete routability and optimality cannot be ensured by single routing method. We came to know that net ordering technique have time constraints and may result in even blockages. Due to increased number of routing layers in modern VLSI design, traditional channel model is not used widely. Instead Over-thecell (OTC) routing is used. 5. REFERENCES
[1] Huang-Yu Chen and Yao-Wen Chang National Taiwan University, Taipei, Taiwan. Global and Detailed routing , <> [2] Michael D. Moffitt, IBM Research Global routing revisited. Computer-Aided Design - Digest of Technical Papers, 2009. ICCAD 2009. IEEE/ACM International Conference , Pages: 805 - 808 [3] SABIH H. GEREZ AND OTTO E. HERRMANN, MEMBERIEEE Switchbox Routing by Stepwise Reshaping, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN, VOL. 8, NO. 12, Pages: 1350-1361 [4] Tae Won Cho and Sam S. Pyo, A PARALLEL APPROACH IN SWITCHBOX ROUTING, IEEE proceedings vol.2., Southeastcon 91, Page 1184 1188. [5] Andrew B. Kahng, Jens Lienig, Igor L. Markov, Jin Hu. VLSI Physical Design: From Graph Partitioning to Timing Closure, Pages: 131-180. [6] Y.-J. Chang, Y.-T. Lee, and T.-C. Wang. NTHU-Route 2.0: a fast and stable global router. In Proceedings of the 2008 International Conference on Computer-Aided Design (ICCAD 2008), pages 338343, 2008. [7]J. A. Roy and I. L. Markov. High-performance routing at the nanometer scale. IEEE Trans. on CAD of Integrated Circuits and Systems, 27(6):10661077, 2008. [8] Nicole Gockel, Rolf Drechsler, and Bernd Becker A Multi-Layer Detailed Routing Approach based on Evolutionary Algorithms, Evolutionary Computation, 1997, Page 557 - 562