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VH1 VHDL Simulation & Verification VH2 VHDL Synthesis

*Note: Students are advised to read through this lab sheet and prepare your VHDL codes before doing experiment. Your performance, teamwork effort, and learning attitude will count towards the marks.

EEN4186: VLSI System Design & Modeling Technique Design Laboratory 1. Introduction
In this lab, there are two sections; lab assignments and project. Students are asked to write the VHDL codes for a few circuits for the lab assignments. Students are then required to do the assigned tasks for their project. Basic procedures on how to design a circuit are given at the end of the lab sheet. However, students are encouraged to use their own creativity in exploring the CAD tools to complete the task(s). This will also sharpen students skills, as engineers are not procedure-followers. An introduction session will be held to get students acquaintance to the Quartus II software.


List of Equipments
Software: Altera Quartus II Hardware: Altera APEX20K200 FPGA development boards


Lab Assignments
The students are advised to come to the lab sessions well prepared with the VHDL source codes of the designs. The lab assignments must be done by individuals (no groups). The assignment titles will be released gradually during the trimester. Some examples of the assignments are as follows: (a) Combinatorial circuits - 2-bit full adder - 4-to-1 multiplexer - 7-segment decoder Sequential circuits - Synchronous decade counter - Asynchronous decade counter - Ascending and descending sorter


After mastering the software with the above assignments, the students will be required to design, simulate and verify the functionalities of a relatively complex digital system using Quartus II. After that they will synthesize the codes and download it on the Altera Apex development board provided.

Design Project
The students will have to CHOOSE ONE of the following topics: (a) Floating-point multiplication unit (b) Floating-point division unit Project Requirements: 1. A team of at most two per project. 2. All floating-point numbers will be based on the IEEE 754 single-precision standard. 3. The project should involve VHDL coding, compilation, and simulation. 4. Students are encouraged to demonstrate good teamwork.


Report Guidelines
After completing the chosen design task, a project report should be submitted by each group. In this report, all the design decisions must be justified. All relevant information must be provided. Organization, conciseness, and completeness are of paramount importance. The following information must be included: (a) Theory of operation (b) The block diagram of the design (c) Functional explanation of the design (d) Source codes (e) Expected results (testbenches) (f) Simulation results (g) Synthesis Technology view and RTL view (h) Conclusions (i) Citation to references is another vital part of the report. All referred materials/articles must be properly cited. The due date for the submission of the report will be announced in MMLS later during this course.