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Efficient Timing Analysis for General Synchronous and Asynchronous Circuits

Yuan-Hua C h , Yih-June Liou, and Jong-LRih Chen

Design Automation Development Depamuent Electronics Research and Service Organization 195 Sec. 4. Chung W i g Rd.. Chutung. Hsinchu,Taiwan 31015. R0.C. Wane: 886-35-917175 Fa: 886-35-953587
ABSTRACT
This paper deals with the timing analysis problem for genNote that, in our algorithm, if two clocks have the same period, then they will be merged to a single group. In dealing with asynchronous designs, logic gates such as D-latches, NAND/NOR latches and transmission gates are not treated as path breaking elements; all paths will pass through these gates. (Loops are checked for their number of multi-fanout points for further loop detection process.) Finally, we would like to point out that in our timing analyzer. the circuit partitioning algorithm is only called once for analyzing a circuit; all the information is saved for future analysis.

eral synchronous and asynchronous circuits. After partitioning the circuit into a set of clock p u p s , we use an eventdriven approach to 6nd paths with delays greater than a given threshold value. F l e paths detated during went Pmpagation are as to the user. In addition to breaking asynchronous loops dynamically, the tool also checks setup/hold time and minimum pulse width violations in a multiple clock environment. Experimental results are shown to demonstrate the efficiency and effectiveness of the proposed algorithms.
1 Introduction . T m n verification is an important performance evaluation iig step in the design of large digital VLSI circuits. While both l m c simulation and timing analysis approaches can be employed, most people prefer performing static timing analysis due to the deficiencies in logic simulation approach for timing vaification[l-4]. Although effective, static timing analysis techniques still find problems in correctly verifying large digital MOS circuits. For instance, by ignoring the circuit functionality, a timing analyzer may trace out a signal path which can never happen (hence the name false path). Moreover, many designs contain asynchronous circuits or may be driven by multiple clocks. These problems complicate the design of general timing analysis environments. In this paper, we first discuss the circuit partitioning techniques in Section 2. An event-driven timing analysis algorithm is then proposed in Section 3. Sections 4 discusses dynamic asynchronous loop breaking. Section 5 describes a method for false path detection. Algorithms to check setuphold tm and minimum pulse width are discussed in Secie t o 6. Section 7 shows some experimental results to demonstrate in the efficiencies of OUT Jgurithms. F d y , Section 8 s u w z e s the presentation. 2. Circuit Partitioning In many applications. digital MOS circuits are driven by multiple clocks. Since manually partitioning a circuit is errorprone and time-consuming, automatic circuit partitioning is often required in analyzing large digital MOS designs. Our partitioning procedure starts by identifying all the start and end points. In our algorithm, primary inputs and the outputs of flipflops are start points; primary outputs and the inputs of flip-flops are end points. After the start-end point pair is identified, a depth-first search step is invoked to trace, from the start point, down to the end point. If a path exists and ends at the clock input of a flipflop. then the path, together with its associated start-end point Pair, is assigned to a group to which the flip-flop belongs. In case no group can be found for a flip-flop, then a new group is formed for the flip-flop and its associated start-end point pair. However, if the traced path ends at the data input of a flip-flop and the flip-flop does not belong to any group. then the path is put into a list to wait for fume groupings.

3. Event-Driven Timing Analysis We use an event-driven approach to solve timing analysis problems. The approach is similar to the one used in logic simulation except that we propagate events as far as possible. The
rationale behind is that if an event occurs at a s t a ~ point and propagates to an end point, then there must exist a path between the start and the end points. Fig. l(a) and Fig. l(b) explain the situation. In Fig. l(b). if one input of the NAND gate is unknown and an event of 0 to 1 OCCUTS at the other input, then there will be an event of 1 to L at the output pin. The L means that it is not a true 0 but a possible path between the input and the output of the NAND gate. Based on this concept, we modify the the evaluation model for all primitive components. Fig. 2(a) and Fig. 2(b) show the new evaluation models for AND and OR gates, respectively. The event-driven process is initiated for every start node. one by one. A logic4 is first scheduled at a start node to initialize the circuit. This initialization process uses the logic simulation models only. After initialization, a logic-1 is scheduled and the new evaluation models are used for path tracing. This logic-0 followed by logic-1 scheduling forms a rising condition of timing analysis. The falling condition can similarly be constructed by scheduling a logic-1 followed by a logic-0. Note that when an event propagates to a multi-fanout point, a new event will be generated and recorded. An event reaching the end point contributes a path. Every event also remembers where it is generated. This information is called event-origin. Eventorigin is used in forward path report and dynamic loop detection as discussed later. For asynchronous logic gates such as D-latches and transmission gates, the input pin is treated as a temporary start point when the clock input is high, and as a temporary end point when the clock input is low. Any path passes these gates with a delay longer than the clock period will not be propagated further. (The clock activation condition is set by the designer.)
4. Reconvergent and False Path Detection

When reconvergence occurs in a start point tracing, a potential false path exists. Fig. 3 is a simple example to show the situation. In the example, let the propagation delays of all the gates be as marked. When A is toggled from 0 to 1 at t = Om, B will be toggled from 1 to L at t = Ins. However, this event will be inhibited when G3 is evaluated due to a 0 in C at t = lnr. The path A-Gl-B-G3-D is therefore a false path. More( C )

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over. since C i changed t 1 a t 5 . 2 ~ .ad D is changed t L s o t . o at t = 3m, path A(i2-CG3-D is a true path. This pmcess is performed automatically because reconvergence handling is one of the basic propcrries of an event-driven algorithm. Note that false path detection at a reconvergent node is only activated when at least one path does not have any unknown branch. Otherwise the= should be no relationship between thosc reconvergent paths. This method only works at reconvergent nodes. Further topologically dependent false paths can be detected by using other techniques [5-81. However, early detection of false paths can reduce the computational times spent in succeeding detection processes.
5. Dynamic Loop Detection Many timing analysis algorithms assume that all loops can be broken before the analysis is started. This is not true in genaal. For cxampk. asynchnow bops such as "/NOR latches can not be broken rtrti#lly. In our algorithm, when an went reaches a multi-fiaout n & thc " m n t origin" infarmation o, is used to trace back to see if it was originated by itself. The maximum number of trace back steps is determinated at the circuit partitioning procedure as described in Section 2. Fig. 4 shows a simple example to explain the trace back process. Assume the maximum trace back step is 2. If an event is propagated to B and then through G2 t the multi-fanout node D, o the trace back of 2 steps will not find any loop. However, D will generate two new events for its two fanouts with the event-origin at itself. An event then propagates through G1 to C. At C, the two steps trace back still can not find any loop. C then generates two new events with event-origin at itself. One event then propagates through G2 to D. The mestep trace back will find that this event is originated by itself and the loop B-G2-D-Gl-C-G2D is detected. Note that the loop is not broken at the feedback point G2 but broken at the succeeding multi-fanout point. This saturation only makes the feedback path worse but will not affect any other paths.
6. SetuphIold Time and Minimum Pulse Width Check In a multiple-clock design environment. for flip-flops mggered by clocks with different periods, it is very difficult to check the timing violations for the paths between the flip-flops. However, for internally generated clocks which are not specified by the designer, a timing analyzer should be smart enough to generate the corresponding clock waveforms. Fig. 5 shows an example for internal clock generation. If the trigger clock CLKA of flip-flop F1 is shown in Fig. 5, then two new clock signals will be generated at QFI. After these new waveforms propagate to CLKB,there will be several different clocks at CLKB,resulting in several trigger conditions for F2. After internal clocks are generated, and all the clocks are propagated to the clock inputs of flip-flops, a longest (shortest) data path is used to check the setup (hold) time violations. If two flip-flops at the start and end points of critical paths are driven by two clocks with the same clock period, the setup time can be expressed as:
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flip-flops (pt aigged U po6itivc-going N t that these oe equations always d u c k two coatiguous edges because, in genaal. two clocks may trigger a flip-flop at different times, and there is no way to know which edge will generate data and which will receive data As for the calculation of minimum pulse widths, the problem can be simplified since the non-triggering edge of the clock must occur later than at least a specified minimum pulse width after the occurrence of the triggering edge. Al the triggering and non-triggering edges of a clock can be l obtained from tracing the clock paths.
7. Experimental Results We have implemented the proposed algorithms in an interactive timing analysis environment. Table 1 shows some results for the event-driven algorithm. The CPU time is in SUN 4/330, a 7 MIPS machine. N t that the total number of paths oe does not include the ones inhibited by the algorithm. The effectiveness and efficiency of our algorithm are justified by the fact that the average time to detect a false path is about 0.03 seconds. 8. Conclusion In this paper, an integrated timing analysis environment for digital MOS VLSI circuits is presented. We first propose an algorithm to automatically partition the circuit. An event-driven algorithm is then proposed to detect false paths under reconvergent conditions. Our algorithm is further enhanced by dynamic asynchronous loop detection, setuphold time and minimum pulse width checking capabilities. 9. Acknowledgements This is paper is a partial result of the project No. 32F1100 conducted by the ITRI under sponsorship of the Minister of Economic Affairs, R.O.C.

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References R. B. Hitchcock, "Timing Verification and the Timing Analysis Program," Proceedings of the 19th Design Automation Conference, pp. 594-604, 1982. R. Reddi and C. Chen, "Hierarchical Timing Verification System," Computer Aided Design, Vol. 18, No. 9, November 1986, pp. 467-471. I. K.Ousterhout. "A Switch-Level Timing Verifier for Digital MOS VLSI," IEEE Transaction on Computer-Aided Design, Vol. CAD-4, No. 3, July 1985, pp. 336-349. N. P. Jouppi, "Timing Analysis and Performance Improvement of MOS VLSI Designs," IEEE Transaction on Computer-Aided Design, Vol. CAD-6, No. 4, July 1987, pp. 650-665. J. Benkowski, E. Vanden Meersch, L. Claesen, and H. De Man, "Efficient Algorithms for Solving the False Path Problem in Timing Verification," Proceedings of ICCAD-87, pp. 44-47, 1987. H. C. Du, H. C. Yen, and S. Ghanta, "On the General False Path Problem in Timing Analysis," Proceedings of the 26th Design Automation Conference, pp. 555-560, 1989. P. C. McGeer and R. K. Brayton, "Efficient Algorithms for Computing the Longest Viable Path in a Combinational Network," Proceedings of the 26th Design Automation Conference, pp. 561-567, 1989. S. Perremans, L. Claesen, and H. De Man, "Static Timing Analysis of Dynamically Sensitizable Paths," Proceedings of the 26th Design Automation Conference, pp. 568-573, 1989.

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