go athena # #To allow changing device size, set the gate length as a variable set Lg=0.

065 # #Set up a mesh suitable for a 65nm MOSFET. The MOSFET will be symmetrical #so just model half of the device starting mid channel at 0.0. #Only need to model out to 0.1um so final transistor will be placed in the middl e #of a 0.2um mesh in x direction line x loc=0 spac=0.01 line x loc=0.5*$Lg spac=0.005 line x loc=0.1 spac=0.1 # line y loc=0.00 spac=0.005 line y loc=0.3 spac=0.015 line y loc=0.5 spac=0.02 line y loc=2 spac=1 # # Start off by defining silicon as p type <100> with boron conc=2e15 init orientation=100 c.boron=2e15 #Deposit an oxide on the silicon surface for implanting to prevent channeling deposit oxide thick=0.05 #nwell formation for the body of the pmos transistor. The shallowest implant #will define the threshold voltage so vary to get desired threshold. implant phos dose=2.6E13 energy=420 tilt=5 implant phos dose=3.5E13 energy=50 tilt=5 #Anneal the nwell and electrically activate it diffus temp=1000 time=100 weto2 hcl=3 #Remove all oxide prior to gate oxidation etch oxide all #Grow a thin gate oxide target 2.5nm. Change steps 2,3,4 to adjust thickness # method fermi compress diffuse temp=700 time=34 f.o2=0.5 f.n2=10 t.final=800 pres=1 diffuse temp=800 time=2 f.o2=20 pres=1 diffuse temp=800 time=3 f.o2=10 f.hcl=0.1 pres=1 diffuse temp=800 time=2 f.o2=10 pres=1 diffuse temp=800 time=10 inert diffuse temp=800 time=20 inert t.final=700 #Display actual gate thickness acheived extract name="Thin Gate Tox" thickness oxide mat.occno=1 x.val=0 #Deposit 200nm Gate Poly. deposit poly thick=0.2 division=20 #Dope the poly P-Type implant boron dose=5.0e15 energy=15 tilt=5 #Etch the poly gate etch poly right p1.x= 0.5*$lg #Deposit Spacer TEOS and etch to form the oxide spacer deposit oxide thick=0.02 division=8 etch oxide thick=0.02 struct outf=exspacer.str

#P+ Source Drain Implant (PSD). This is a very shallow implant for 65nm #which is why we had to dope the poly earlier. implant boron dose=1.0e15 energy=4 tilt=0 #Anneal PSD using spike (very fast) RTA diffusion temp=1000 time=2 seconds f.o2=0.3 f.n2=2.7 struct outfile=expsdrta.str #Now need to form silicide on the Source Drain and Gate regions. #130nm and below uses sputtered Cobalt to form CoSi. #First remove all oxide from surfaces where CoSi is to be formed. etch oxide thick=0.014 #Sputter 40nm Cobalt deposit cobalt thick=0.04 div=8 #Use RTA to react Cobalt with Silicon to form CoSi diffusion temp=550 time=10 second inert #Strip away any unreacted cobalt from non silicon surfaces #e.g. the spacer oxide. etch cobalt all struct outfile=exsal.str #mirror the structure to form the complete transistor structure mirror left struct outfile=final.str #Define the electrodes electrode name=drain x=-0.08 electrode name=source x= 0.08 electrode name=gate x= 0 electrode name=substrate backside #----------------------------------------------------------------------------go devedit base.mesh height=1000000 width=1000000 bound.cond !apply max.slope=28 max.ratio=300 rnd.unit=0.001 line.straightening=1 align.points when=automatic imp.refine imp="NetDoping" sensitivity=1 imp.refine min.spacing=0.01 constr.mesh max.angle=90 max.ratio=300 max.height=1 max.width=1 min.height=0.000 1 min.width=0.0001 Mesh Mode=MeshBuild refine mode=both x1=-0.5*$Lg y1=0 x2=0.5*$Lg y2=0.2 ############# PVt Test : Returns PVt, PBeta and PTheta ################ go atlas # set material models models cvt srh print contact name=gate p.poly interface qf=3e10 # get initial solution solve init

method newton trap solve prev

# Bias the drain a bit... solve vdrain=-0.1 name=drain # Ramp the gate log outf=mos1ex08_1.log master solve vgate=0 vstep=-0.05 vfinal=-1.5 vdrain=-0.1 name=gate save outf=mos1ex08_1.str quit