HARDWARE IMPLEMENTATION OF ENCRYPTION AND DECRYPTION TECHNIQUES FOR SECURED COMMUNICATION SYSTEM A PROJECT SYNOPSIS

Submitted in the Fulfillment of the Requirement of Major Project in degree of

BACHELOR OF TECHNOLOGY
(Electronics and Communication)

Under the guidance of Mr. Abhishek Srivastava Senior Lecturer Jaypee Institute of Information Technology Submitted by Ayush Singhal Enrolment no. 08102266 Pranjal Srivastava Enrolment no. 08102279

1. Project Summary Last year was spent entirely in learning the Verilog Hardware Description Language for the efficient Digital Hardware Implementation of encryption algorithms. The encryption algorithms designed and synthesized last time around were Blowfish Data Encryption Algorithm (64-bit) and Advanced Encryption Standard (AES-128bit). The Verilog design of both the algorithms gave exactly the required simulation output; however, the hardware synthesis result for AES-128 (Xilinx Virtex-4) was not up to the mark as it occupied a very large area, specifically the Number of Slices (510 %). The code underwent many modifications last semester. The modifications produced significant improvements in the synthesis result. This semester our aim is to implement and test the design of AES-128 on an FPGA, preferably Xilinx Virtex-4 (because the software synthesis has been performed on the very same platform). The data blocks on which the encryption and decryption processes will be performed are as long as 128 bits. Hence, our initial aim is to get familiar with the working of an FPGA, as to how to feed the inputs, how to extract the outputs and other nuances. For this purpose, a combinational design of a 4-bit ALU has been created till now that works on a 2-bit input control variable, 2x 4bit inputs and 2x 4-bit outputs. The ALU performs the different mathematical operation depending on the value of the 2-bit control variable as follows: 00- Add the two 4-bit numbers, 01- Subtract the two 4-bit numbers, 02- Multiply the two 4-bit numbers, 03- Right Shift a 4-bit number by 1 bit All these modules were created without using any predefined mathematical operators already used in Verilog. This code can also be used if in case RTL logic for a particular algorithm or problem is to be designed. Apart from this, the sub-shift module of the AES-128 design has undergone a radical change and has resulted in a noticeable reduction in area. Apart from this, the mix-columns module has undergone a few minor changes that has resulted in a lesser output processing time and a minor improvement in area. 2. Project Plan Till now (Jan, Feb), a 4-bit ALU code has been created for the purpose of getting familiar with working on an FPGA before actually implementing the AES design which is the crux of our project this semester. The AES design as well has undergone a few changes. From here on, March: Implementing the 4-bit ALU on the FPGA available at JIIT and getting more and more familiar with it by exploring all the different options.

April: Realizing an efficient floor plan on the FPGA for the AES-128 design (sequential). Implementing this design on the available FPGA. May: (Conditional) Implementing this design on an IC or any other form of non-reconfigurable hardware. 3. Progress Report Supervisors Remarks Supervisors Signature

S. Period No. (Event) Till MidSem 1

Work Presentation (T1)

Work(s) Done a 4-bit ALU code has been created for the purpose of getting familiar with working on an FPGA before actually implementing the AES design which is the crux of our project this semester. The AES design as well has undergone a few changes.

Examiners Dr. Vikram Karwal, Mr. Jawaid Alam

4. References [1]. Clifford E. Cummings, Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill! , Sunburst Design Inc., San Jose, 2000. [2]. Electrical Engineering Technical Interview Questions/Review,file://///chronias/doredlh/Desktop/Electrical%20Engineering%20Inter view%20Questions-Review.htm (1 of 20)7/18/2006 5:26:04 PM. [3]. J. Bhasker, Verilog HDL Synthesis- A Practical Primer, Star Galaxy Publishing. [4]. Stephen Brown, Zvonko Vranesic, Fundamentals of Digital Logic with Verilog Design, Tata McGraw Hill, 2002. [5]. A Combinational Multiplier Using the Xilinx Spartan II FPGA, author unknown.