9. Define Macro. Write a C program with a macro to find out biggest of two numbers.

A macro is a fragment of code which has been given a name. Whenever the name is used, it is replaced by the contents of the macro. There are two kinds of macros. They differ mostly in what they look like when they are used. Object-like macros resemble data objects when used, function-like macros resemble function calls.
You may define any valid identifier as a macro, even if it is a C keyword. The preprocessor does not know anything about keywords. #include<stdio.h> #include<conio.h> #define Greatest(X,Y) X>Y?X:Y int main() { int x,y; scanf("%d %d",&x,&y); printf("%d",Greatest(x,y)); getch(); }

8. List out the pass-1 data structures and pass-2 data structures. Two Pass Assembler Pass 1 (define symbols) - Assign addresses to all statements - Save addresses assigned to all labels - Process assembler directives (e.g., WORD, RESB, ... Pass 2 (assemble instructions & write output files) - Translate operation codes - Assemble operands - Generate data values for BYTE & WORD directives - Process START and END directives - Write to object and listing files Data Structures 1) OPTAB (operation code table) mnemonic, machine code (instruction format, length) etc. static table instruction length array or hash table, easy for search Contents - Mnemonic Codes of all instructions - Machine language op code

- Other Information (for architectures with more that one length of instruction format) o Length of instruction o Instruction formats In pass 1 - Validate op codes - Compute instruction length (in SIC/XE) In pass 2 - Translate op codes to machine language Organized as hash table - Static (no updates)

2) SYMTAB (symbol table) label name, value, flag, (type, length) etc. dynamic table (insert, delete, search) hash table, non-random keys, hashing function Contents - Name of symbol - Address (value) - Error flags (from pass1) - Other information: attributes of data or instruction labeled In pass 1 - Enter labels as they are encountered in source program - Enter addresses from LOCCTR In pass 2 - Look up operand labels for addresses Also organized as a hash table - Entries only (no deletions) - Non-random keys -- watch hashing function 3) Location Counter (LOCCTR) counted in bytes. Initialized to address specified in START directive. Length of each assembled instruction is added to LOCCTR. LOCCTR points to starting address of each statement in the program.

Intermediate Data . Between Passes 1 and 2 . For each statement in source program - Address - Error flags - Pointers to OPTAB and SYMTAB - Other (more complicated languages): results of processing of operation and operand fields

TWO PASS ASSEMBLER

7. Discuss Addressing Modes of Intel 80X86 with suitable examples ADDRESSING MODES OF 8086 Addressing mode indicates a way of locating data or operands. Depending upon the data types used in the instruction and the memory addressing modes, any instruction may belong to one or more addressing modes, or some instruction may not belong to any of the addressing modes. Thus the addressing modes describe the types of operands and the way they are accessed for executing an instruction. Here, we will present the addressing modes of the instructions depending upon their types. According to the flow of instruction execution, the instructions may be categorized as (i) Sequential control flow instructions and (ii) Control transfer instructions. Sequential control flow instructions are the instructions, which after execution, transfer control to the next instruction appearing immediately after it (in the sequence) in the program. For example, the arithmetic, logical, data transfer and processor control instructions are sequential control flow instructions. The control transfer instructions, on the other hand, transfer control to some predefined address somehow specified in the instruction after their execution. For example, INT, CALL, RET and JUMP instructions fall under this category. The addressing modes for sequential control transfer instructions are explained as follows: 1. Immediate: In this type of addressing, immediate data is a part of instruction, and appears in the form of successive byte or bytes. Example: MOV AX, 0005H

In the above example, 0005H is the immediate data. The immediate data may be 8-bit or 16-bit in size. 2. Direct: In the direct addressing mode, a 16-bit memory address (offset) is directly specified in the instruction as a part of it. Example: MOV AX, [5000H] Here, data resides in a memory location in the data segment, whose effective address may be computed using 5000H as the offset address and content of DS as segment address. The effective address, here, is 10H*DS+5000H. 3. Register: In register addressing mode, the data is stored in a register and it is referred using the particular register. All the registers, except IP, may be used in this mode. Example: MOV BX, AX. 4. Register Indirect: Sometimes, the address of the memory location, which contains data or operand, is determined in an indirect way, using the offset registers. This mode of addressing is known as register indirect mode. In this addressing mode, the offset address of data is in either BX or SI or DI registers. The default segment is either DS or ES. The data is supposed to be available at the address pointed to by the content of any of the above registers in the default data segment. Example: MOV AX, [BX] Here, data is present in a memory location in DS whose offset address is in BX. The effective address of the data is given as 10H*DS+ [BX]. 5. Indexed: In this addressing mode, offset of the operand is stored in one of the index registers. DS and ES are the default segments for index registers SI and DI respectively. This mode is a special case of the above discussed register indirect addressing mode. Example: MOV AX, [SI] Here, data is available at an offset address stored in SI in DS. The effective address, in this case, is computed as 10H*DS+ [SI]. 6. Register Relative: In this addressing mode, the data is available at an effective address formed by adding an 8-bit or 16-bit displacement with the content of any one of the registers BX, BP, SI and DI in the default (either DS or ES) segment. The example given before explains this mode. Example: MOV Ax, 50H [BX] Here, effective address is given as 10H*DS+50H+ [BX].

7. Based Indexed: The effective address of data is formed, in this addressing mode, by adding content of a base register (any one of BX or BP) to the content of an index register (any one of SI or DI). The default segment register may be ES or DS. Example: MOV AX, [BX] [SI] Here, BX is the base register and SI is the index register. The effective address is computed as 10H*DS+ [BX] + [SI]. 8. Relative Based Indexed: The effective address is formed by adding an 8-bit or 16-bit displacement with the sum of contents of any one of the bases registers (BX or BP) and any one of the index registers, in a default segment. Example: MOV AX, 50H [BX] [SI] Here, 50H is an immediate displacement, BX is a base register and SI is an index register. The effective address of data is computed as 160H*DS+ [BX] + [SI] + 50H. For the control transfer instructions, the addressing modes depend upon whether the destination location is within the same segment or a different one. It also depends upon the method of passing the destination address to the processor. Basically, there are two addressing modes for the control transfer instructions, viz. intersegment and intra-segment addressing modes. If the location to which the control is to be transferred lies in a different segment other than the current one, the mode is called inter-segment mode. If the destination location lies in the same segment, the mode is called intra-segment. Inter-segment Direct Inter-segment Inter-segment Indirect Modes for control Transfer instructions Intra-segment Intra-segment Direct Intra-segment Indirect

Addressing Modes for Control Transfer Instruction 9. Intra-segment direct mode: In this mode, the address to which the control is to be transferred lies in the same segment in which the control transfer instruction lies and appears directly in the instruction as an immediate displacement value. In this addressing mode, the displacement is computed relative to the content of the instruction pointer IP. The effective address to which the control will be transferred is given by the sum of 8 or 16 bit displacement and current content of IP. In case of jump instruction, if the signed displacement (d) is of 8 bits (i.e. 128<d<+128), we term it as short jump and if it is of 16 bits (i.e. 32768<+32768), it is termed as long jump. 10. Intra-segment Indirect Mode: In this mode, the displacement to which the control is to be transferred, is in the same segment in which the control transfer instruction lies, but it is passed to the instruction indirectly. Here, the branch address is found as the content of a register or a memory location. This addressing mode may be used in unconditional branch instructions. 11. Inter-segment Direct Mode: In this mode, the address to which the control is to be transferred is in a different segment. This addressing mode provides a means of branching from one code segment to another code segment. Here, the CS and IP of the destination address are specified directly in the instruction. 12. Inter-segment Indirect Mode: In this mode, the address to which the control is to be transferred lies in a different segment and it is passed to the instruction indirectly, i.e. contents of a memory block containing four bytes, i.e. IP (LSB), IP (MSB), CS (LSB) and CS (MSB) sequentially. The starting address of the memory block may be referred using any of the addressing modes, except immediate mode. 8086 INSTRUCTION FORMAT The 8086 instruction sizes vary from one to six bytes.
6. Compare RISC Architecture with CISC Architecture? What was the necessity to move to RISC architecture?
The simplest way to examine the advantages and disadvantages of RISC architecture is by contrasting it with it's predecessor: CISC (Complex Instruction Set Computers) architecture.

Multiplying Two Numbers in Memory On the right is a diagram representing the storage scheme for a generic computer. The main memory is divided into locations numbered from (row) 1: (column) 1 to (row) 6: (column) 4. The execution unit is responsible for carrying out all computations. However, the execution unit can only operate on data that has been loaded into one of the six registers (A, B, C, D, E, or F). Let's say we want to find the product of two numbers one stored in location 2:3 and another stored in location 5:2 - and then store the product back in the location 2:3. The CISC Approach The primary goal of CISC architecture is to complete a task in as few lines of assembly as possible. This is achieved by building processor hardware that is capable of understanding and executing a series of operations. For this particular task, a CISC processor would come prepared with a specific instruction (we'll call it "MULT"). When executed, this instruction loads the two values into separate registers, multiplies the operands in the execution unit, and then stores the product in the appropriate register. Thus, the entire task of multiplying two numbers can be completed with one instruction: MULT 2:3, 5:2 MULT is what is known as a "complex instruction." It operates directly on the computer's memory banks and does not require the programmer to explicitly call any loading or storing functions. It closely resembles a command in a higher level language. For instance, if we let "a" represent the value of 2:3 and "b" represent the value of 5:2, then this command is identical to the C statement "a = a * b." One of the primary advantages of this system is that the compiler has to do very little work to translate a high-level language statement into assembly. Because the length of the code is relatively short, very little RAM is required to store instructions. The emphasis is put on building complex instructions directly into the hardware. The RISC Approach RISC processors only use simple instructions that can be executed within one clock cycle. Thus, the "MULT" command described above could be divided into three separate commands: "LOAD," which moves data from the memory bank to a register, "PROD," which finds the product of two operands located within the registers, and "STORE," which moves data from a register to the memory banks. In order to perform the exact series of steps described in the CISC approach, a programmer would need to code four lines of assembly: LOAD A, 2:3 LOAD B, 5:2

PROD A, B STORE 2:3, A At first, this may seem like a much less efficient way of completing the operation. Because there are more lines of code, more RAM is needed to store the assembly level instructions. The compiler must also perform more work to convert a high-level language statement into code of this form. However, the RISC strategy also brings some very important Emphasis on hardware Emphasis on software advantages. Because each Includes multi-clock Single-clock, instruction requires only one clock complex instructions reduced instruction only cycle to execute, the entire Memory-to-memory: Register to register: program will execute in "LOAD" and "STORE" "LOAD" and "STORE" approximately the same amount of incorporated in instructions are independent instructions time as the multi-cycle "MULT" command. These RISC "reduced Small code sizes, Low cycles per second, instructions" require less high cycles per second large code sizes transistors of hardware space than Transistors used for storing Spends more transistors the complex instructions, leaving complex instructions on memory registers more room for general purpose registers. Because all of the instructions execute in a uniform amount of time (i.e. one clock), pipelining is possible. CISC RISC Separating the "LOAD" and "STORE" instructions actually reduces the amount of work that the computer must perform. After a CISC-style "MULT" command is executed, the processor automatically erases the registers. If one of the operands needs to be used for another computation, the processor must re-load the data from the memory bank into a register. In RISC, the operand will remain in the register until another value is loaded in its place

5. How many characters can be represented by ASCII-8 data format? What is the limitation of ASCII-7 format? The code called ASCII (pronounced "AS-key"), which stands for American Standard Code for Information Interchange, uses 7 bits for each character. Since there are exactly 128 unique combinations of 7 bits, this 7-bit code can represent only characters. A more common version is ASCII-8, also called extended ASCII, which uses 8 bits per character and can represent 256 different characters. For example, the letter A is represented by 01000001. The ASCII representation has been adopted as a standard by the U.S. government and is found in a variety of computers, particularly minicomputers and microcomputers. The following table shows part of the ASCII-8 code. Note that the byte: 01000011 does represent the character 'C'. Ascii7 is a Unicode-to-ASCII conversion module for programmers. It converts any Unicode string to 7-bit ASCII preserving information. Available as a source code module, Ascii7 is an easy way to support good Unicode-to-ASCII conversion in your own applications.

Key features. Convert Unicode strings to 7-bit US-ASCII. Drop diacritics. Remove accents and umlauts. Replace special symbols with pure ASCII. Convert Cyrillic and Greek letters to their Latin equivalents. Get rid of gargabe conversion. Available as source code for: Visual Basic 6.0 Visual Basic .Net Visual Basic for Applications Other languages can be arranged on demand. Please inquire. The problem. Today's applications support a large range of Unicode characters. However, compatibility often requires the use of 7-bit ASCII. Character values must be forced to the 0127 range. What's the best way to convert Unicode text to ASCII? Programming environments, such as Visual Basic and the .Net framework, have lacking support for proper conversion. Even where available, conversion loses some non-ASCII characters and converts them to question marks (?). The result is loss of information and garbage text. The solution. This is where Ascii7 comes to help. Ascii7 converts Unicode text to its ASCII representation. Instead of turning non-ASCII characters to garbage, it provides a meaningful conversion. It does this by dropping diacritics from Latin letters and finding the closest ASCII equivalent for a wide range of characters.Where an exact match is not possible, a reasonable equivalent is used. The text stays as intelligible as possible for a human reader. Suggested uses. Enforce ASCII filenames for generated files. Produce standards-compliant file formats. Common formats requiring 7-bit ASCII: GIF file comment field, MHT file header lines and email headers. With Ascii7 you convert national characters to an international format that is guaranteed to work everywhere. 4. Classify and define Grammars. Which Grammar is best suitable for Programming Languages and why? Grammars The theory behind the traditional description of the syntax of programming languages is Chomskys hierarchy of formal grammars[8]. Chomsky described generative grammars for describing human languages such as English, where the concept is recursive rules that produce sequences of lexemes (words and punctuation in the context of human languages, and identifiers, keywords and symbols in the context of programming languages). Generative grammars are suitable for human languages where the focus is on building phrases and there is natural ambiguity, but less suitable for programming languages where the focus is on breaking phrases down, or parsing them, and ambiguity is a problem that has to be worked around. Regular Grammars Regular grammars are the most restrictive of the hierarchy, recognised by a finite state automaton. Regular grammars are applied in lexical analysis, described below, and the regular expressions (RE) often used to express search patterns for text strings.

Context-Free Grammars The productions of Context-free grammars (CFGs) cannot refer to any text around the production, or rule, for context. CFGs are recognised by a pushdown automaton, an FSA with a stack data structure that allows it to store a state to return to later. This allows recursive rules. Context-Sensitive Grammars The productions in Context-sensitive grammars may apply depending on the surrounding text (the context of the production) and are recognised by linear bounded automatons, which are Turing machines where memory consumption is linear to the size of the input. Unrestricted Grammars Unrestricted grammars include all formal grammars and there are no restrictions on the type of productions in the grammar. Any Turing machine can parse text according to an unrestricted grammar but the complexity and use of resources by the parser are also unrestricted. Most programming languages are defined using CFGs expressed in BackusNaur form with informally defined extensions in the form of code actions to support the context-sensitive parts of the language. The syntax of languages including C and Eiffel is context-sensitive and are implemented using this method. Opposed to the generative grammars of the Chomsky hierarchy are the recognitionbased, or analytic grammars which conceptually focus on parsing texts according to a language instead of constructing them. Ford[11] gives a formal example of the difference between generative and recognition-based grammars for a language consisting of any number of pairs of the character a: A generative grammar {s a | s = (aa)n} constructs a string as any number of concatenated as. A recognition-based grammar {s a | (|s| mod 2 = 0)} accepts a string of as if the length is even. A top-down parsing language[6] (TDPL) is a recognition-based grammar that describes how to parse constructs instead of how to generate them. As will be shown, the Katahdin grammar is a form of parsing expression grammar and can ultimately be reduced to a TDPL.