SIEMENS

FUNDAMENTOS DE LOS SISTEMAS DE PROTECCION NUMERICOS Proteccin Diferencial de Barras Distribuida

Copyright Siemens Austral Andina 2009. All rights reserved.

Versions 7SS50 7SS51 Centralised version Summation transformer Centralised version Phase segregated

S IP R O T E C

7SS52

Distributed version Phase segregated

B U S B A R P R O T E CT I O N

7S S5 2 11 - 5C A 0 0

1
SIPRO E TC

2
SIPR TEC O

3
SIPRO TEC

48
SIPRO TEC

B U S BA R P R O T E C T O N I

7S S 52 11- 5 CA 0 0

B US B A R P R O T E C TI O N

7 S5 21 1-5 C A00 S

B U S B A R P R O TE C TIO N

7 SS 52 1 1-5 C A 0 0

B U S B A R P R O TE C TIO N

7S S 52 1 1-5 CA 00

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Copyright Siemens Austral Andina 2009. All rights reserved. ED SE PTI

q Further development of the centralised busbar and breaker failure protection 7SS50/51 q Employing the prooven low impedance principle which is already used by Siemens in conventional, analogue and numerical protection schemes q Firmware based on experienced software 7SS50/51 ( about 200 systems worldwide in service ) q Tripping time 15ms ( heavy duty tripping contact ) q Current transformer saturation after 3ms tolerable q Integrated two-stage circuit-breaker failure protection

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Copyright Siemens Austral Andina 2009. All rights reserved. ED SE PTI

q Phase segregated measurement for each bus section q Additional, isolator independant 'checkzone' q Transfer bus treated as separate bus section q Fault detection within the 'dead zone' between CB and CT of buscouplers q Bay specific O/C-interlocking of trip command q Bay-out-of-service function for maintenance

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Copyright Siemens Austral Andina 2009. All rights reserved. ED SE PTI

Substation configurations
q Single, double or triple busbar with transfer bus q 48 bays q 12 busbar sections q 4 couplers, 24 sectionalisers

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Copyright Siemens Austral Andina 2009. All rights reserved. ED SE PTI

S IP R O T E C

central unit central

unit

B U S B A R

P R O T E C T IO N

7 S S 5 2 1 1 -5 C A 0 0

1
S IPR OTEC

2
S IPR OTEC

3
SIPR OTE C

48
S IPR OTEC

bayunits bay units

B USB AR PROT EC TIO N 7SS5211-5CA00 BU S B A R PROT EC TION 7SS 5211-5CA00 BUSB AR PROTECTION 7S S5211 -5CA 00 BU S BA R PROT ECTION 7S S5211-5 CA00

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Copyright Siemens Austral Andina 2009. All rights reserved. ED SE PTI

IL1 I L2 18 LEDs LC-Display membrane keyboard OF TTL RS232 operating/diagnosis (RS232, 19,2kBd) TTL OF TTL

IL3 I 0

central unit (OF, 1,2 MBit/s)

Q1 ON Q1 OFF Q2 ON Q2 OFF Q3 ON Q3 OFF Q4/7 ON Q4/7 OFF Q9 ON Q9 OFF BF L1 BF L2 BF L3 BF trig. puls/ CB test BF release trip release CB OFF CB ON CB in service

TRIP L1/1 TRIP L1/2 TRIP L2/1 TRIP L2/2 TRIP L3/1 TRIP L3/2

bay unit

TRIP /1 TRIP /2

intertrip

device failure bay out of service V+ V= =

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Copyright Siemens Austral Andina 2009. All rights reserved. ED SE PTI

Features of the bay unit

q Sampling, processing, testing and display of measured values q Special handling of measured values for use in couplers q Isolator position monitoring and indication q Data acquisition for breaker failure protection q Serial port for communication with the central unit q Cyclic testing, self monitoring

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Copyright Siemens Austral Andina 2009. All rights reserved. ED SE PTI

bay unit 1 (OF, 1,2 MBit/s)

TTL OF 34 LEDs LC-Display

annunciation 1

bay unit 48 (OF, 1,2 MBit/s)

TTL OF

membrane keyboard

control master unit (OF) OF operating/diagnosis (RS232, 19,2kBd)

TTL

TTL RS232

central unit
time synchronisation release differential current supervision release disturbance record buffer freeze disturbance record buffer reset of LEDs annunciation 16 (32)

device failure V+ V=

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Copyright Siemens Austral Andina 2009. All rights reserved. ED SE PTI

Features of the central unit

q Phase- and sectionsegregated measurement q Circuit-breaker failure protection q Communication and synchronisation with bay units q Cyclic checks of the entire system q Administration of configuration data and parameters q Interface to local PC ( DIGSI ) q Fault reporting and status indication q Fault recording
Copyright Siemens Austral Andina 2009. All rights reserved. ED SE PTI

Page 9

Serial link central unit - bay unit

q Synchronous data transmission q Full duplex communication via 2 optical fibres (62,5/125m, 820nm, 1,5km, FSMA) q Protocol in accordance to HDLC with additional monitoring of length of telegram (High Level Data Link Control Procedures for Data Communication) q 1,2 MBaud q Cycle time 1ms (50Hz), 0.83ms (60Hz) q Hamming-distance d = 4

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Copyright Siemens Austral Andina 2009. All rights reserved. ED SE PTI

Circuit-breaker failure protection

q Two-stage for faults outside the busbar l Stage 1: repetition of tripsignal for faulty bay l Stage 2: tripping of every bay connected to the same bus section l Phase segregated unbalancing (reversal of current) l Limit of differential current related to nominal bay current l Bay-specific minimum current release l Bay-specific intertrip l Unbalancing on receive signal from the opposite protection q Busbar faults l Bay-specific intertrip q Bus section specific, O/C-controlled distribution of trip commands in combination with external circuit-breaker failure protection devices Functionality configurable independently for each bay
Copyright Siemens Austral Andina 2009. All rights reserved. ED SE PTI

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central unit
ZPS (BSZ1) DPR ZPS (SBK) DPR ZPS (SK1) 1 2 8 DPR ZPS (SK2) DPR ZPS (SK3) DPR ZPS (SK4) DPR ZPS (SK5) DPR ZPS (SK6) 48 ZPS (BSZ2) DPR ZPS (BSZ3) DPR EAZ1 EAZ2 SV

q Modular system q Few types of components q easy to extend q easy to assemble

bay 1

bay 2

bay 48

bay unit
A/D C

bay unit
A/D C

bay unit
A/D C

ZPS: processing unit SBK: system management

BSZ: protection algorithm SK: Serial link

EAZ: I/O unit SV: power supply

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Copyright Siemens Austral Andina 2009. All rights reserved. ED SE PTI

central unit
Master System control
ZPS (SBK) DPR ZPS (SK1) 1 2 8 DPR ZPS (BSZ1) DPR

Calculatio n checkzone

ZPS (BSZ2) DPR

Calculation even samples

ZPS (BSZ3) DPR

Calculation odd samples

Interface to up to 8 bay units

ZPS (SK6) 48

Abzweig 1

Abzweig 48

Date acquisition of bay informations, indication, tripcommands

bay unit
A/D C

bay unit
A/D C

ZPS: processing unit SBK: system management

BSZ: protection algorithm SK: Serial link

EAZ: I/O unit SV: power supply

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Copyright Siemens Austral Andina 2009. All rights reserved. ED SE PTI

Security against malfunction: 3-out-of-3 decision per bay

Short circuit in disciminative zone x, calculated from even samples
ZPS (BSZ 2) DPR

Short circuit in the check zone, calculated from all samples

ZPS (BSZ 1) DPR

Short circuit in disciminative zone x, calculated from odd samples

ZPS (BSZ 3) DPR

Trip- relay (per bay)

LL+

3 pole tripping control per bay

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Copyright Siemens Austral Andina 2009. All rights reserved. ED SE PTI