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1. VGA (HD-15) Monitor Port 2. 9-pin (DB-9) 3. Power Connector 4. A1 Expansion Port 5. A2 Expansion Port 6. B1 Expansion Port 7. PS/2 Port 8. Seven Segment Displays 9. Switches (8) 10. Buttons (4) 11. LEDs (8) 12. Power LED 13. Spartan 3 FPGA Core 14. Program LED (Lit when the FPGA is programmed) 15. JTAG Port (used to program the FPGA)
Select a project location and type the name you would like to call your project HalfAdder:
Click Next Select the device family, device, package, and speed grade as shown below:
Click Next
Click Next
Specify the inputs and outputs of your design (HalfAdder). This is used to generate a template for your VHDL code.
Click Next
Click Finish if you are satisfied your specifications shown in the summary page
Click Next
Click Next
Click Finish.
Include an enable input in your entity and it should be 1 bit wide. Complete the architectural part of your VHDL code.
Specify the pins you would like the inputs and outputs to be connected to. Double-click on Assign Package Pins in the Process pane in the left of the window.
Note: You may be asked to save your VHDL code. Your design will be checked for syntax error. If you have any error, make sure you fix them before proceeding.
Click Yes.
You can select Package View tab at the bottom of the right pane. The package view gives a better view of the physical FPGA package).
Type in the desired pin names for each signal in the Design Object List at the left in the Loc column
Click File and Save. Click File and Exit. Note: The following dialog may appear when saving the file:
View the UCF file by double-clicking Edit Constraints (Text) in the project Navigator window.
In the Process Properties windows, Select Startup Options tab. Change FPGA Start-UP Clock to JTAG Clock
Click Apply. Click Ok. In the Processes window, click on the + sign by Generate programming file. Double-click on Configure Device (iMPACT). This opens the iMPACT tool and a wizard for creating a new configuration.
Click Finish.
Assign New Configuration File window opens. Select the name of your select the .bit file (HalfAdder.bit).
Click Open.
click Bypass.
Click Apply. Click Ok. The FPGA is now being programmed as shown: