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Physical Design

LAYOUT GENERATIONS

What is a technology ?
Technology is a set of rules which the designer follows for laying out a design

This gives all the set of rules which we should Follow in order to get desired functionality

This specifies the distance that is to be maintained Between two layers or two components in a chip

Design rules provides a methods for designing a circuit in silicon Design rules are the communication link between the designer specifying the requirements and the fabricator An abstraction between the traditional transistor schematic and the layout (Stick diagrams) helps in organizing the layout design Stick diagrams can be drawn much faster than layout

Stick Diagrams
VDD VDD

X
X

Stick Diagram

X Gnd

Gnd

Stick Diagrams
Stick diagrams are a means of capturing topography and layer information using simple diagrams.

Stick diagrams convey layer information through color codes (or monochrome encoding).
Acts as an interface between symbolic circuit and the actual layout. Mask layouts (Compatible with the fabrication processes) can be easily obtained from Stick diagrams Shows all components/vias.

Provides easy approach to performing simple CMOS circuit layouts Helps in planning physical design before using the actual CAD tool

Complicated wiring of gates and cells is often easier to visualize using stick diagrams
Helps in visualizing the signal flow in complex networks

Stick diagrams Shows relative placement of components. Goes one step closer to the layout Helps plan the layout and routing A stick diagram is a cartoon of a layout. Stick diagrams does not shows Exact placement of components Transistor sizes Wire lengths, wire widths, tub boundaries.

VDD X

VDD

x
X X

Gnd

Gnd

Stick layers
metal 1
poly

ndiff
pdiff

Stick Diagrams Rules


1. When two or more sticks of the same type cross or touch each other that represents electrical contact.

2. When two or more sticks of different type crosses or touch each other there is no electrical contact. (If electrical contact is needed we have to
show the connection explicitly).

1. When a poly crosses diffusion it represents a transistor.

Note: If a contact is shown then it is not a transistor.

4. In CMOS a demarcation line is drawn to avoid touching of pdiff with n-diff. All pMOS must lie on one side of the line and all nMOS will have to be on the other side.

Demarcation line

Lambda Based Design Rules


Design rules based on single parameter, Interface between designer and process engineer

Guidelines for constructing process masks


Minimum feature size is defined as 2 scalable design rules: lambda parameter

Used to preserve topological features on a chip


Prevents shorting, opens, contacts from slipping out of area to be contacted Design rules specify geometry of masks that provide reasonable yield

Design rules for CMOS wires


Minimum width of n-Diffusion: 2 Minimum width of p-Diffusion: 2 Minimum width of polysilicon: 2

Minimum width of Metal1 : 3


Minimum width of Metal2 : 4

Spacing
Diffusion/diffusion: 3 Poly/poly: 2 Poly/diffusion: 1 Via/via: 2 Metal1/metal1: 3 Metal2/metal2: 4

Metal3/metal3: 4

Design rules for Transistors and contacts


Minimum size of n-mos enhancement transistor:

2x2
Minimum size of p-mos enhancement

transistor: 2 x 2
Contact area: 2 x 2 Contact Spacing: 2 Overlap of diffn or poly over contact:

Contacts (Vias)
Types of via: metal1/diff, metal1/poly, metal1/metal2.

4 1 2

Overlap Rules for Contact cuts

Design rules for p-Well and P+ mask


P-well width : 4 Overlap of internal diffusion: 3 Spacing to external diffusion: 5

Overlap of P+ mask over diffusion : 2

A CMOS Inverter

A CMOS NAND2 Gate

CMOS NOR2 Gate

CMOS NAND3 Gate

Layout optimization
The transistors can be placed in the layout as individual devices Groups with shared polysilicon gate lines Groups with shared drain/source regions Shared drain/source regions among several transistors is

the area efficient placement and reduces wiring


complexity Shared drain/source regions is always not possible to link

transistors

Layout optimization
Graph theory is used for transistor placement in a more structured manner Here drain and source of MOSFET are translated to a nodes called vertices The transistor is represented as edge

x vertex

Edge y vertex

Layout optimization
Euler Graph is used for optimum placement and wiring of circuits To construct Euler Graph, start with a CMOS circuit and select a starting vertex

Find common Euler path for pull-up and pull-down devices


If it is possible to trace the entire graph (pull-up and pull down) with edge passing only once then it is possible to use shared regions

Pull-up: A-B-C-D Pull-down: A-B-C-D

There may be several different valid stick diagrams for the same logic gate. By interchanging the nMOSFETs controlled by C and D, the Euler path can also be chosen as follows.

Pull-up: A-B-C-D Pull-down: A-B-C-D

This results in an equally good but different stick diagram.

Logic Graph
X j B X = C (A + B) C A i B GND X B i A PDN C C VDD PUN

Two Versions of C (A + B)

OAI22 Logic Graph


A B C D X = (A+B)(C+D) C A D B X B A PDN D X C VDD PUN

GND

Layout with non-Optimum Gate Ordering

The stick diagram at the left (done with arbitrary gate

ordering) gives a very nonoptimum layout for the CMOS gate above.

Layout with Optimum Gate Ordering


By reordering the input gates as E-D-A-B-C, we can obtain an optimum layout of the given CMOS gate with single actives for both NMOS and PMOS

devices