Synchronisation Training

Presenter:

Colin Argent

CECP

On behalf of:

Horsebridge Network Systems Ltd.

Contents

Day 1
Introductions Chapter 01 - Time, Frequency and Phase Chapter 02 - Synchronisation Chapter 03 - Sync Distribution layer Chapter 04 - Sync Distribution Layer Clocks Chapter 05 - Sync Distribution Layer Equipment

Day 2
Chapter 06 - Sync Distribution Layer Links Chapter 07 - SDH Network Topology Chapter 08 - Synchronisation Network Architecture Chapter 09 - Synchronisation Standards Chapter 10 - Sync E (Synchronous Ethernet)

Day 3
Chapter 11 - IEEE 1588v2 - PTP (Precision Timing Protocol) Chapter 12 - Boundary and Transparent Clocks Chapter 13 - Clock Measurements Chapter 14 - CALNEX Testing On-screen demo

Chapter 01

Time, Frequency and Phase

Time and Frequency

Time, Time Scales & Dates

There are Two meanings of the word time: - The date of an event on a time scale - As a time interval between two events Time scales : - A time scale is defined by : A time unit A time origin Dates : A date is a number of units on the time scale

The Second
The second is the time unit of the International System of Units (SI) It just so happens that the second is relative to that of Caesium atom transition This means that modern time accuracy is based around time derived from a Caesium device This is commonly known as an Atomic Clock

Clocks
A clock consists of: - A period which can be observed e.g. Secs, Mins & Hrs - A counter which counts the number of periods - A means for setting the counter to a preset value - A display of the registered count

Oscillator

u(t)

Counter

n(t)

Display

T(t)

N0

start

Atomic Time Scales

Origin of Atomic Time Scales : 1 January 1958, at 0hr 0min 0sec - UT2 International Atomic Time (TAI) : Based on atomic time scales and implemented by a network of atomic clocks located all over the earth and operated by the Bureau International de lHeure (BIH) in Paris Coordinated Universal Time (UTC) : Timescale based on the time unit of TAI, transmitted on air from the GPS system In 1967 a new SI definition of a second was created based on the radiation from the caesium-133 atom It is correctly defined as "the duration of 9,192,631,770 periods of the radiation corresponding to the transition between two hyperfine levels of the ground state of the caesium-133 atom"

BIPM

The International Bureau of Weights and Measures

(Bureau International des Poids et Mesures) The realization and dissemination of the international time scales is the responsibility of the Time Section of the BIPM. International Atomic Time (TAI) is the uniform time scale; it is kept as close as possible to the second of the SI. Coordinated Universal Time (UTC) is an atomic time scale derived from TAI, to provide a reference scale in step with the irregular rotation of the earth Local realizations of UTC exist at the national time laboratories. These laboratories participate in the calculation of the international time scales by sending their clock data to the BIPM. Most of them are equipped with commercial caesium beams that provide a practical realization of the second sufficiently accurate for most applications. More accurate caesium standards exist in a small number of laboratories; for them, the uncertainties are estimated to be a few parts in 1015. New developments in clocks using trapped or cooled atoms or ions are leading to improvements well beyond this The atomic time scales TAI and UTC are disseminated monthly through the BIPM Circular T. The Annual Report of the BIPM Time Section provides all relevant information, data and results for the year previous to its publication. Reports on time-transfer techniques are also issued regularly Other activities related to the time scales are developed in the section; these contribute to improving the calculation algorithms and increasing knowledge about time transfer techniques

Frequency
Definition: the number of occurrences within a given time period Unit: Frequency is expressed in [ Hertz = 1cycle/second ]
1

amplitude 0

1x10-7

2x10-7

3x10-7 time

4x10-7

5x10-7 6x10-7

Phase
Phase is the difference in time relationship between two same frequency waveforms It is usually measured in degrees It can be a comparison with an earlier instance of the same waveform - known as Differential Phase
90 180 0 360

270 270Differential Phase Shift

90 Phase
Shift

Round Up
What are the 2 main time standards? What is periodic value of a Caesium atom? What are the 3 main components of a clock? What unit is frequency expressed as?

10

Chapter 02

Synchronisation

Introduction to Synchronisation

What is Synchronisation ?
Definition of Synchronisation The timing of all nodes within digital networks to a common highly accurate and stable clocking source To ensure they all use the same data rates to transmit and receive information

Why do we need Synchronisation ?

If synchronisation is not used node clocks operate asynchronously and the their transmit and receive data rates would be different. This would cause slips or pointer adjustments to occur frequently, seriously degrading the quality of services transported by the network

Types of Synchronisation
3 types of Synchronisation: 1 - Frequency synchronisation

2 - Phase synchronisation

3 - Time synchronisation

Frequency Synchronisation
System A System B

Clock signal of system A

t
Clock signal of system B

Frequency Synchronisation
Transmission data is loaded and recovered from transmission lines by data processing circuits These use a clock edge to denote the transition of one bit to the next
Transmission Link Data Data Data

Clock 1

Clock 2

If Clock 1 & 2 are at different speeds then slips between equipments will occur at the input buffers

Frequency Sync Too Fast

Transmission Link Data Data Data

Clock 1

Clock 2

If the frequency of Clock 1 is higher than that of Clock 2 Data will be clocked into the transmission link at a higher rate than it is clocked out The result will be that data is lost at the receiving end

Frequency Sync - Too Slow

Transmission Link Data Data Data

Clock 1

Clock 2

If the frequency of Clock 1 is lower than that of Clock 2 Data will be clocked into the transmission link at a lower rate than it is clocked out The result will be that data is lost at the receiving end

Phase Synchronisation
System A System B

Clock signal of system A

t
Clock signal of system B

10

Time synchronisation
System A Time signal of system A
14/01/00 14/01/00 14/01/00 08:34:55 08:34:56 08:34:57

System B

Time signal of system B

14/01/00 14/01/00 14/01/00 08:34:55 08:34:56 08:34:57

11

N'wks/Services that require Sync

Public Switched Telephone Networks SONET and SDH transport networks Cellular mobile telecom networks - GSM, UMTS etc Location Services over Mobile Networks - E911, GSM 03.71, etc Ground stations of satellite networks Digital Audio Broadcasting (DAB) Digital Video Broadcasting (DVB) Time distribution for charging & event time stamping Next Generation Networks Wi-Max, MPLS

12

Slips
Slips are the main consequence of poor synchronisation within SDH / SONET networks Slips can have a detrimental effect on quality of service

13

What Are Slips ?

A slip occurs when an equipment input buffer over or underflows due to differences in timing

Incoming data rate

Slip

Outgoing data rate

This results in information being lost

14

Mobile Networks 2G & 3G

Successful handover requires synchronisation between base transceiver stations (BTS)

BTS

BTS

BTS

BTS

15

Cellular Mobile Telecom Networks

Radio carrier frequencies must be synchronised precisely in order to prevent cross-talk

Radio spectrum

Frequency

16

Effects of Frequency Errors

Slip PDH Environment FIFO buffer overflows and dumps its contents Pointer Adjustment SDH Environment 2Mbit/s transmission VC12 pointer adjustments cause phase hits of 3.47s 34 & 140 Mbit/s transmission Pointer Movement at SDH-PDH boundaries PDH takes sync from 2 Mbit/s and needs excellent phase performance Pointer adjustments will create phase hits

17

Services effected by slips

Voice Uncompressed - only 5% of slips lead to clicks Compressed - a slip will cause an audible click Fax A slip can wipe out several lines Modem A slip can cause several seconds of drop out Compressed video A slip can wipe out several lines More slips can freeze frames for several seconds Encrypted/compressed data protocol Slips will reduce transmission throughput Cellular Dropped calls and poor cell handover

18

Implications on Performance
Poor network synchronisation means that network performance is not optimized, quality of service is reduced and customers are lost Implementation of synchronisation in network design enhances Quality of Service for your customers Protection of your customers traffic means confidence, loyalty and ultimately improved business relationships

19

Round Up
So why do we need synchronisation? What are the 3 main types of synchronisation? What is a slip? What can slips cause?

20

Chapter 03 Sync Distribution Layer

Network synchronisation
The objective of network synchronisation is to ensure that all the telecommunication systems use the same transmit and receive data rates to avoid slips So the clocks in the telecommunication systems must be synchronised to the same master network clock, or synchronised to a number of very closely matched master clocks

Distribution Layer function

To generate a primary reference timing signal To distribute timing signals from the primary reference source to nodes and equipment To provide protection against failures in the generation and distribution of timing

Logical Synchronisation Network

Master Clock

Telecom equipment clocks

Master-Slave Mechanism
The clock is injected into the master unit The slave unit locks to the incoming clock rate and is now synchronised to the master No slips occur between these elements

Transmission Link Data

Master Master
Data + Clock PRC 1

Slave Slave

Physical synchronisation network

Not every system in the network can have a direct connection to the master network clock Therefore the telecommunication systems are synchronised in chains or trees Each system clock is the master clock of the subordinate system clocks slaved to it The slave system continually adjusts its own clock to the incoming signal Therefore both the master and slave systems have the same transmit and receive rates There are no slips (WE HOPE!!!!)

Clock types
The clock elements of the synchronisation distribution layer are categorised in three ways: 1. Primary Reference Clock (PRC) - This is defined by ITU-T recommendation G.811 2. Synchronisation Supply Unit (SSU) - The purpose of these elements is to provide filtering and regeneration - Defined by ITU-T recommendation G.812 3. SDH Equipment Clock (SEC) - These devices have an internal SDH Equipment Clock (SEC) that is normally synchronised to a traffic or an external timing input signal - Defined by ITU-T recommendation G.813

Master-slave principle
PRC = master
SEC SEC SEC

= slave
SEC

= slave = slave = slave

SSU = slave

SSU
SEC SEC SEC SEC SEC

SSU = slave
SEC SEC

SEC

SSU

SSU

Sync Distribution (SD) Trails - 1

The clock frequency along an SD trail is the SAME as the head-end, i.e. PRC, SSU or SEC SD trails can be very long or very short There can be hundreds of SD trails in a synchronisation network

Sync Distribution (SD) Trails - 2

There are several types of SD trails:
PRC SD trail - when the head-end is a PRC SSU SD trail - when the head-end is a SSU SEC SD trail - when the head-end is a SEC SSU and SEC SD trails are created only when the PRC SD trail is broken

10

Physical synchronisation networknetwork Physical synchronisation

clock quality traceable back to the SEC clock quality traceable back to the SSU

SEC

SSU

SEC SD trail

PRC

SSU SD trail

PRC SD trail

clock quality traceable back to the PRC

11

Slip Rate due to Freq Deviation

For 2 Mbit/s signals, frame duration = 125 microseconds: 10-11 10-10 10-9 10-8 10-7 10-6 10-5 = = = = = = = 1 slip in 4.8 months 1 slip in 14.5 days 1 slip in 1.45 days 6.9 slips per day 2.9 slips per hour 28.8 slips per hour 4.8 slips per minute PRC G.811 SSU G.812 SSU G.812 SEC G.813 SEC G.813 SEC G.813 SEC G.813

12

Calculating Slip Rates

Normal Calculation for Slip Rates per observation period is: Slip Rate = F x T x D L F= Frequency Offset T= Observation Time D= Data Rate L= Frame Length

13

Calculating Slip Rates Exercise!

Calculate the Slip Rate for the following conditions:

F= Frequency Offset = 1 x 10E-08 T= Observation Time = 86400 Seconds (1 day) D= Data Rate = 2.048Mbps x 10E+06 L= Frame Length = 256

What clock quality would this slip rate equal?

14

Calculating Slip Rates Result

The Solution:
F (1x10E-08) x T(86400) x D(2.048x10E+06) L(256)

= 6.912 or 7 slips per day! F= Frequency Offset = 1 x 10E-08 T= Observation Time = 86400 Seconds D= Data Rate = 2.048E+06 L= Frame Length = 256 So 7 slips per day is G.813 or SEC in HOLDOVER

15

Sync Distribution (SD) Trails - 3

The synchronisation distribution trails are not perfect: what comes out is not exactly what went in This is due to: - Equipment and cables generate jitter and wander - Excessive jitter or wander causes slips - Equipment or cables can fail

16

Jitter
Pattern, or pattern-dependent, jitter is sometimes called "flanging". This type of jitter is not random; it generally results from sub-harmonics Viewed in the time domain, this type of jitter appears as multiple modes. Pattern jitter is deterministic jitter that can be attributed to a unique source. All other jitter is stochastic (random) in nature Jitter can be quantitatively expressed in the following ways:
In unit intervals (UIs). One UI is one cycle of the clock frequency. Jitter expressed in UIs describes the magnitude of the jitter as a decimal fraction of one UI In degrees. Jitter expressed in degrees describes the magnitude of the jitter in units of degree for which one cycle equals 360 In absolute time. Jitter expressed in units of time describes the magnitude of the jitter in appropriate orders of magnitude, usually picoseconds. As a power measurement in units of radians or unit intervals squared, which is often expressed in decibels relative to one cycle squared

17

Wander
Because it involves low frequencies for long periods, wander data can consist of hours of phase information. Because phase transients are of importance, high temporal resolution is also needed. So to provide a concise measure of synchronisation quality, three wander parameters have been defined and are used to specify performance limits: - TIE - MTIE Time Interval Error (wander in ns) Maximum Time Interval Error (related to Peakto-Peak wander) - TDEV Time Deviation (related to RMS wander)

18

Definition of Jitter : ITU- Rec G.810

Definition of Jitter

The short term variations of the significant instances of a digital signal from their reference positions in time Greater than 10Hz in modulation frequency Jitter is caused by the sync trail equipment

Ideal

Jittered Sampling (reading) points

19

Definition of Wander

The long term variations of the significant instances of a digital signal from their reference positions in time Less than 10Hz in modulation frequency Wander is caused by the interaction of technologies in a network

Ideal

Wander Sampling points Sampling points

20

Main Causes of Jitter/Wander

Jitter/Wander is caused by the sync trail equipment
For Example:

MUX / Switch equipment PLL Poor equipment component quality Proximity of components to EMI Microprocessor noise Equipment Transfer functions Length of transmission paths due to cable expansion and contractions Inter-reaction of different technologies e.g. SDH, PDH, ATM

21

PLL Effects on Reference Signals

PLL can overcompensate and oscillate above and below the reference PLL can under-compensate and take too long to get to the reference Changes in Temperature effect the stability of the OCXO Jitter is generated by granularity (steps) in correction voltage applied to the OCXO

22

Jitter/Wander summary

23

Cable Expansion/Contraction
Wc = 80ps/Km/oC, for fibre optical cable Wc = 725ps/Km/oC, for copper cable
20oC

1010111001010101000001100101000100010
40oC
Cable has expanded - the bits come out later

1010111001010101000001100101000100010
0oC
Cable has contracted - the bits come out earlier

1010111001010101000001100101000100010

24

ITU-T G.823 Model of Wander

Specifies the maximum network limits for jitter and wander that should not be exceeded Specifies the minimum equipment tolerance to jitter and wander based on the 2048 kbit/s hierarchy The jitter control philosophy is based on the need: - to recommend a maximum network limit that should not be exceeded at any hierarchical interface - to recommend a consistent framework for the specification of individual digital equipments - to provide sufficient information and guidelines for organizations to measure and study jitter accumulation in any network configuration

25

ITU-T G.823 Wander formula

The maximum relative wander between the slave clock and the data input at a node is: Dwpk = WequipPk + WconnectionsPk + < / = 18s The formula allows the planner to calculate the accumulated Wander by simply adding the sum of each element within the network This total must be less than 18s to adhere to G.823

26

ITU-T G.823 Network Wander

PRC PRC
Cable A Wa = 6 Microseconds
Total Wander = 18microseconds

Cable C Wc = 6 Microseconds

Equipment Wander = Slave Slave 1 microsecond

Slave Slave Cable B Wb = 4 Microseconds

Equipment Wander = 1 microsecond

This diagram demonstrates the effect of accumulative wander

27

The control of jitter and wander

SDH requires that jitter and wander be kept below tight network limits. This is achieved by inserting narrow-bandwidth SSUs in the synchronisation chain (SEC bandwidth is relatively wide). Narrow-bandwidth SSUs attenuate jitter and wander components that lie outside the SSU bandwidth.

28

Sync Distribution in SDH - Rules

PRC
SEC SEC SEC

N x SECs
SEC SEC SEC

Level 1

SASE
SEC

SASE
SEC

SASE
SEC

N = 20 Max Level = 10 Max Maximum 60 SECs in a single trail

N x SECs
SEC SEC SEC

Level 2

SASE
SEC

SASE
SEC

SASE
SEC

N x SECs
SEC SEC SEC

29

Synchronisation reference chain

See ITU-T G.803 or ETS 300 462-2 The ITU-T/ETS synchronisation reference chain meets the network limits on jitter and wander: Not more than 60 SECs in a chain Not more than 20 SECs between two SSUs Not more than 10 SSUs in the chain

30

Distribution Layer composition

The SDH Synchronisation distribution layer is comprised of 3 parts:
1. Clocks

2. Equipment

3. Links

31

Round Up
What are the two main causes of synchronisation problems? What equipment is normally at the top of a sync tree? What is the maximum allowed wander under G.823?

32

Chapter 04 Sync Distribution Layer - Clocks

Distribution Layer Clocks

The clock element of the synchronisation distribution layer is categorised in three ways:
1. Primary Reference Clock (PRC) 2. Synchronisation Supply Unit (SSU) 3. SDH Equipment Clock (SEC)

PRC Systems
The PRC System is a master clock used to synchronise the entire network with a frequency accuracy of < 1 x 10-11 This is defined by ITU-T recommendation G.811. A complete Primary Reference Clock consists of the following:
3 separate Primary Reference Sources Reference Selector Tracking Unit Output Distribution Unit

Typical PRC
SASE Unit GPS 1
Input stage & reference Selector Tracking Oscillator Section Output Section

Caesium 1

Caesium 2

Primary Reference Source

This is a single source of G.811 Reference which is used to feed a PRC or can be used as a standalone reference This can take two forms:
1. Caesium reference source 2. Off air source i.e. GPS, Loran, GLONASS

Caesium PRS
These elements are usually expensive items but provide the network with its own source of synchronisation
The beam can last up to 10 years before requiring a re-tube They provide a stability of 1x10-11 over 20 years Where two beams are compared the maximum difference between the two beams equates to 2x10-11 which will result in 1 slip every 72 days on E1 links This is the standard set by ITU and can be found in ITU-T G.811

Off-air PRS
Off-air Primary Reference Sources provide an excellent alternative or additional reference to Caesium This is a single source of G.811 Reference which is used to feed a PRC or can be used as a standalone reference Off-air Primary Reference Sources include: Global Positioning Systems (GPS) Loran GLONASS GPS is the most commonly used

GPS as a PRS
The raw GPS signal contains various information including UTC time and identification data for navigation purposes The GPS satellites contain Caesium beams which are used to provide the accuracy needed for time and location information In Telecoms it is the stability of the Satellites Caesium that is of interest. Therefore receivers used in telecoms are specific to the requirement The signal is received by the GPS receiver and is converted into a useable source for slaving a local oscillator. The resulting output is G.811 compliant and therefore is suitable to be used within a PRC

PRS Operation
Three PRS sources are fed into an SASE (Stand Alone Synchronisation Equipment). This forms the hub of the PRC The SASE is normally configured to be completely redundant. It will contain an input stage, a prioritising and selection mechanism to determine which source it will utilise, a tracking oscillator unit and an output stage

Which PRS is Best?

Technically both are perfectly acceptable sources. The differing factor is mainly down to cost On the surface GPS looks like a cheap option, but beware, it is not always easy to obtain permission from landlords to fit antenna systems and the cost of installation can be more than the cost of the units When deciding on a solution look at the cost of each of the options and consult your vendor as to what is most cost effective Most common forms of PRC use a combination of different types of PRS

10

Oscillators
PLL Phase Lock Loop
The Most common form of slaving an oscillator This function employs a feedback mechanism which feeds the Oscillator output into a comparator where the signal is compared with the input and the difference is sent as correction voltages to the oscillator

11

Phase Lock Loop

Simple Block Diagram of a Phase Lock Loop
Phase Comparator Input Referenc e

S1 + S2

Error Pulses

Low Pass Filter

Error Correction Voltage

Voltage Controlled Oscillator

Output

Frequency Divider (optional)

Feedback Path

12

Slaved Oscillator Mechanisms

DDS Direct Digital Synthesis
A mechanism in which the Oscillator is free running and the output signal is synthesised in software with the incoming reference signal to produce a stable output

13

Chapter 05 Sync Distribution Layer - Equipment

Synchronisation Elements
SASE SSU TNC CTO BITS - Stand Alone Synchronisation Equipment - Synchronisation Supply Unit - Transit Node Clock - Compact Tracking Oscillator - Building Integrated Timing Supply

All refer to the same class of equipment Used with PRCs or standalone for regenerating timing signals Modular by design and configured to be redundant to allow for single or multiple internal and/or external failures

The SASE
SASE stands for Stand Alone Synchronisation Equipment (Element) The purpose of these elements is to provide filtering, regeneration and distribution of a primary reference signal This is achieved by simple yet highly accurate equipment The equipment is designed to be very resilient to internal and external failures therefore all components are at least duplicated

SASE Architecture
Input Interface
Jitter/Wander

Output Interface Output Interface Output Interface

Low-Pass Filter

Input Interface

Reference

Selector

Input Interface

Holdover Memory

Output Interface

SASE Input Section

Inputs
Most SASEs have multiple input capability, allowing the unit to select from a number of references The amount and type of inputs are dependent upon the make and model. For regeneration purposes, 2 or 3 inputs are sufficient

SASE Reference Selectors

Reference Selectors
Within each SASE will be the reference selector. Normally this is duplicated for redundancy. This section contains the priority table and selection criteria for the units inputs Selection can be made by the following methods Automatic Manual Forced Synchronisation Status Message (SSM)

SASE - Selection Modes

Selection Modes
Automatic This mode will choose the highest available priority source set within the priority table Manual Forced SSM This mode will only switch to another available input by manual intervention This mode will stay fixed to its intended sync source at all times The selection is dictated by the incoming SSM information

SASE - Fltering & Holdover

Filtering & Holdover section
This section of the unit provides the filtering of the reference signal. This can be achieved using two techniques: - Phase Lock Loop - PLL - Direct Digital Synthesis - DDS This section should be duplicated for redundancy All SASEs employ a mechanism which prevents phase and frequency jumps when switching between channels

SASE Output Section

Output Stages
Most SASE output arrays allow for different output frequencies to be used. 2.048Mhz is the most common for SDH but 1MHz, 10MHz, E1 Framed, etc. can all be generated by the SASE. Consult your vendor if specific frequencies are required Again these can be configured to provide protection in the event of a hardware failure Cards can be fitted with differing protocols. In some units the framing and bit pattern of E1 or T1 signals can be altered to generate AIS and other states. Units may also have the ability to change output protocol by means of software, e.g. 2.048Mbps to 2.048Mhz

Which SASE Configuration?

When deciding which equipment is right for your network, it is important to look at the application first SASEs can be fitted with an array of different cards and clock types Review the importance of the location and the equipment the SASE is to be connected to, before deciding on oscillator types and configuration Typically, SASEs should be used within the core of the transmission network

10

SDU Sync Distribution Unit

The purpose of the SDU is to expand the capacity of an SASE O/P The SDU typically has two I/Ps and no Hold over capability The SDU will have a large O/P capacity - consider it as an amplifier for Synchronisation signals An SDU will typically be referenced from an SASE or SSU

11

SDU Layout
Output Interface
Low Loss Splitter

Input Interface

Output Interface Output Interface Output Interface

Input Interface

12

SDU Inputs
SDU Inputs
The SDU will normally have two input Interface Units, these are typically 2Mhz. Jitter can be filtered on these units The SDU I/P reference source are often derived from an associated SASE / SSU SDUs can be daisy-chained: however the lack of holdover and wander filtering make this undesirable Some manufacturers have incorporated a HOU (Hold Over Unit) capability - this is normally for a single channel

13

SDU Outputs
SDU Outputs
The SDU is designed as a low cost, high O/P capacity option Most SDU output arrays allow for different output frequencies to be used. 2.048Mhz is the most common for SDH but 1MHz, 10MHz, E1 Framed, etc. can all be generated by the SASE. Consult your vendor if specific frequencies are required Again, these can be configured to provide protection in the event of a hardware failure

14

SDH Elements
With the possible exception (depending on manufacturer) of the Optical Line Amplifiers, all the following equipments contain SECs (SDH Equipment Clocks) and should be counted within the trail count for SDH design: Add Drop Multiplexers -- Microwave Systems Cross-Connects -- Regenerators Optical Line Amplifiers
This internal SEC is normally synchronised to a traffic or external timing input signal
Traffic & timing input External timing input

1 n

SEC

Traffic & timing output External timing output

15

SDH Equipment Clock (SEC)

Synchronous Equipment Timing Source (SETS)
STM-N input

Selector C

PDH input
External timing input (2 MHz or 1.5 Mbit/s or 2Mbit/s)

SDH Equipment Clock

Synchronous Equipment Timing Generator

External timing output (2MHz or 1.5 Mbit/s, or 2Mbit/s)

NE internal timing

16

SDH SEC features

Input synchronisation signals are: STM-N aggregates and tributaries 2Mbit/s tributaries 2MHz and 2Mbit/s (non traffic) timing inputs Input selection is determined by: a priority table, that is user definable Synchronisation Status Message (SSM) on the STMN and 2Mbit/s interfaces Output synchronisation signals are: All STM-N aggregates and tributaries 2MHz and 2Mbit/s (non traffic) timing outputs

17

SEC Timing options

Line timing: in nodes not equipped with a node clock (SSU) External timing: in nodes equipped with a node clock Tributary timing: only in exceptional cases, e.g. during the evolution from PDH to SDH Internal timing: when all synchronisation reference signals are lost (= holdover mode)

18

SEC Line Timing

Line timing: in nodes not equipped with a node clock (SSU) Timing is extracted from the STM-N (optical overhead) In normal operating conditions timing is traceable to a G.811 primary reference

Line timing
STM-N STMSTM-N STM-

19

SEC External Timing

External timing: in nodes equipped with a node clock Used for synchronisation injection points within the network Normally either a 2 MHz or 2 Mbit/s reference signal Node clock traceable to G.811 Primary Refence Source Node Clock has G.812 holdover capability

External timing
STM-N STMSTM-N STM-

2 MHz or 2Mbit/s

20

SEC Internal Timing

Internal timing: when all external timing references are lost Intended for failure conditions SEC Clock has G.813 holdover capability

Internal timing
STM-N STMSTM-N STM-

21

SEC Timing Outputs

If a 1.5Mbit/s, 2MHz, 2Mbit/s synchronisation output is

derived from the Synchronous Equipment Timing Generator (SETG), then it is called a SETG locked output
If a 1.5Mbit/s, 2MHz, 2Mbit/s synchronisation output is

directly derived from the OC-N or STM-N input, then it is called a non-SETG locked output
The 2MHz timing output can be squelched when : The SEC enters hold-over or free-run mode The input SSM falls below the set threshold

22

SEC - Selection Modes

Automatic This mode will choose the highest available priority source set within the priority table Manual This mode will only switch to another available input by manual intervention This mode will stay fixed to its intended sync source at all times The selection is dictated by the incoming SSM information

Forced

SSM

23

Inter-working: SDH NE & SASE

SDH NE
Noisy traffic & timing input External timing output External timing input cleaned traffic & timing outputs

SASE

24

Round Up
What are the 3 main equipment types found in the sync distribution layer? What is a SEC? What provides the higher clock order - PRS or SEC? What is the difference between a SASE and an SEC?

25

Chapter 06 Sync Distribution Layer - Links

SDH Sync Link connections - 1

Supported by an SDH multiplex section trail i.e. the timing information is carried by the STM-N data rate (N x 155 Mbit/s) by a retimed PDH E1 connection SDH regenerator timing generators are not counted as elements of the synchronisation distribution layer, they belong to the synchronisation link connection The SDH multiplex section trail may be supported by an optical transport layer such as DWDM (dense Wavelength Division Multiplexing) or OTN (Optical Transport Network)

SDH Sync Link connections - 2

PRC
Synchronisation link connection

SSU

Synchronisation

SDH

SDH Multiplex section trail

SDH

SDH/SONET

OTN

OTN

OTN/DWDM

Optical Trail

Types of Oscillators in Links

Oscillators are a common section of all of the three clock types described Various types of oscillators exist and their selection is based upon the application, i.e. PRC, SASE or SEC, that they are to be utilised within The main types of crystal oscillators are: Caesium High Quality Rubidium Low Quality Rubidium High Stability Double Oven OCXO Single Oven OCXO Temperature Controlled TCXO

Rubidium Oscillators
Atomic Standard Tracking Oscillators are extremely stable and thus are very suitable for using within a telecom network Typically these oscillators are used within a Primary Reference System as Slaved units to Caesium or GPS These are usually the most expensive tracking oscillators available They have a life span varying from 6 to 12 years, depending on Manufacturer The longer life span of Rubidium oscillators is achieved using DDS rather than PLL techniques within the clock element Usually Maintenance Free Holdover Quality dependent on Manufacturer, typically 1x10-11/mth

Single Oven OCXO

Relatively inexpensive OCXO Provides Holdover of 1x10-9 to 1x10-10 per day depending on Manufacturer Usually suited for Standby oscillators within SASEs or as Local Node Clock Systems They will also be found in Large transit Switches and XConnects

High Stab. Double Oven OCXO

Life span of 20+ years Maintenance free Lower cost than Rubidium Holdover is typically 1x10-11/day Can be used in a Primary Reference System or as a SASE Oscillator

Temperature Controlled TCXO

Inexpensive Oscillators Maintenance free Used in a majority of Telecom equipment such as Multiplexers and Radio Systems Holdover of 1x10-6 per day or less

Typical Oscillator Performance

Oscillator Type Rubidium Low cost Rubidium High Stability Double Oven OCXO Single Oven OCXO TCXO Holdover Quality
(Typical)

Slip Rate
(Worst Case)

1x10-11/m 5x10-11/m 1x10-11/d

1 after month 1 after week 1 after 3.5 days

2x10-10/d 2x10-6/d

1 after 1 day 1400 per day

Oscillator Characteristics
Oscillators are susceptible to changes in temperature and stability of rectified power Variations in these conditions can affect the performance of the oscillator

10

Retimed PDH Sync Link - 1

PDH path layers supported by SDH path layers are not suitable for transporting synchronisation Retiming is used when E1 traffic signals transported over SDH are used as synchronisation links (e.g. to synchronise distant PABXs or GSM BTSs) Retiming is applied on E1 traffic signals affected by excessive wander (e.g. from pointer adjustments) Retiming buffers can be integrated in the SDH network element or the SASE

11

Retimed PDH Sync Link - 2

SDH network element

STMN
SEC

SEC timing signal PDH tributary output PDH tributary output PDH tributary output

Retiming Buffer Retiming Buffer Retiming Buffer

re-timed rePDH signal re-timed rePDH signal re-timed rePDH signal

12

Retiming
The retiming buffer transmits the incoming traffic at the data rate of the SEC timing signal, thus removing the excessive wander The long-term frequency (data rate) of the E1 traffic signal must be synchronized to the network PRC Slips will occur if the SEC has lost its synchronisation to the PRC

13

Round Up
What is the synchronisation link layer? How is synchronisation transported from site to site? How is synchronisation delivered within the node? Name 3 Oscillator types

14

Chapter 07 SDH Network Topology

Master-Slave Principle
A designated master clock is used as a reference frequency generator The frequency generated by the master clock is disseminated to all other clocks which are slaved to the master clock

Master-Slave Mechanism
The clock is injected into the master unit The slave unit locks to the incoming clock rate and is synchronised to the master No slips occur between these elements

Transmission Link Data

Master Master
PRC 1

Data + Clock

Slave Slave

Master-slave principle
PRC = master
SEC SEC SEC

= slave SEC = slave

SSU = slave

SSU
SEC SEC SEC SEC SEC

SEC

SEC

= slave SEC = slave

SSU = slave

SSU

SSU

Principle of trail redundancy

Each slave clock should get at least two reference signals from the master clock via geographically separate trails Sometimes it is not possible to fulfil this principle for all nodes of the network (depending on connectivity)

Hierarchy of Quality Levels

There is a hierarchy of clock quality levels The higher the clock quality level, the higher the frequency accuracy of the clock Frequency accuracy =
either overall free-run accuracy or holdover accuracy over a limited time period

Clock Quality Levels

2048 kbit/s based: PRC: 1E-11 SSU I: 2E-10/d SEC 1: 4.6E-6 1544 kbit/s based: PRC: 1E-11 SSU II: 1.6E-8/1yr SSU III/IV: 4.6E-6 SEC 2: 20E-6

Weak Hierarchical Distribution

RULE A clock of a given quality level must always (even under failure conditions) take timing (directly or indirectly) from a source clock with the same or higher quality level

Implementing the Rule

Question:
How can we implement the Weak Hierarchical Distribution Rule? ..........

Answer:
By implementing the Strong Hierarchical Distribution Rule: A clock of a given quality level must take timing (directly) from a clock with the same or higher quality level Or by the use of SSM signalling

Strict Hierarchical Layering

PRC

SSU

SSU

SSU

SSU
SEC SEC SEC

SSU

SEC

SEC

SEC SEC

SEC

SEC

SEC

10

Failure Scenario
PRC
SEC SEC SEC

Link failure! Holdover mode!

SEC

SSU
SEC SEC SEC SEC SEC SEC

SSU

SEC SEC

SSU

SSU

SSU

11

Sync network with SSM

There is a link failure within a chain of SECs The SSM signalling prevents the downstream SSU from following a SEC in holdover mode Instead, the downstream SSU enters holdover mode and becomes the source clock for the cut off sub-network

12

The control of jitter and wander

SDH requires that jitter and wander be kept below tight network limits This is achieved by inserting narrow-bandwidth SSUs in the synchronisation chain (SEC bandwidth is relatively wide) Narrow-bandwidth SSUs attenuate jitter and wander components that lie outside the SSU bandwidth

13

Sync Distribution in SDH

PRC
SEC SEC SEC

N x SECs
SEC SEC SEC

N = 20 Max

Level 1

SASE
SEC

SASE
SEC

SASE
SEC

N x SECs
SEC SEC SEC

Maximum 60 SECs in a single trail

Level 2

SASE
SEC

SASE
SEC

SASE
SEC

N x SECs
SEC SEC SEC

Maximum 10 SASEs in a single trail

14

Synchronisation reference chain

See ITU-T G.803 or ETS 300 462-2 The ITU-T/ETS synchronisation reference chain meets the network limits on jitter and wander: Not more than 60 SECs in a chain Not more than 20 SECs between two SSUs Not more than 10 SSUs in the chain

15

Summary
PRC SSU

Synchronisation PSTN

PSTN

SDH

SDH

SDH/SONET

OTN

OTN

OTN

16

Synchronisation Signalling layer

Function:
To provide the source clock quality level from clock to clock down the synchronisation chains, in order to:
Enable clocks to select the best available reference timing signal Enable clocks to go into holdover mode if reference timing signals are of low quality Prevent timing loops in SDH chains and rings

17

SDH Sync Status Messages

The clock source quality level is indicated by the

Synchronisation Status Message (SSM)

In SDH, the message set is: QL-PRC QL-SSU-A QL-SSU-B QL-SEC QL-DNU

= PRC, G.811 = SSU, G.812 Type I or V = SSU, G.812 Type VI = SEC, G.813 Option 1 = Do not use

18

SSM Transmission Channels

The timing quality level carried by STM-N signals (SDH) is indicated by the S1 byte in the STM-N Multiplex Section Over Head (MSOH) The timing quality level carried over 2048 kbit/s synchronisation signals is indicated in one of the bits Sa4 to Sa8 in Time Slot Zero (TS0) 1544 kbit/s T1 signals: see ITU-T Rec. G.704 34 Mbit/s E3 and 140 Mbit/s E4 signals: see ITU-T Rec. G-832

19

SSM Algorithm
Always select the highest quality input and if a number of equal quality timing inputs are available, then select the highest priority timing input In locked mode, the output SSMs are set to the selected input SSM e.g. G.811 in = G.811 out The SSM in the return direction of the selected input is automatically set to Do Not Use (DNU)

20

If all inputs are bad ...

The SEC enters holdover mode The SEC memorises the phase and frequency values of the last known good input, but quickly drifts toward 4.6 x 10-6 The SEC will be in free-run mode if it has never locked to a higher level reference signal Ext Clock Out signals should be squelched Output SSM STM-n value is set to G.813 (unless manually set)

Unfortunately, SECs inject jitter on to the PRC signal and accumulative jitter can cause slips

21

SDH ring sync protection

Automatic SSM correction and automatic
synchronisation distribution trail reconfiguration under failure conditions Using the SSM algorithm

Revertive operation
SD trails returns to the original paths when the failed section or the failed network element has been repaired No operator action is needed

22

Revertive/Non-Rev Switching
Revertive switching will allow previously disqualified inputs to be re-qualified and re-selected as the selected source Non-Revertive switching will not allow previously disqualified inputs to be re-selected if they return to a useable reference Pros & Cons are associated with either option. The operator must decide which method to use as a standard for the whole network

23

Chapter 08 Synchronisation Network Architecture

Centralised or Distributed PRC

Two methods of deploying PRCs are utilised in todays networks:
Centralised Distributed

A combination of both methods is also a valid strategy for Synchronisation

Centralised PRCs - 1
This method was typically used by operators when PDH systems were used as the main transmission media. This method, utilised 2 or 3 fully equipped PRCs located separately. The clock was embedded within the E1 bearer on the Primary Multiplexers and distributed over the PDH to the Exchanges. Each PRC system typically employed three Caesium beams for redundancy. These systems were expensive to purchase and required maintenance to be carried out.

Centralised PRCs - 2
In todays networks the Centralised PRC is still supported and is still valid for timing SDH. With the onslaught of new technologies and transport mechanisms, new operators have approached the issue of network synchronisation differently. Preferring to have multiple low cost PRS clocks situated all around the network Distributed PRCs.

Physical View
The PRC distributes timing through master slave Synchronous Equipment Clocks. All elements are traceable to the PRC
SEC SEC

SEC SEC

SEC

Equipment Clocks

PRC
SEC SEC SEC SEC

SEC

SEC

SEC

SEC

PRC = Primary Reference Clock

Distributed PRS - 1

There are many primary reference sources distributed in the network The most common form of PRS utilised for this purpose is GPS The GPS satellite system distributes USNO-UTC-derived time and timing to all GPS-clocks Each GPS-clock is the master of a synchronization subnetwork This is also referred to as decentralised PRCs

Distributed PRS - 2
This mode of clocking is favoured by the new operators. Mainly due to having isolated sites or regions which are linked by lines, leased from the incumbent carrier In this instance, trace-ability is lost when transported over another operator's network. Therefore, installing primary reference sources at all sites ensured synchronisation quality is maintained

Distributed PRS - 3
Leased Transmission Link Data + Clock PRS 1

Data

Master Master

Master Master
PRS 2

Each element or node is timed by a separate high stability clock These are virtually identical speeds (accuracy of 1x1011) Will cause one slip every 72 days - perfectly acceptable

Physical View
Region 1 Region 2
SEC SEC SEC SEC SEC SEC

PRC
SEC SEC SEC Local Equipment Clocks SEC SEC SEC

PRC
SEC

Timing Feeds Traffic Links PRC Primary Reference Clock SECSDH Element Clock
SEC

PRC
SEC

Region 3

Mixed sync distribution - 1

Mixed synchronisation network architectures offer a combination of benefits from centralised and distributed PRS solutions Less wander due to short synchronisation chains Simplified network design Easy to modify the network (evolution) Low risk of creating timing loops

10

Mixed sync distribution - 2

n n n n n n

G
n n n

G
n n

G
n

M
n n n n n n

G
n n n

G
n n

G
n

GPS-clock

central master clock

node n clock

equipment clock

Sub-network

11

Sync entirely based on GPS

It is technically feasible to deploy one GPS-clock per node Less wander due to very short synchronization chains Very simple network design Easy to modify the network (evolution) Very low risk of creating timing loops Not robust enough, since there is only one synchronization reference signal available (dual GPS receivers do not provide protection against interference and jamming!) - no trail redundancy Not economical for very large networks with many nodes, because of total equipment cost

12

Which Strategy is Best? - 1

There are benefits and drawbacks to both options. Both methods are perfectly acceptable With distributed GPS there is a cost impact for installation and technically speaking there are multiple boundaries inside the network Plan for a failure. If one GPS fails the network must be able to recover from a standby GPS or if possible from a GPS at an adjacent site

13

Which Strategy is Best? - 2

With a centralised PRC careful planning is required to prevent timing loops Inter oscillator chain length can be large, so regenerator units such as SASEs are required If planned correctly this can be a more cost effective way of synchronising the network All elements will be traceable to one Master Clock

14

Equipment cost model

Total equipment cost

GPS-BASED SYNCHRONISATION DISTRIBUTION: (single GPS + SASE) per node WIRED (PDH- OR SDH-BASED) SYNCHRONIZATION DISTRIBUTION: one central PRC with 3 Cs clocks, and one SASE per node

60-80

number of nodes or synchronisation sub networks

15

Sync from a co-operating N'wk - 1

Most common when there is no PRC in the network All clocks in the network are slaved to synchronization signals from a co-operating network Under normal operating conditions all slave clocks operate at the same frequency as the PRC in the cooperating network There are normally no slip for on-net and off-net traffic to the co-operating network

16

Sync from a co-operating N'wk - 2

The clock signals from the co-operating network may be received at only a few synchronisation gateway nodes The clock signals from the co-operating network may also be received at every node, or at every sub-network

17

Sync from a co-op N'wk - Issues

The networks synchronisation performance is dependent on the quality of the synchronisation signals from the co-operating network There must be an agreement with the co-operating operator on service level The cost to lease the synchronisation signals can be high

18

Agreement on sync interfaces

Physical interface specification (e.g. 2 Mbit/s, G.703) SSM configuration Guaranteed synchronization quality (e.g. G.823 Network Limit) Upstream synchronisation chain length (number of clocks) Guaranteed availability of agreed quality (e.g. 0.9999) Mean Time to Repair in case of failure Worst case quality degradation in case of failure (e.g. max. frequency error, max. frequency drift, max. jitter & wander) Alarming method in case of failure (e.g. SSM) Quality monitoring criteria

19

Round Up
What is a master slave clock arrangement? What is a centralised PRC system? What is a de-centralised PRC system? Which system is best? Give two examples of a PRS

20

Chapter 09 Synchronisation Standards

Standardisation Bodies
International level : Regional level, Europe: USA: Industry level: e.g. Company level: e.g. ITU ETSI ANSI TIA Bellcore Recommendations Legally binding standards Legally binding standards Industry standards Internal standards

ITU : ETSI : ANSI : TIA:

International Telecommunication Union European Telecommunications Standards Institute American National Standards Institute Telecommunication Industry Association

ITU-T Recommendations

ITU-T Rec. G.810

Definitions for synchronisation networks Includes the definitions of time error, MTIE, TDEV, etc.

ITU-T Rec. G.803

Architecture of SDH transport networks Section 8.2: architecture of SDH-based synchronisation networks Section 8.2.4: synchronization network reference chain

ITU-T Rec. G.823 (11/98)

The control of jitter and wander in PDH networks based on the 2048 kbit/s hierarchy: 1.\ Maximum network limits on jitter and wander 2.\ Minimum equipment tolerance to jitter and wander

G.823 - What does it specify?

Network limits for traffic interfaces Network limits for synchronization interfaces Jitter and wander tolerance of traffic interfaces

ITU-T Rec. G.824

The control of jitter and wander in PDH networks based on the 1544 kbit/s hierarchy Similar to ITU-T Rec. G.823, but for the 1544 kbit/s based PDH network

ITU-T Rec. G.825

The control of jitter and wander in SDH networks based on the 2048 kbit/s hierarchy Similar to ITU-T Rec. G.823, but for SDH networks

ITU-T Rec. G.811

Specification for Primary Reference Clocks (PRC) It is an equipment specification Specifies only one PRC type

10

G.811 - What does it specify?

Frequency accuracy Noise generation Phase discontinuity in case of internal protection switching

11

ITU-T Rec. G.812 (6/98)

Specification for Node Clocks (Node Clock is the ITU-T term for SSU) It is an equipment specification Specifies six SSU types

12

ITU-T Rec. G.812 - SSU Types

SSU Type Which hierarchy? Primary Application Which case?

Type I Type II Type III Type IV Type V Type VI

2048 kbit/s 1544 kbit/s 1544 kbit/s 1544 kbit/s 1544 & 2048 kbit/s 2048 kbit/s

Sync. chains as long as G.803 reference chains Distribution hubs End offices (1) If used in SDH: must also comply with G.813 option 2 Existing (2)transit nodes; same as TNC G.812 - 1988 Existing (2)local nodes; same as LNC G.812 - 1988 (1) single input reference ;

Note (1): see Bellcore terminology Note (2): prior to introduction of SDH

13

G.812 - What does it specify?

Frequency Accuracy Pull-in, hold-in, and pull-out ranges Noise tolerance Noise generation Noise transfer Transient response in case of input reference switching Holdover performance Phase discontinuity in case of internal protection switching

14

ITU-T Rec. G.813

Specification for SDH Equipment Clocks (SEC) It is an equipment specification Specifies two SEC types: SEC Option A: 2048 kbit/s hierarchy SEC Option B: 1544 kbit/s hierarchy

15

G.813 - What does it specify?

Frequency Accuracy Pull-in, hold-in, and pull-out ranges Noise tolerance Noise generation Noise transfer Transient response in case of input reference switching Holdover performance Phase response to input signal interruption Phase discontinuity in case of internal protection switching

16

Round Up
What does ITU-T G.811 specify? What does ITU-T G.812 specify? What does ITU-T G.813 specify? How many levels are defined under G.812?

17

Chapter 10 Sync E (Synchronous Ethernet)

Whats driving the industry?

Networks migrating to Packet but mission-critical Comms and Data need accurate timing Must continue to provide the same quality of synchronisation delivered today by TDM Can this be done without the need to retain the T1/E1 links used today to transfer synchronisation?
Core Network

Today: Hybrid Network Base Station

Ethernet TDM

Future: Ethernet-only Base Station

Sync-E and IEEE1588V2 compared

Synchronous Ethernet delivers Frequency Only
Regular heartbeat on link signal provides frequency synchronization.
Application GSM UMTS/ W-CDMA UMTS/ W-CDMA femtocells GSM, UMTS, LTE Network Interface CDMA2000 TD-SCDMA Frequency 50 ppb 50 ppb 250 ppb 16 ppb, suggested to meet 50ppb RF specification 50 ppb 50 ppb 50 ppb 50 ppb Time N/A N/A N/A

IEEE1588V2 delivers Frequency, Phase & ToD less than 100 nanosecond (target 50nS) time-of-day precision over Ethernet LAN. Less than 1s time-of-day precision over switched Ethernet WAN. stable frequency (1.6x10-8 or 16ppb) recovery (from time-of-day reference).
1588V2 CAN MEET & EXCEED MOBILE NETWORK REQUIREMENTS

N/A Should +/-3s, shall +/10s +/- 1.5s N/A +/- 1.5s small cell, +/5s large cell +/- 1-32s, implementation dependent +/- 500 ns (0.5 s), pre-standard +/-1 - 8 s, implementation dependent

LTE (FDD) LTE (TDD)

LTE MBSFN LTE-A CoMP (Network MIMO) WiMAX (TDD)

50 ppb

50 ppb 2 ppm absolute, ~50 ppb between base stations

Building a N'wk with SyncE/1588v2

G.8260

Definitions / terminology

(Definition)

Agreed

Ongoing

G.8260
(metrics)

Consent Dec2011

Frequency: G.826x

Time/Phase:G.827x
G.8271

Basics Network requirements Clock

G.8261

SyncE NetwkJitter-Wander: Included in G.8261

G.8271.1
(NetwkPDV_time/phase

G.8261.1
(NetwkPDV_frequency)

G.8271.2
may be needed in future

G.8262
(SyncE)

G.8272
PRTC

73.1-GM 73.2 BC 73.3 TC

G.8263 G.8264

G.8273

Methods

(SyncE-architecture)

G.8265
(Packet-architecture-Frequency))

G.8275
(Packet-architecture-time)

G.8265.1

Profiles

G.8275.1
(PTPprofileTime/phase)

(PTPprofileFrequency)

G.8265.m
(PTP Profile frequency m)

G.8275.n
(PTPprofileTime/phase n)

ITU-T Standards

Synchronous Ethernet (SyncE)

Line rate of the Ethernet Interface used to transfer timing No impact/demand on packet layers Defines the use of a high stability oscillator to generate line frequency
Ethernet Classic: 100ppm
Synchronous Ethernet: 4.6ppm

ITU-T Standards in place G.8262: Timing Characteristics for Synchronous Ethernet Equipment G.8261: Timing & Synchronisation in Packet Networks G.8264: Distribution of Timing Through Packet Networks (ESMC)

Challenges
Cost: All interfaces need to be Sync-E compatible Cannot be used with existing Ethernet equipment when transferring synchronisation

~
PRC

~
PRC

Conformance Testing - Jitter

Sync-E (1GbE/10GbE) ITU-T G.8262
EEC

1G/10G SyncE

1G/10G SyncE

Jitter Generation Jitter Tolerance

Conformance Testing - Wander

Sync-E (100M/1GbE/10GbE) ITU-T G.8262
Frequency Accuracy Synchronisation Source Reference Pull-in, Pull-out, Hold-in Wander generation Wander tolerance 100M/1G/10G SyncE EEC Wander transfer

100M/1G/10G SyncE Reference SyncE (Wander-free) EEC

Phase transient response

SyncE Under Test

Jitter/Wander measurement
narrow-band filter (jitterless) internal

wide-band filter (jittered)

internal

Sync architecture for Sync-E

PRC

G.812 Type I (SSU)

Number of G.812 type I clocks < 10

SEC

SEC G.8262 is Compatible with G.813

Number of G.813 option 1 clocks < 20

SEC

EEC

SEC Total number of G.813 clocks in a sychronisation trail should not exceed 60

EEC

SEC

SEC

G.812 Type I (SSU)

10

White Paper & Application Note

11

G.8260
Metrics
1588v2

Network

pktfilteredMTIE

Metrics released as ratified by ITU-T Includes pktfilteredMTIE, MATIE, MAFE, etc.

12

G.8261 Appendix VI
Slave Clock (Frequency) Test (Old)

Apply G.8261 or Network Profiles, Measure E1/T1 MTIE/TDEV (now) Stress multiple slaves with G.8261 or Network Profile (H1 2012) Stress multiple slaves with multiple profiles (H2 2012)

13

G.8263
Slave Clock (Frequency) Test (New)

Apply G.8263 Profile, Measure E1/T1 MTIE/TDEV (now) Apply G.8263 Profile to multiple slaves, Measure E1/T1 MTIE/TDEV (H1 2012) Apply G.8263 Profile to multiple slaves, Measure multiple E1/T1 MTIE/TDEV (H2 2012)

14

Introducing ESMC
ESMC: Ethernet Synchronization Messaging Channel ESMC has been built first and foremost as the transport channel for SSM (QL) over Synchronous Ethernet links Key outcome: Simple and efficient ESMC does not aim to become a complex protocol However, in the future it may support some extensions It is not a control plane and does not need a control plane

15

G.8264 ESMC testing

Stimulus to EEC 1. ESMC = PRC Response from EEC 1.ESMC = PRC 2.Wander locked to Reference 1.ESMC changes to EEC1/2 2.Wander shows offset as EEC now locked to local clock 1.ESMC changes to PRC 2.Wander locked to reference
Synchronisation Source 10MHz, 2.048MHz, E1, T1

Clock with Freq offset

2. ESMC = DNU

3. ESMC = PRC
Wander Graph shows Line Clock Rate switching into and out of Holdover

Paragon GUI & TimeMonitor Port 2 Change QL of ESMC

Port 1

100M/1G SyncE (Wander free)

EEC

ESMC Graph shows ESMC messages changing state to reflect status

ESMC with EEC defined QL

16

Chapter 11

IEEE 1588v2 - PTP (Precision Timing Protocol)

Packet Sync Technologies

Separate packet flow used to transfer timing Timestamps embedded in packets to transfer timing Two-way protocol employed to measure delay between Master and Slave devices Able to transfer frequency (syntonisation) and phase/timeof-day (synchronisation) Standards define devices/techniques to reduce uncertainty (Peer-to-peer & End-to-end Transparent Clocks) and to create hierarchical clocking topology (Ordinary Clocks, Boundary Clocks)

Standards
IEEE: 1588v2; Precision Timing Protocol, PTP

IETF: RFC1305; Network Time Protocol, NTPv3, RFC5905: NTPv4 (TICTOC group) Deployed by Ericsson ITU-T: G.8264; Distribution of Timing through Packet Networks

IEEE 1588v2 (PTP)

Benefits: 1588v2 Standard ratified March 2008 Independent of services Suitable for layered/complex clock distribution topologies Compatible with currently deployed packet networks Drawbacks: Cost: Extra bandwidth required Protocol assumes symmetrical delays in up- and down-stream paths Sensitivity to PDV

IEEE1588 Network Sync - 1

Phase 1 - Establishes the Master-Slave hierarchy via the session protocol and a local state machine

Phase 1 - Session Management

Session Start-up
Master Clock Slave Clock

ce) quest Announ Signalling (Re Signalling (Ac knowledge)

quest Sync) Signalling (Re

Announce and Signaling messages configure and maintain the clocking structure - they include: Clocking Topology Grand Master identity and priority Timestamps Current UTC offset

Signalling (A cknow ledge )

p) quest Del_res Signalling (Re

Signalling (A cknowledge )

IEEE1588 Network Sync - 2

Phase 2 - Synchronises the clocks
Master Clock Slave Clock

1) Mean Progation Delay Tmpd = (T2 T1) (T4 T3) 2 2) Clock offset correction Offset = T2 T1 tmpd *simple model 3) Slave Clock Synchronisation *Calculation differs by vendor

Phase 2 Slave Clock Sync

Propagation Delay Message Exchange
Master Clock Slave Clock

t1 t-ms Sync t2 Follow_Up t3 t-sm t4 Delay_Req

Clock Output must comply with the relevant ITU-T clock specification (MTIE & TDEV specification) G.81x series of specifications (G.823/4 for TDM delivery)

Delay_Resp

Time Transfer Example

Assume at an instant in time: Master clock value = 100 seconds Slave clock value = 150 seconds (the slave clock error = 50 seconds) One way path delay = 2 seconds Sync message is sent at t = 100 seconds t1
sync (t 2s 1)

Master Clock

Slave Clock

Data At Slave Clock

For illustration, Delay_Req is sent 5 seconds after the Sync message is received: t2 t1 = 100 seconds t2 = 152 seconds (150+2) t3 = 157 seconds (152+5) Round Trip Delay RTD = (t2 - t1) + (t4 - t3) RTD = (152 - 100) + (109 - 157) RTD = 4 seconds Slave clock error eliminated Slave Clock Error = (t2 - t1) - (RTD 2) = (152 - 100) - (4 2) = 50 seconds Round trip error eliminated If the slave clock is adjusted by -50 seconds, the Master & Slave will be synchronized.

re delay_

t) q(ues

t3

t4
delay_ re sp(on s e) (t4 )

t4 = 109 seconds (100+2+2+5)

Influences on 1588v2 Accuracy

Packet Delay Variation (PDV) appears as a
change in frequency or phase of the recovered clock
Increases with number of network elements and traffic load Multiple causes, including queuing delays, routing changes, congestion, use of switches versus routers, etc.

Prolonged Packet Loss (Outage)

Causes clock recovery process to enter holdover

Slave Performance
Vendor A PDV tolerance X Vendor B PDV tolerance Y

Network asymmetry

Packet Delay, Packet Loss, and Packet Errors are not an issue for packet timing protocols

10

Todays test challenges (G.8261)

Building a ref. network/designing algorithms is timeconsuming and expensive Not repeatable (varying behaviour) and inconsistent (many different implementations) Does it truly represent YOUR network?

11

1588v2 Slave (Ordinary Clock)

In a network with legacy routers, PDV and Asymmetry accumulation (in each direction) can be significant Slave clock recovery is a challenge
PDV Accumulation

Master Clock

Router

Router

Router

Router

Slave Clock

12

Testing 1588v2 Ordinary Clocks

Testing 1588v2 Ordinary Clocks involves applying PDV and testing the recovered Slave clock
Connect equipment as shown Apply PDV profile Test recovered clock to ITU-T limits

13

G.8261 Appendix VI
Slave Clock (Frequency) Test (Old)

Apply G.8261 or Network Profiles, Measure E1/T1 MTIE/TDEV (now) Stress multiple slaves with G.8261 or Network Profile (H1 2012) Stress multiple slaves with multiple profiles (H2 2012)

14

G.8263
Slave Clock (Frequency) Test (New)

Apply G.8263 Profile, Measure E1/T1 MTIE/TDEV (now) Apply G.8263 Profile to multiple slaves, Measure E1/T1 MTIE/TDEV (H1 2012) Apply G.8263 Profile to multiple slaves, Measure multiple E1/T1 MTIE/TDEV (H2 2012)

15

Chapter 12

Boundary and Transparent Clocks

Boundary Clocks
Boundary Clocks reduce PDV accumulation by: Terminating the PTP flow and recovering the reference timing Generating a new PTP flow using the local time reference, (locked to the recovered time) There is no direct transfer of PDV from input to output A Boundary Clock is in effect a back-to-back Slave+Master

Q1

Clock

Q2

Master

Slave

Qn

1588v2 with Boundary Clocks

BCs recover and re-generate the 1588v2 clocking With a network of BCs, PDV contribution (per hop) is only from BC and link PDV experienced by Slave is minimised
PDV PDV PDV PDV PDV

Master Clock

BC

BC

BC

BC

Slave Clock

Boundary Clocks - Specifications

The ITU-T are working on a performance specification,

to appear in G.8273.2
Considered performance areas: 1) Frequency/Time Accuracy 2) Noise Generation 3) Noise Tolerance 4) Noise Transfer 5) Phase Response 6) Holdover

Boundary Clocks - G.8273.2

Conformance Testing - Wander
~ ~

Master Clock Master Clock

Slave Clock

Master Clock Master Clock

Slave Clock

BC
Master Clock

BC

Frequency Accuracy Noise generation Noise tolerance Noise transfer

Phase transient response Holdover

Transparent Clocks
Transparent Clocks reduce PDV by: Calculating the time a PTP packet resides in the TC device (in nsec) and inserting the value into the CorrectionField Using the CorrectionField, the Slave or terminating BC can effectively remove the PDV introduced by the TC
Q2 Qn

Q1

Packet Delay in TC Device inserted into correctionField at output of Transparent Clock device

1588v2 with Transparent Clocks

PDV Accumulation

Master Clock

TC

TC

TC

TC

Slave Clock

PDV is written by each TC into CorrectionField and this accumulates, so CorrectionField = PDV Accumulation at the End Slave

End Slave removes PDV Accumulation using CorrectionField

Transparent Clocks - Specifications

Performance specifications will be given in ITU-T G.8273.3 IEEE C.37.238 specifies less than 50ns error for a TC. The performance of a TC is essentially the accuracy of the CorrectionField This accuracy must be tested in the presence of traffic for forward path (Sync) and return path (Del-req).
(Note 1-step and 2-step methods differ in the location of the CorrectionField)

Tests should be done with varying congestion traffic: Packet size, traffic priority and utilisation

Transparent Clock Test Plan

CorrectionField Accuracy
~
Master Master `1` Clock Slave `1` Clock

Connect as shown, and broadcast Traffic Generator traffic on all ports of the TC 1. Capture PDV before and after TC, with CorrectionField 2. Perform differential calculation of PDV - Confirm CorrectionField error is <50ns 3. Repeat under multiple traffic conditions:
1. Vary traffic packet size 2. Vary traffic priority 3. Vary traffic utilisation

TC

Traffic Generator

Test Procedure to measure accuracy of CorrectionField

Packet /Traffic Generator Errors

~
e.g. GPS

TC
Traffic Generator

Claim: Emulating Master and Slave can verify CorrectionField accuracy

TC has 50ns error limit (e.g. IEEE C.37.238) TC test equipment must have better accuracy Meeting the ns challenge Even synchronised to GPS, hardware architecture of traffic generators has 10s/100s of ns error. So these are not fit for purpose Paragon is accurate to 5ns and fit for purpose.

10

The 1s Challenge
An increasing number of applications require accurate transfer of frequency and time through Ethernet networks:
TDD base stations
need phase synchronisation to 1s accuracy

High Frequency Trading (HFT)

needs 1s timestamp resolution

Power Substations
specify a maximum time variation through a system of 1s

For Mobile Backhaul

frequency accuracy must be better than 16ppb

11

Test Boundary/Transparent Clocks

Confirming 1s accuracy
The 1s inaccuracy limit is for a network as a whole but each network element plays a part Standards bodies are creating performance specs for BCs and TCs Errors in a BC or TC can only be a fraction of 1s
Standards (e.g. IEEE C.37.238) propose 50ns limits

Test equipment must be accurate to ns

Traffic Generators/Packet Capture Platforms have 10s if not 100s of ns error

12

Network Conditions in the Lab

Capture PDV profiles from live or trial networks . . .
. . . then replay the real-world PDV profiles back in your lab.

MKR-1:x=894.874691063, y=0.000360070 MKR-2:x=894.874691063, y=0.000360070 0.000645879

Delta: x=0.000000000, y=0.000000000

x=895.477518835 y=0.000444870

TDM-o-Ethernet Base Station

Time Interval Erro r (TIE) vs Nominal (seconds)

Core Network

-0.000296349 894.478017335

894.977768110 T (a)

895.477518885 Offset=0.002 pp m

TDM

. . . additionally: Record and replay from G.8261 Reference Network (Removes repeatability issues and minimizes resource effort.) Use PDVs from a library of profiles (including G.8261, MEF-18) Generate pseudo-real world profiles (edit real-world profiles to test margins of operation and clock recovery) Generate theoretical models (Gamma or Gaussian PDV distributions)

13

Chapter 13

Clock Measurements

Clock Performance measurements

Tie Interval Error (TIE)

TIE (sec)

Maximum Time Int Error (MTIE)

Time Deviation (TDEV)

10

100

1000

10000

100000

Modified Allen Deviation (MDEV)

G.8271.1 N'twk PDV Time/Phase

1588v2 GPS

1588v2 Slave

Network

1pps ToD Accuracy

1588v2 Master

pktfilteredMTIE

LAB

NETWORK

Lab Network

G.8271.1 profiles stress Slave, 1pps and ToD accuracy measured Measure Network PDV pktfilteredMTIE to G.8271.1/G.8260 (available on ratification of G.8271.1)

G.8273.2 Boundary Clock Test

GPS

Ref Ref 1588v2 + PDV + Traffic 1pps ToD 1pps ToD 1588v2 + PDV + Traffic

BC

1588v2

BC

Frequency+Time Accuracy Pull-in, Pull-out, Hold-in Noise generation Noise tolerance Noise transfer Phase transient response

G.8273.3 Transparent Clock Test

GPS

Ref

TC 1588v2 + PDV + Traffic

1588v2 + PDV + Traffic

Measure Latency vs Correction Field

Chapter 14

CALNEX Testing

Testing E1/2.048MHz
PRC Node-B

E1 Clock out

MTIE/TDEV against G.823 PDH Interface masks

Testing 10MHz
PRC Node-B

10MHz Clock out

Calnex Freq Converter

MTIE/TDEV against G.823 PDH Interface masks

Testing Sync-E
PRC Node B

MTIE/TDEV against G.8261 Opt1 mask

Testing 1588v2
Delay Distribution 1588v2 Protocol Analysis 1588v2 Forward PDV

GPS
1588v2 Reverse PDV

Node-B

1588v2 Master (RNC)

1588v2 pktMTIE (future)

How to measure Forward PDV

Master Clock

Slave Clock
MKR-1:x=894.874691063, y=0.000360070 MKR-2:x=894.874691063, y=0.000360070 0.000645879 Delta: x=0.000000000, y=0.000000000 x=895.477518835 y=0.000444870

t1 Sync t-ms t2 Follow_Up t3 t-sm t4 Delay_Req Delay_Resp

-0.000296349 894.478017335 Time Interval Erro r (TIE) vs Nominal (seconds)

894.977768110 T (a)

895.477518885 Offset=0.002 pp m

Sync PDV
Paragon uses timestamp from Sync message to calculate Sync PDV Sync PDV = variation of (arrival time at Paragon timestamp)
Does Master > Slave PDV impact clock recovery?

Propagation Delay Message Exchange

How to measure Reverse PDV

Master Clock

Slave Clock
MKR-1:x=894.874691063, y=0.000360070 MKR-2:x=894.874691063, y=0.000360070 0.000645879 Delta: x=0.000000000, y=0.000000000 x=895.477518835 y=0.000444870

t1 Sync t-ms t2 Follow_Up t3 t-sm t4 Delay_Req Delay_Resp

-0.000296349 894.478017335 Time Interval Erro r (TIE) vs Nominal (seconds)

894.977768110 T (a)

895.477518885 Offset=0.002 pp m

Delay_Req PDV
Measure variation between the launch time of the Delay_Req message (arrival time of Del_Req in Paragon) and the embedded timestamp, t4, in the corresponding Delay_Resp message
Does Slave > Master PDV impact clock recovery?

Propagation Delay Message Exchange

Simultaneous Measurements
Delay Distribution 1588v2 Protocol Analysis 1588v2 Forward PDV

GPS

1588v2 Protocol Analysis

1588v2 Reverse PDV

Node-B

1588v2 Forward PDV 1588v2 Reverse PDV Delay Distribution

Sync-E MTIE / TDEV E1/T1 MTIE / TDEV

E1/T1 MTIE / TDEV 1pps ToD Accuracy Sync-E MTIE / TDEV

Hybrid 1588v2 Master and Sync-E EEC

1pps ToD Accuracy

ESMC Monitor / Overwrite

ESMC Monitor / Overwrite

ALL AT THE SAME TIME!

Calnex Products

Paragon
Lab & Field up to 1G 1588v2, SyncE, CES, NTP, OAM

Paragon-X
Lab & Field up to 10G 1588v2, SyncE, CES, NTP, OAM E1/T1 and 1pps

Paragon-m
Field up to 1G 1588v2, SyncE, CES, NTP, OAM E1/T1 and 1pps

Portable GPS Rubidium reference

Provides stable frequency (10MHz) and 1pps reference in the field GPS Antenna and cables included