Semiconductor Memories

Overview
Memory Classification Memory Architectures The Memory Core

MEMORIES
Memory circuits provide the means of storing
information (data) on a temporary or permanent basis and for future recalls.

Magnetic memory generally is capable of storing

large amount of data at very low cost, but the access time (the time it takes to locate and then read or write) is usually very long.

Semiconductor memories use electrical signals to

identify memory location and its content. The access time in several orders of magnitude faster that magnetic memory.

MEMORIES
MOS and bipolar technologies can be used to
implement various types of semiconductor memories.

Semiconductor memories are usually classified into

two major types: volatile, or non-volatile.

Volatile memories (SRAM, DRAM) loose their data

once the power supply is turned off.

Non-volatile memories (ROM, EPROM) on the other

hand can retain their data even after power is removed.

Types of memories

Semiconductor Memory Classification

Read-Write Memory Volatile Random Access Non-Random Access FIFO LIFO Shift Register CAM Read-Write Memory Non-Volatile EPROM E2PROM FLASH Read-Only Memory Non-Volatile

Mask-Programmed Programmable (PROM)

SRAM DRAM

Memory Timing: Definitions

Read cycle

READ
Read access Read access Write cycle

WRITE
Write access Data valid

DATA

Data written

Memory Architecture: Decoders

M bits S0 S1 S2
Word 0 Word 2 Storage cell

M bits S0
Word 0 Word 1 Word 2 Storage cell

N
words

A1 AK-1

SN-2 SN-1

Word N-2 Word N-1

Decoder

Word 1

A0

Word N-2 Word N-1

K = log2N
Input-Output (M bits) Intuitive architecture for N x M memory Too many select signals: N words == N select signals Input-Output (M bits) Decoder reduces the number of select signals

Array-Structured Memory Architecture

2L 2 K
Row Decoder

Bit line

Storage cell

AK A K1 1 AL2 1

Word line

M. 2K
Sense amplifiers / Drivers
Amplify swing to rail-to-rail amplitude Clock-signals, R/W control Selects appropriate word

A0 A K2 1

Column decoder

Input-Output ( M bits)

Hierarchical Memory Architecture

Block 0 Row address Column address Block address Block i Block P 2 1

Global data bus Control circuitry Block selector Global amplifier/driver I/O

Advantages: 1. Shorter wires within blocks 2. Block address activates only 1 block => power savings

Static RAM (SRAM)

Random Access Memory (RAM) is a readable and
write-able volatile memory.

The term random access means that the user can

access any location of the entire memory and in any order.

RAM is further divided into static RAM (SRAM) and

dynamic RAM (DRAM).

Static RAM is a simple latch circuit (flip-flop) that

remembers its state until it is toggled.

Static RAM (SRAM)

The simplest SRAM would be a simple data latch

with pass transistors for selection and isolation.

The actual implementation is usually carried out by

the 6-transistor cell.

6-transistor SRAM Cell

WL M2 M5 !Q M1 M3 M4 Q

M6

!BL

BL

Consumes power only when switching - no standby power (other than leakage) is consumed. The major job of the pull-ups is to replenish loss due to leakage. Sizing of the transistors is critical

Static RAM (SRAM)

Static RAM (SRAM)

Static RAM (SRAM)

Static RAM (SRAM)

Memory Array

Memory Array

Dynamic RAM (DRAM)

DRAMs are fabricated using MOS technology and are

noted for their high capacity, low power requirement, and moderate operating speed (when compared to SRAM).

DRAMs make use of MOS capacitors to store the data

as electronic charges. The capacitors can be switched in and out of the bit lines via a pass transistor.

The storage capacitor will loose its charge over time.

Therefore, DRAMs must be refreshed in a regular basis.

Dynamic Memory Cell

Typical storage capacitance has a value of 20 to 50 fF.

V = 2.5V, leakage current is I = 40pA, C = 20fF then the time to discharge the capacitor to the half of the initial voltage can be estimated as:

Dynamic RAM (DRAM)

The most important difference of the DRAM fabrication

process from other technology is the storage capacitor.

The single-transistor DRAM cell requires a capacitor

that can store sufficient charge to allow the cell state to state true between refresh cycles.

The most significant development in the DRAM

devices has been the advance in the capacitor design.

The DRAM capacitors have been improved in two

ways: increasing the surface area and increasing the capacitor dielectric constant.

Dynamic RAM (DRAM)

Dynamic RAM (DRAM)

3-Transistor DRAM Cell

WWL RWL M3 M1 Cs BL1 BL2 BL2 Vdd-Vt X M2 WWL BL1 X RWL Vdd-Vt read write Vdd

No constraints on device sizes (ratio less). Reads are non-destructive. Value stored at node X when writing a 1 is VWWL - Vtn

Core of first popular MOS memories (e.g., first 1Kbit memory from Intel). Cs is data storage (internal capacitance of wiring, M2 gate, and M1 diffusion capacitances). Note threshold drop at point X which decreases the drive Write uses WWL and BL1. Read uses RWL and BL2. Assume BL2 pre-charged to Vdd (or Vdd-Vt). If cell is holding 1, then BL2 goes low so reads are inverting. Refresh read stored data, put its inverse on BL1 and assert WWL (need to do this every 1 to 4 msec)

1-Transistor DRAM Cell

WL WL M1 CBL Cs X X Vdd-Vt write 1 read 1

BL

BL Vdd/2

Vdd sensing

Write: Cs is charged (or discharged) by asserting WL and BL Read: Charge redistribution occurs between CBL and Cs, Read is destructive, must be refreshed
Most pervasive DRAM cell in commercial designs. Write set BL and activate WL. Could bootstrap WL so that voltage drop at X doesnt occur (to bring it up to Vdd) common practice. Read - BL precharged to Vpre typically Vdd/2 then assert WL and sense state of BL that takes effect due to charge sharing between CBL and Cs. Note that Read is destructive (steal charge from Cs) so must follow with a refresh cycle. Note that Cs << CBL (1 to 2 orders of magnitude) so read voltage swings are typically very small (around 250mV for 0.8 micron technology?). REQUIRES a sense amp for each bit line for correct operation

1-Transistor DRAM Cell

Trenched DRAM Cell One area of progress in making a capacitor with a larger surface area is to form the capacitor in a trench. This technique make use of a deep trench (> 7m into the silicon). It has the advantage of allowing the transistors to be formed nearly planar on the surface with the trench extending below the device active area.

1-Transistor DRAM Cell

Stacked DRAM Cell

Another area of tremendous progress in DRAM technology goes in the other direction and forms the capacitors in geometries that extend above the silicon to create a large capacitor area. The large surface areas can be created using a large planar capacitor shaped like a dome or a crown. These structures also take advantage of higherdielectricconstant materials for the inter-level dielectric for thecapacitors Ta2O5 (Ba, Sr)TiO3, etc.

DRAM Cell Observations

DRAM memory cells are single ended (complicates the design of the sense amp) 1T cell requires a sense amp for each bit line due to charge redistribution read 1T cell read is destructive; refresh must follow to restore data 1T cell requires an extra capacitor that must be explicitly included in the design A threshold voltage is lost when writing a 1 (can be circumvented by bootstrapping the word lines to a higher value than Vdd)

Read-Write Memories (RAMs)

Static SRAM data is stored as long as supply is applied large cells (6 fets/cell) so fewer bits/chip fast so used where speed is important (e.g., caches) differential outputs (output BL and !BL) use sense amps for performance compatible with CMOS technology Dynamic DRAM periodic refresh required small cells (1 to 3 fets/cell) so more bits/chip slower so used for main memories single ended output (output BL only) need sense amps for correct operation not typically compatible with CMOS technology

Read Only Memory (ROM)

Certain applications may require the memory to hold
data that are either permanent or will not be changed frequently.

In this case, nonvolatile memory is the candidate. As the name implies, Read Only Memory (ROM) has no
provision to write or update its memory contents.

The programming is usually done during the

manufacturing process or by a burning procedure prior to field use.

Read Only Memory (ROM)

ROMs can be considered as lookup tables where an
address code input will produce a certain data at the output.

The internal organization of ROM chips are similar to

the SRAM and DRAM except that no input data buffers are neccessary.

ROMs can be programmed by photo masks that

determine the connections in an array

Read Only Memory (ROM)

One obvious disadvantage of the mask ROM is the fact that a new
photomask must be prepared if the stored data is to be changed.

This will also be accompanied by a sizable turn-around time when

manufacturing the new ROMs.

An alternate method of implementing the ROM is with a

programmable technology such as fuse or anti-fuse.

In this case, the ROM becomes a programmable parts, hence the

name PROM.

One advantage of the PROM is the fact that all ROMs,

regardless of data content can be manufactured using the same set of photomask and fabrication procedures.

Read Only Memory (ROM)

However, a one-time-only programming procedure
must be applied prior to field use. After the PROM is programmed, its contents cannot be changed anymore.

Read Only Memory (ROM)

Read Only Memory (ROM)

Read Only Memory (ROM)

Read-Only Memory Cells

BL VDD WL WL WL BL BL

BL WL WL

BL

BL WL

0
GND Diode ROM MOS ROM 1 MOS ROM 2

MOS NOR ROM

V DD Pull-up devices

WL[0]
GND WL [1]

WL [2] GND WL [3]

BL [0]

BL [1]

BL [2]

BL [3]

MOS NAND ROM

V DD Pull-up devices BL [0] WL [0] BL[1] BL[2] BL[3]

WL [1]

WL [2]

WL [3]

All word lines high by default with exception of selected row

Precharged MOS NOR ROM

f
pre

V DD Precharge devices

WL [0] GND WL [1]

WL [2] GND WL [3]

BL [0]

BL [1]

BL [2]

BL [3]

PMOS precharge device can be made as large as necessary, but clock driver becomes harder to design.

Conventional Flash E2PROM cell

Structures Similar to an ordinary MOSFET except for an extra gate buried in the silicon dioxide.

Charges are stored in the floating gate to alter the

threshold voltage of the E2PROM cell

Simple construction and fabrication steps Very high packing density Flash E2PROM and E2PROMs share the same
technology

Non-Volatile Memories The Floating-gate transistor (FAMOS)

Floating gate Source

Gate Drain tox tox G

n+ Substrate

n+_

Device cross-section

Schematic symbol

Cross-sections of NVM cells

Flash

EPROM

Floating-Gate Transistor Programming

20 V 0V 5V

10 V 5 V 20 V S D S

2 5V

0V

2 2.5 V S

5V

Avalanche injection

Removing programming voltage leaves charge trapped

Programming results in higher V T .

For programming, hot electrons are created by the large drain bias current. These electron tunnels through the thin gate oxide and become trapped in the floating gate.

FLOTOX EEPROM
floating gate tunneling oxide
Floating gate Source 2030 nm n1 n1 10 nm Gate Drain -10 V 10 V Substrate p V GD I

FLOTOX transistor

Fowler-Nordheim I-V characteristic

For erasing, the stored electrons are removed by Fowler Nordheim (FN) tunneling from the floating gate to the substrate and the source

Flash EEPROM

Control gate
Floating gate

erasure n1 source

Thin tunneling oxide

programming psubstrate

n1 drain

Many other options

Flash memories based on EPROM or EEPROM technologies are devices for which contents of all memory array cells can be erased simultaneously

Flash EEPROM
For programming, hot electrons are created by the large drain bias current. These electron tunnels through the thin gate oxide and become trapped in the floating gate.

For erasing, the stored electrons are removed by Fowler Nordheim (FN) tunneling from the floating gate to the substrate and the source.

Characteristics of State-of-the-art NVM

Limitations of Existing Flash E2PROM Cells

Most require high drain bias voltage (VD > 5V) to generate hot electrons for programming. Not directly scalable to shorter channel length. Not suitable for low voltage applications.

Require high drain current (IDS @ 1mA) during programming. Require

large charge pump circuits and limits the number of cells that can be programmed at once.

Suffers from slow programming speed (a few s). Not suitable to

replace RAM and electronic hard drives. Most cells suffer from hole trapping in the thin gate oxide during erasing. Reduction in VTH window after several cycles of erase and programming.

Read-Write Memories (RAM)

STATIC (SRAM)
Data stored as long as supply is applied Large (6 transistors/cell) Fast Differential

DYNAMIC (DRAM)
Periodic refresh required Small (1-3 transistors/cell) Slower Single Ended

SRAM Characteristics

3-Transistor DRAM Cell

BL 1 WWL RWL M3 M1 CS X M2 BL 2

Area reduction Reads are non-destructive Value stored at node X when writing a 1 = V WWL-VTn

1-Transistor DRAM Cell

BL WL WL M1 CS BL V DD /2 CBL V DD V /2 sensing DD X GND V DD 2 V T
Write 1 Read 1

Write: C S is charged or discharged by asserting WL and BL. Read: Charge redistribution takes places between bit line and storage capacitance
V = CS (V V PRE ) -----------BIT C S + CBL

Voltage swing is small; typically around 250 mV.

DRAM Cell Observations

DRAM memory cells are single ended in contrast to SRAM cells. The read-out of the 1T DRAM cell is destructive; read and refresh operations are necessary for correct operation. Unlike 3T cell, 1T cell requires presence of an extra capacitance that must be explicitly included in the design. When writing a 1 into a DRAM cell, a threshold voltage is lost. This charge loss can be circumvented by bootstrapping the word lines to a higher value than VDD

Advanced 1T DRAM Cells

Word line Insulating Layer Cell plate Capacitor dielectric layer

Cell Plate Si

Capacitor Insulator

Refilling Poly

Transfer gate

Isolation Storage electrode

Storage Node Poly Si Substrate 2nd Field Oxide

Trench Cell

Stacked-capacitor Cell

Sense Amplifiers

Differential Sense Amplifier

VDD M3 M4 y bit M1 M2 bit Out

SE

M5

Directly applicable to SRAMs

Differential Sensing SRAM

V DD PC V DD BL EQ WL i BL y M3 x M1 SE M2 M5

V DD M4
2 x

V DD
2 y

x SE

2 x

SE
SRAM cell i Diff. x Sense 2 x Amp

V DD y SE Output

Output
(a) SRAM sensing scheme (b) two stage differential amplifier

Latch-Based Sense Amplifier (DRAM)

EQ BL VDD SE BL

Little voltage changes should result in a rapid production of a large voltage at the output

SE

Initialized in its meta-stable point with EQ During read, once adequate voltage gap created, sense amp enabled with SE Positive feedback quickly forces output to a stable operating point.

Memory Circuits
Semiconductor memories are comprised of a main
storage array surrounded by peripheral circuits for read and write operations.

These peripheral circuits includes row and column

address decoders, data buffers/registers, sense amplifiers, and charge pumps circuits.

The decoders and buffer/registers are basically digital

circuits and can be implemented using conventional VLSI design methodology.

The sense amplifier is basically a high gain circuit that

is used to differentiate the stored information with a reference voltage.

Memory Circuits
This is especially critical if the storage element is a DRAM cell.

Most memory arrays require separate high and low

voltage supply to operate.

In order to eliminate the need for multiple external

power supplies, more memory chips have built-in charge pump circuits to generate multiple voltage levels from a single supply (usually 5V or 3.3V).

Sense Amplifiers
One of the most difficult tasks in DRAM design is the
dynamic sense amplifier.

In a high density DRAM, the intrinsic differential

voltage across the sense amplifier can be in the order of 10s of mV.

The sense amplifier must detect and amplify this

small signal with reasonable speed.

On the other hand, since sense amplifiers are located

between bit-lines, the available layout area is also limited, making the design particularly challenging.

Uso de memorias como circuitos lgicos