Question Paper Computer System Architecture (MC121) January 2005

Section A : Basic Concepts (30 Marks)

1. This section consists of questions with serial number 1 - 30. Answer all questions. Each question carries one mark. Maximum time for answering Section A is 30 Minutes.
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The computer architecture having stored program is _____. (a) Harvard (d) Ada (b) Von-Neumann (e) Cobol. (b) SSI (e) Vacuum Tubes. (c) Pascal

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The key technology used in IV generation computers is _______. (a) MSI (d) Transistors (c) LSI &VLSI

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3.

x and y are two digit BCD numbers. It is known that x + y is equal to 82(BCD) and x - y is equal to 04(BCD). The value of x is _______. (a) 01000011 (b) 00001010 (b) 0110 (b) Carry (b) Full-Adder (c) 00101011 (c) 1101 (c) Parity (c) Half-Adder (b) 2s complement (d) 00100111 (d) 1111 (d) E (d) Adder (e) 00110010. The gray code of a given binary number 1001 is (a) 1110 (e) 0000. When the addition of two +ve numbers results in a ve value, then _______ flag will be set. (a) Over-flow (e) Sign. The digital circuit that generates the arithmetic sum of two binary numbers of any length is ________ . (a) Binary-Adder (e) OR-gate. Which of the following representation requires the least number of bits to store the number +255? (a) BCD (d) Unsigned binary (e) Signed binary. (c) 1s complement

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8.

The number of select input lines in an 8-to-1 multiplexer is ________. (a) 1 (b) 8 (c) 2 (b) (AB)+(CD) (e) (A+B)+(C+D). (d) 4 (e) 3. If F= AB + CD then F= _______. (a) (A+B)(C+D) (AB)(CD) (d) (A+B)(C+D) (a) Accumulator (d) CPU (c)

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10. Serial to parallel data conversion is done using (b) Shift Register (e) Control Unit. (b) Dont care (c) Data (d) Device (c) Counter

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11. What does D stand for in a D flip-flop? (a) Direct (e) Disk. 12. Which of the following is not an advantage of asynchronous circuits? (a) Higher speed (c) Smaller design effort (e) Simple functions. (a) X-OR gate (a) Dynamic RAM (b) AND gate (b) Low power consumption (d) No need to provide clock generation circuitry

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13. Carry in half-adder can be obtained using _______. (c) OR gate (b) Static RAM 1 (d) X-NOR gate (e) Inverter. 14. CACHE memory is implemented using ________. (c) EA

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RAM (d) ED RAM 15. CISC stands for ______________________. (a) (b) (c) (d) (e) Control Instruction Set Completeness Complex Instruction Set Conversion Complex Instruction Set Computer Control Instruction Set Conversion Complex Instruction Set Control.

(e) EP RAM.
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16. BUN instruction stands for_______ (a) Branch conditionally (c) Boot unconditionally (e) Branch and save return address. (b) Branch unconditionally (d) Begin unconditionally

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17. Information transfer from one register to another is designated in symbolic form by means of _________. (a) Control functions (d) Stack operation 18. DMA stands for__________________. (a) Direct Memory Address (c) Direct Memory Access (e) Device Memory Access. (a) { } (d) (a) Stack (e) (b) Direct Main Address (d) Direct Main Access (b) OP-Code (e) Replacement operator. (c) Registers

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19. ______ is a symbol to denote a part of a register. (b) ( ) (c) < >

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20. ________ structure is useful in the evaluation of postfix arithmetic expression. (b) Queue (c) Linked List (d) Graph (e) Tree. 21. When a large number of registers is included in the CPU, it is most efficient to connect them through a ______. (a) ALU (d) QUEUE (a) AC (b) Memory Register (c) STACK (e) Bus system.

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22. The register that keeps track of the address of next instruction to be executed is ______ . (b) PC (c) IR (d) AR (e) DR. 23. The correspondence between the main memory blocks and those in the cache is specified by _________. (a) Miss penalty (d) Page fault (a) Control unit (d) Logic unit 25. The set of physical addresses is called (a) Disk Space (d) Frames (a) Bus master (d) Bus request (a) Cycle stealing (d) Inter-leaving (b) Address Space (e) Location. (b) Bus arbitration (c) Bus cycle (e) Parallel bus. (c) Pages (b) Replacement algorithms (e) Mapping functions. (b) Arithmetic unit (e) Main memory. (c) Speaker (c) Hit rate

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24. Which one of the following can be called as a peripheral?

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26. The device that is allowed to initiate data transfer on the bus is called ___________.

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27. The DMA transfer technique where transfer of one word data at a time is called ______. (b) Memory stealing (e) Bus stealing. 2 (c) Hand-shaking

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28. ______ interface is used to connect the processor to I/O devices that require transmission of data one bit at a time. (a) Parallel (b) Serial (c) Output (b) Displacement (e) Indirect address. (b) Asynchronous (e) Indirect. (c) Serial (d) Input (e) Bus. 29. In based addressing mode, instruction contains ________. (a) Base address (d) Relative address (a) Synchronous (d) Parallel (c) Absolute address

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30. A hand-shake based protocol for data transfer is an example of ______ type of data transfer.

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END OF SECTION A

Section B : Problems (50 Marks)

1. a. This section consists of questions with serial number 1 5. Answer all questions. Marks are indicated against each question. Detailed workings should form part of your answer. Do not spend more than 110 - 120 minutes on Section B.

Convert the following pairs of decimal numbers to 5 bit 2s complement binary numbers and add them. State whether or not overflow occurs in each case. i. ii. iii. iv. v. 5 and 10 7 and 13 -14 and 11 -5 and -8 13 and 3.

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Represent the decimal values -10, 26, -2, 51 and -43 as signed 7 bit numbers in the following formats. i. Sign and magnitude (i.e. Binary format) ii. 9s complement. (5 + 5 = 10 marks) < Answer >

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a. b. a.

Simplify the following with the help of a K-Map. F (a, b, c, d) = (3, 5, 6, 7) + d (10, 11, 12, 13, 14, 15) in SOP form. Explain SR Latch with the help of a Logic Diagram (5 + 5 = 10 marks) < Answer > Convert the following numerical arithmetic expression into reverse polish notation and show the stack operations for evaluating the numerical result. (3 + 4) * (10 * (2 + 6) + 8) An instruction is started at location 300 with its address field at location 301. The address field has the value 400. A processor register R1 contains the number 200. Evaluate the effective address if the addressing mode of the instruction is i. ii. iii. iv. Direct. Immediate. Relative. Index with R1 as index register. (6 + 4 = 10 marks) < Answer >

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b.

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Explain the Instruction Cycle with the help of a flow chart. (10 marks) < Answer > Consider a state machine with 4 states S0, S1, S2 and S3. The machine has one input labeled X and output labeled Y. S0 is the initial state. The behavior of the state machine is shown below.

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Present State S0 S0 S1 S1 S2 S2 S3 S3

Input X 0 1 0 1 0 1 0 1
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Next State S0 S1 S1 S2 S2 S3 S3 S0

Output Y 0 0 0 0 0 0 0 1

Design the above state machine using JK flip-flops. Assume synchronous operation. (10 marks) < Answer > END OF SECTION B

Section C : Applied Theory (20 Marks)

This section consists of questions with serial number 6 - 7. Answer all questions. Marks are indicated against each question. Do not spend more than 25 -30 minutes on section C.

6.

Explain Virtual Memory with address mapping using pages. (10 marks) < Answer > Explain the DMA transfer with help of a diagram. (10 marks) < Answer >

7.

END OF SECTION C END OF QUESTION PAPER

Suggested Answers Computer System Architecture (MC121) January 2005

Section A : Basic Concepts
1. 2. Answer : (b) Reason : The first computer architecture having stored program is Von-Neumann Answer : (c) Reason : Large-scale integrated and very large-scale integrated circuits are used generation. Answer : (a) Reason : The x value is 01000011 Answer : (c) Reason : The gray code of 1001 is 1101 Answer : (a) Reason : Over flow flag will be set . Answer : (a) Reason : The binary adder is used to add binary numbers of any length Answer : (d) Reason : Unsigned binary representation occupies less space to store the number +255. Answer : (e) Reason : If 2n data inputs lines are connected to a MUX then there will be n Selection lines. For 8-to -1 MUX 23 input lines and 3 selection lines are possible Answer : (d) 5 in the IV
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3. 4. 5. 6. 7. 8.

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Reason : The complement of AB +CD is ( A+B ) ( C+D ) 10. 11. 12. 13. 14. 15. 16. 17. Answer : (b) Reason : Shift registers are used for serial to parallel data. Conversion. Answer : (c) Reason : In a D flip-flop D stands Data.. Answer : (c) Reason : Smaller Design effort is not an advantage of asynchronous circuits. Answer : (b) Reason : AND gate is used to obtain the carry in the half-adder circuit. Answer : (a) Reason : Using Dynamic RAM CACHE memory is implemented. Answer : (c) Reason : CISC stands for Complex Instruction Set Computer Answer : (b) Reason : BUN means Branch Unconditionally.) Answer : (e) Reason : A replacement operator consist of the information transfer from one register to another is designated in symbolic form Answer : (c) Reason : DMA stands for Direct Memory Access Answer : (b) Reason : The part of the register is denoted with () Answer : (a) Reason : Data structure stack is used in evaluating the post-fix expression. Answer : (a) Reason : All registers in a CPU are connected through ALU.. Answer : (b) Reason : Program Counter contains the address of the next instruction to be executed.. Answer : (e) Reason : The corresponding between the main memory blocks and those in the cache is specified by a mapping function, because the basic characteristic of cache memory is fast access time. Therefore, very little or no time must be wasted when searching for words in the cache. Answer : (c) Reason : Speakers can be called as a peripheral as all others are part of the system. Answer : (b) Reason : The collection of address spaces in a physical memory is called address space. Answer : (a) Reason : The Bus master is allowed to initiate data transfer on the bus. Answer : (a) Reason : Transfer of one word data at a time using DMA transfer technique is called Cycle Stealing. Answer : (b) Reason : Serial interface transfers one bit at a time, whereas others can handle more than one bit. Answer : (b) Reason : In a based addressing mode the displacement is the address field. Answer : (b) Reason : Asynchronous data transfer 6
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18. 19. 20. 21. 22. 23.

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24. 25. 26. 27. 28. 29. 30.

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Section B : Problems MC121

1. a. 1) Number 5 10 Binary rep. 00101 01010 1s complement 11010 10101 Add No over flows occurs 2) 7 13 00111 01101 11000 10010 Add Overflow occurs 3) 14 11 01110 01011 10001 10100 Add Overflow occurs 4) 5 8 00101 01000 11010 10111 Add No overflow occurs 5) 13 3 01101 00011 10010 11100 Add No overflow occurs b. i) 10 26 2 51 43 11001010 0011010 1000010 0110011 1101011 10011 11101 11101 11000 10010 10101 11001 10011 2s complement 11011 10110

1 10001

1 01100

1 00111

1 00111

1 10000

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2.

a.

Simplify the following with the help of a K-Map. F(a,b,c,d)=(3,5,6,7)+d(10,11,12,13,14,15) in SOP form. 00 00 01 11 10 0 4 12 8 01 1 5 13 9 11 3 7 15 11 10 2 6 14 10

00 00 01 11 10 0 0 x 0

01 0 1 x 0

11 1 1 x x

10 0 1 x x

ABCD+ABCD+ABCD+ABCD=ACD+ACD=CD ABCD+ABCD+ABCD+ABCD=ABD+ABD=BD ABCD+ABCD+ABCD+ABCD=ABC+ABC=BC F=CD+BD+BC in Sum of Products form ( 3marks) Explain SR Latch with the help of a Logic Diagram? SR Latch

b.

S 1 0 0 0 1

R 0 0 1 0 1

Q 1 1 0 0 0

Q 0 0 1 1 0 Invalid
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3.

a.

Convert the following numerical arithmetic expression into reverse polish notation and show the stack operations for evaluating the numerical result. ( 3 + 4 ) * ( 10 * ( 2 + 6 ) + 8 ) Let X=(3+4)*(10*(2+6)+8) =(3+4)*(10 26+*+8) =(3+4)*(10 26+*8+) =(3 4+)*(10 26 +*8+) =3 4 + 10 26 +*8 + * is the reverse polish notation

b.

An instruction is started at location 300 with its address field at location 301. The address field has the value 400. A processor register R1 contains the number 200. Evaluate the effective address if the addressing mode of the instruction is i) Direct. ii) Immediate. iii) Relative. iv) Index with R1 as index register

1) 2) 3)

4)

Direct Addressing mode: Effective address = Address field of the instruction =400 Immediate Addressing Mode: Effective address cant be defined for an immediate instruction. Relative addressing Mode: Effective address = Contents of PC + Address field of the instruction. We know that PC is pointing to next i.e. PC=302. Thus effective address = 400+302=702 Index with R1 as Index register: Effective address= Contents of index register + address field. Here R1 is index register = 200 + 400 =600

instruction

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5. Present State A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 X 0 1 0 1 0 1 0 1 Next State A 0 0 0 1 1 1 1 0 B 0 1 1 0 0 1 1 0 JA 0 0 0 1 X X X X KA X X X X 0 0 0 1 JB 0 1 X X 0 1 X X KB X X 0 1 X X 0 1 Output Y 0 0 0 0 0 0 0 1

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X AB 00 01 11 10

X AB 00

0 X X

1 X X 1

X AB 00 01 11 10

1 1

X AB 00 01 11 10

1 X 1 1 X KB=X

1 X X JA=BX X X

01 11 10

X X

X X 1

KA=BX

JB=X

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Section C: Applied Theory

6. Give the programmer the illusion that the system has a very large memory, even though the computer actually has a relatively small main memory. Address Space(Logical) and Memory Space(Physical)

Address Mapping Memory Mapping Table Virtual Address (20 bits) -> Physical Address (15 bits)

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Address Space and Memory Space are each divided into fixed size group of words called blocks or pages 1K words group

Organization of memory Mapping Table in a paged system

ASSOCIATIVE MEMORY PAGE TABLE Assume that Number of Blocks in memory = m Number of Pages in Virtual Address Space = n Page Table - Straight forward design -> n entry table in memory Inefficient storage space utilization <- n-m entries of the table is empty More efficient method is m-entry Page Table Page Table made of an Associative Memory m words; (Page Number:Block Number)

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Page Fault Page number cannot be found in the Page Table

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7.

Block of data transfer from high speed devices ,Drum, Disk, Tape * DMA controller - Interface which allows I/O transfer directly between Memory and Device Freeing CPU for other tasks * CPU initializes DMA Controller by sending memory address and the block size(number of words)

DMA I/0 OPERATION Starting an I/0 - CPU executes instruction to Load Memory Address Register Load Word Counter Load Function(Read or Write) to be performed Issue a GO command Upon receiving a GO Command DMA performs I/O operation as follows independently from CPU Input [1] Input Device <- R (Read control signal) [2] Buffer(DMA Controller) <- Input Byte; and 13

assembles the byte into a word until word is full [4] M <- memory address, W(Write control signal) [5] Address Reg <- Address Reg +1; WC(Word Counter) <- WC - 1 [6] If WC = 0, then Interrupt to acknowledge done, else go to [1] Output [1] M <- M Address, R M Address R <- M Address R + 1, WC <- WC - 1 [2] Disassemble the word [3] Buffer <- One byte; Output Device <- W, for all disassembled bytes [4] If WC = 0, then Interrupt to acknowledge done, else go to [1] CYCLE STEALING While DMA I/O takes place, CPU is also executing instructions DMA Controller and CPU both access Memory -> Memory Access Conflict Memory Bus Controller - Coordinating the activities of all devices requesting memory access - Priority System Memory accesses by CPU and DMA Controller are interwoven, with the top priority given to DMA Controller -> Cycle Stealing Cycle Steal - CPU is usually much faster than I/O(DMA), thus CPU uses the most of the memory cycles - DMA Controller steals the memory cycles fromCPU - For those stolen cycles, CPU remains idle - For those slow CPU, DMA Controller may steal most of the memory cycles which may cause CPU remain idle long time

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