Design and Microcontroller Implementation of a Three Phase SCR Power Converter

Richard W. Wall
Department of Electrical Engineering University of Idaho Boise, ID 83712

Herbert L. Hess
Department of Electrical Engineering University of Idaho Moscow, ID 83844

Abstract-A single processor controls a three phase silicon controlled rectifier (SCR) power converter. An inexpensive, dual optoisolator interface to the power line provides noise rejection and an improved measure of the zero crossing. A dynamic digital phaselocked loop (PLL) algorithm implemented in an Intel 87C196KD20 processor achieves frequency tracking, dynamically changing characteristics for improved performance. Dynamically modifying the PLL characteristics permits independent capture and locked dynamics. A feedforward method provides command tracking for improved response without loss of performance. This threecomponent design (processor, optoisolator, and SCR gate drivers) represents a minimal implementation with potential for closed loop voltage and current control. High speed input and output resources included on the 87C196KD processor make an efficient singledevice implementation possible. The processor is less than 1% utilized allowing for additional functions to be added in the future. This system operates on both 50 Hz and 60 Hz power systems without modification or loss of performance.

sophisticated controllers, such as digital signal processors[18, 21], neural networks[22], and other hardware have also been proposed. In this paper, the phase controlled topology, with its economical silicon controlled rectifiers, is retained and its control implemented through innovative analog and digital signal processing. Recently, advances in microcontroller technology have led to self-contained systems capable of performing much more than mere computation. Peripheral tasks so necessary to high speed, real time control can now be incorporated with a microprocessor onto a single controller chip. These include high speed data collection, analog-to-digital data conversion, timing (including sampling rates), multiplexing, and high speed output of digital data. Microcontrollers perform such high speed control functions plus microprocessor computation at reasonable cost and as an easily interfaced part of a larger control system.[12] In this paper, a microcontroller application to a phase controlled rectifier is reported. Optoisolators digitize the voltage polarity and the microcontroller digitizes the voltage zero crossing time using high speed inputs, mitigating some of the effect of line noise. On-board timers control sampling rates and delay times. Though interface signals to an outer loop may be the product of sophisticated control algorithms, they are intentionally kept simple in this particular investigation to keep the focus on the microcontrollers implementation of an all digital PLL and gate signal generator. The result is a low cost implementation of a three phase SCR power converter. II. HARDWARE REQUIREMENTS The general hardware requirements for this implementation are shown in Fig. 1. Since the 87C196KD-20 processor has sufficient internal Read-Only Memory (ROM) and Random Access Memory (RAM), no other digital electronics are necessary. The total cost for the electronic parts is less than $50! For prototype development, the power circuits are mounted on a separate PC board and connected to an MCS96 board via a 40 pin ribbon wire cable. (The MCS-96 board is one of the Intel evaluation boards for this family of microcontrollers.) The processor generates the digital signals for the gate drive circuit. A 386-based host PC development platform uses a serial interface to manage the MCS96 board with the ECM96 monitor software. A separate AC power supply is required for the MCS-96 board.

I. INTRODUCTION The Phase Controlled Rectifier, employing Silicon Controlled Rectifier (SCR) devices, is a reliable technology common to a host of electric machine drives, High Voltage Direct Current (HVDC) systems, and other power conversion systems. Though the rectifier has been employed for a very long time, it has been continuously improved.[1] For example, to solve a harmonic instability problem, in which firing instants determined directly from voltage zero crossings become susceptible to line noise, Ainsworth proposed using a Phase-Locked Loop.[2] Several improvements on his idea followed, including digital implementations of his algorithm[3-5] and sophisticated control and optimizing techniques.[6,7] Control of delay or extinction angles, current regulation, and other functions common to outer control loops became possible. Simple, reliable gate drives for interfacing logic to power devices enhanced the control of large amounts of power.[8] Soon microprocessor implementation of rectifier control [9,10] and of an entire HVDC system were proposed.[11] Much of the recent research has improved upon the less desirable aspects of a controlled rectifier, for example, its input current harmonic behavior[12], displacement factor[13], effects of dc ripple[14], its topology and commutation[15], minimizing its hardware[16], and optimizing its control[17] and losses[18]. Usually these improvements come through pulse width modulation (PWM) techniques and advanced power devices, such as the Insulated Gate Bipolar Transistor (IGBT).[13-15,17-21] Quite

The 87C196KD microcontroller is one of a family of processors which has on-chip resources that allow efficient phase-locked loop (PLL) implementation.[12] The two most critical resources for this design are high speed outputs (HSO) and high speed inputs (HSI). Output resources allow up to eight independent events to be scheduled based upon one of two timers with a maximum time resolution of 0.8 s for a 87C196KD operating at 20 MHz. These events include setting output pins high or low. High speed input allows the relative time of specific events on input pins to be captured. The time resolution is the same for output and input events. These two processor resources allow for a minimal implementation of a three phase power converter: high speed input and output capabilities are not generally available on lower performance microcontrollers.

LAY buttons simulate the commands normally generated by an outer control loop. Direct input of DELAY commands is possible but was not done for reasons relating to the environment in which the particular rectifier at hand will be placed. IV. PHASE DETECTION The first step in implementing a phase locked loop based control is to establish a reference phase for timing of the power devices gate pulses. In order to determine the phase of the input signal, it is necessary to repeatedly and reliably determine a fixed point on the sine wave. One of the more readily identifiable points is either the positive or negative zero crossing. The implementation used in this design identifies two points on the sine wave: the first just before the positive going zero crossing and the second just after the same zero crossing. Using two optoisolators, one can compensate for variations in level sensitivity and switching time delays. Constant frequency (60 Hz input) makes delays due to switching time indistinguishable from delays due to threshhold levels. The processor is programmed to capture the time of the internal 16 bit, 2.5 MHz clock at the rising edge of the Negative-On optoisolator output and at the falling edge of the Positive-On optoisolator output. The true zero crossing is computed by linear interpolation between the sampled Negative-On going high value and the sampled Positive-On going low value. Fig. 2 shows that this method results in an improved degree of accuracy. The Est. Zero shown in Fig. 2 is computed from the phase-locked loop algorithm that estimates the next zero crossing time. This algorithm is discussed in greater detail in Section VI.
6

S1 Phase A Phase B Phase C

S3

S5 Output Load

S4 H11L1QT Optoisolator

S6

S2

SCR Gate Drivers

High Speed Inputs

High Speed Outputs

i80C196KD uP
Decrease Delay Increase Delay RUN STOP Converter Power ON/OFF Indication

Fig. 1. Simplified schematic diagram for an i87C196KD controlled power converter.

Volts

4 2 0 -2 -4 -6

Negative On Est. Zero Positive On

III. DESCRIPTION OF I/O Two classes of inputs for this system are the real-time instrumentation and the user control interface. As shown in Fig. 1, the phase instrumentation hardware consists of two H11L1QT optoisolators connected to two of the processors input pins. The user control consists of three inputs: RUNSTOP, INCREASE DELAY, and DECREASE DELAY. These inputs are push buttons connected to the processor input/output (I/O) port 2 pins. Outputs generated by the microcontroller are for user display and real-time control. An LED indicator on a processor output pin shows when the program is operating in phase lock and generating pulses to the SCR gates. The signals used to control the SCR firing sequence are generated with six output pins, one for each SCR gate. The INCREASE DELAY or DECREASE DE-

Input Sine Signal -0.5 0

Time - ms

0.5

Fig. 2. Oscilloscope capture of the sine wave signal, optoisolator outputs and computed zero crossing.

Using optoisolators provides electrical isolation and signal conditioning. This method eliminates the need for signal transformers and comparators to convert the 60 Hz AC power signal to a suitable level and to provide a fast transition at the zero crossing.

V. PHASE FILTERING Most amplitude phase detection schemes, including thoes described above, are subject to errors from power system harmonics and random amplitude noise. Power system harmonics are the predominant cause of premature or delayed zero crossing detection. Random noise may also cause multiple zero crossings. The dual optoisolator method can effectively reject noise which generates multiple zero crossings by using only the times recorded for a negative transition of the Negative-On followed by a positive transition of the Positive-On signal. The SPICE model output shown in Figure 3 illustrates this operation for a 10 kHz signal superimposed on a 480 Volt RMS AC 60 Hertz signal. This algorithm, as discussed in greater detail in Section IV, will compute the zero crossing at 0.8325 ms, resulting in the computation of 63.15 Hertz to the most recent period. If the zero crossing is correctly determined for the next period, 57.14 Hertz will then be computed, correctly compensating but introducing an unacceptably large deviation between consecutive computations: Amplitude noise used for this illustration results in a 3.0 Hertz frequency measurement error. This requires further filtering as discussed in the following paragraph. Additional noise reduction is accomplished by Schmitt-triggered optoisolators which have TTL-compatible outputs. The method works well for a range of ac inputs but is most accurate for inputs lacking a phase shift between harmonics and fundamental and without dc offset. These conditions are common to every commericial power distribution system. This method takes advantage of such conditions.

Hertz cutoff results in 0.55 degrees phase lag at 60 Hertz. This is unacceptable, being considered large for the system at hand. Bandpass analog filtering can achieve zero degree phase shift but does so at only one frequency by delaying the input signal one or more integer cycles. Conventional systems use a phase-locked loop to track the small variations in frequency and identify the zero crossing for a phase reference.[2] This synchronous filtering technique is not frequency dependent due to its bandpass characteristics. Hence, it does not generate the phase lag and is therefore more effective than lowpass filtering for reducing measurement errors in the presence of harmonic distortion. Bandpass filtering using a phase-locked loop to further reduce sensitivity to the noise described above is dicsussed in Sections VI and VII. VI. SOFTWARE IMPLEMENTATION OF A PHASELOCKED LOOP The voltage controlled oscillator (VCO) is the weakest link in an analog or semi-analog phase-locked loop.[25] Changes of supply voltage and temperature affect the stability and operating performance of these phase-locked loop implementations. Both hardware and software all-digital phase-locked loop implementations are immune to these problems. Fig. 3 shows a block diagram of the phase-locked loop algorithm implemented in 80C196 assembler code. The output from this control loop is a predicted zero crossing, Tzcn, as computed from the last predicted zero crossing and a computed period, Pd. The measured zero crossing, Tzcm , is obtained from the input event algorithm described in IV. The zero crossing error, Tzce, is actually the phase error for the PLL.
Fixed period bias Pd 0 Period Error Pde Pdn Divide by 6 Pd/6n Filtered period outputs

6 Positive On 4

2 Volts

0 Negative On -2 Input signal

Measured zero crossing time Tcmn Tzcn

Lowpass Filter

Period adjust

Pdn

Tzcn+1 Predicted next zero crossing time

1/z

-4

Tzcn
-6 0 0.5 1 Time - ms 1.5 2

Fig. 4. Block diagram of a digital PLL implemented in processor code.

Fig 3. Optoisolator simulatedd outputs with 10% amplitude noise at 10 kHz. The input signal is scaled 1/40 for clarity.

Since the power system frequency is usually quite constant, fluctuating at most a tenth of a Hertz under normal operating conditions, bandpass filtering helps to further reduce sensitivity to noise. Analog filtering the 60 Hz input to reduce noise and harmonics generates a phase shift; for example, a second order RLC lowpass filter designed for 7.5

The output from the lowpass filter is an offset level which, when added to a fixed bias corresponding to a nominal period, Pd0, generates the synthesized signal with period, Pd. Adding a nominal fixed bias to the filter output is a feedforward technique to reduce the time required for initial capture and for capture after relatively large, rapid changes in nominal period. Nominal bias also reduces windup problems. These advantages are accomplished by reducing the offset level to which the integrating lowpass filter must ini-

tially ramp up. When lock is achieved, Pd is locked or synchronized to the input signal in both frequency and phase. The lowpass filter algorithm is arbitrary and may be tuned to meet control objectives as will be discussed below. Typically, the loop filter for an analog PLL is a first order lag-lead low pass filter with a transferfunction expressed by (1). Use of such a filter resuls in steady state error for a step input and may be warrented for some applications. Applications and effects of higher order loop filters are the subject of on-going investigations.[26] For this particular investigation, we have choosen a first order filter based upon a common proportional plus integral (PI) algorithm that has the continuous time Laplace transfer function as shown in (2).[5] The complexity of the loop filter algorithm is, in a sense, only limited by processor speed. Using a filter based upon the PI algorithm results in loop filter with a transfer function as expressed in (2). The discrete transfer function for the PI algorithm described by (3) is derived from (2) using the bilinear transformation. Although the theoretical steady state error for an analog PLL using a loop filter with a transfer functions expressed by (2) is zero, the discrete realization expressed by (3) can result in finite steady state errors due in part to the sampling speed. The demonstration system has a finite resolution of 0.0172 degrees based upon the 2.5 MHz sampling rate and 60 Hz nominal frequency. Using 16 bit integer math results in truncation error which contribute less significantly to the steady state errors..

on the unit circle and two poles which must lie inside the unit circle to insure PLL stability. Adjusting these poles can attenuate the the higher frequencies making the control loop less responsive to fast changes of the frequency of the input signal as well as making the filter more stable.
T zce = z 1 z2 + ( K a
p

2) z + ( K

+ 1)

(4)

2Ki = + K T

(5)

2K T

(6)

Experimentally, variations in control response are observed by monitoring the phase error, Tzce, as shown in Fig. 5. These plots agree well with simulation results for the filter types using MATLAB. The four cases are generated using the values of Ki and Kp shown in Table I with T set to 1/60 s. All four algorithms achieve zero steady state error for a step change of the frequency on the input signal thus confirming earlier observations about the PLL using PI algorithm for the loop filter. TABLE I. Chart of constants used in Fig. 5 simulations.
Type A B Ki 0.0025 0.0012 0.0006 0.00006 Kp 0.5 0.7555 0.8315 0.8925 Ka 0.8 0.9 0.9 0.9 Kb -0.2 -0.610 -0.763 -0.885

s+ H ( s) = K f s+

(1)

C D

H ( s) = K

i s
2 Ki + T
1 z 1 K p

(2)

H (z) =

2 Ki T

+ K p

1 z

Filter type "A"

(3)
Zero Crossing Error - Hz Filter type "B"

Although a PLL using the PI algorithm for the loop filter guarantees zero steady state error for a step input change, its dynamic behavior can be very different depending upon choices of integral gain, Ki , and the proportional gain, Kp. Since the sampling interval, T, is also the measured period, the value of T used in (3) will change depending upon the variance in system frequency. This is usually not a problem because the power system frequency normally changes less than a tenth of a Hertz and does so at a typical rate on the order of hundredths of a Hertz per second. The discrete transfer function expressed in (4) is for the phase error, Tzce. This transfer function uses the PI lowpass filter algorithm expressed by (3) while Ka and Kb are defined by Ki and Kp as shown in (5) and (6). (4) has a zero a =0

Filter type "C"

Filter type "D" 69 Hz 53 Hz -1 0 Signal Frequency 1 Time - seconds 2 3 4

Fig. 5. Four experimental dynamic responses of the phase-locked loop control system shown in Fig. 3 to a step change of input frequency of 69 to 53 Hz.

A filter with slightly underdamped characteristics similar to the Type B filter is used for the pre-lock lowpass filter to obtain phase lock quickly, within 0.5 seconds as demonstrated by the zero phase error. A similar filter to the Type D filter, with significantly overdamped characteristics, is used after phase lock because this filter rejects higher frequencies and has a high degree of momentum. Mathematically, a critically damped response can be achieved using Ka = 0.9 and Kb = -0.6975. As mentioned previously, the power system will vary by at most 0.1 Hertz from its 60 Hertz nominal value and these variations occur at a rate of hundredths of Hertz per second or slower. The noise spectrum is known to exist at somewhat higher frequencies. Therefore, a filter of the Type D nature, designed for its slow response, rejects the noise while retaining sufficient bandwidth to effectively track the desired system frequency. (The feedforward aspect of the control loop provides a wide bandwidth for the commanded period, overcoming what may appear as a very sluggish control loop response. Feedforward also overcomes windup problems.) In other words, this algorithm takes advantage of known system behavior in applying appropriate filtering. Hence, frequency measurement noise such as that illustrated in Fig. 3 does little to change the computed locked period. The mechanism to achieve the dynamic filter is discussed in Section VII. An important observation from Table I and Figure 5 is that lower integral gains result in a slower responding system. When choosing the PI algorithm constants or even the order of the lowpass filter algorithm, one must consider the performance criteria for a given application. This is beyond the scope of this discussion. The reader is referred to [6] for additional information. The processing power of the 87C196KD-20 allows implementation of high order lowpass filter algorithms or limited change-rate algorithms. VII. PHASE LOCK DETECTOR When the PLL control system in Fig. 4 has obtained lock, the Phase error, Tzce, is nominally zero. A lock detector is implemented which tracks the sum of squares of the Tzce over a finite length window of past values as expressed by (7). From experimentation, the sum squared term, S2, for a window of 20, is less than 1000 when the system has achieved phase lock. The pulse generation for the SCR gates is inhibited unless operating in phase lock. The processor code to implement thic control will be discussed in greater detail in Section IX.

after becoming locked. During operations, if the lock detection algorithm indicates a loss of lock, the phase-locked loop is switched back to the fast response filter algorithm until lock is acquired again. VIII. OUTPUT CONTROL Fig. 6 illustrates the feedforward method to determine the SCR gate firing times. The closed-loop portion of Fig. 6 is described by (8) and the open-loop portion by (9). Initially, the zero phase reference, Tref, is set to zero phase, Tzcn, shown in Fig. 4. Tref updates after a delay equal to six times Pd/6 plus the delay control variable TD. Tref updates using the most recent value of Pd computed in the PLL. Hence Tref and Tzcn are both phase-locked to the input signal but are not necessarily equal: The update timing of Tref depends upon the delay control whereas Tzcn depends upon the PLL input signal. The locked period, Pd, computed in the PLL contains the disturbance rejection information. To obtain command tracking as a separate matter, the firing times are computed according to (9). The variable, K, serves as the HSO output pin sequence table pointer as well as the multiplier for Pd/6 in (9). K is incremented each Pd/6 period from zero to five.

T ref

n +1

= T ref

+ Pd n

(8) (9)
T 3 HSO
Pd/6

Pd THSO = T +K +T ref D 6 K n
TD Pd
1/z Trefn

T 1 HSO

T 2 HSO

T 4 HSO
Pd/6

T 5 HSO
Pd/6

T 6 HSO
Pd/6

Pd/6

Fig. 6. Control diagram for SCR firing timing.

IX. PROCESSOR SOFTWARE The 87C196KD processor operates in one of three routines: A main routine containing the processor default code and two real-time interrupts routines shown in Fig. 7 and Fig. 8. Upon power up, the code begins execution by setting all initial conditions and allocating the various microprocessor resources for this particular application.

S =
2

i=n k

( Tzce )
i

i=n

(7)

The lock detection circuit is also used to adjust the parameters of the PI loop switching from a fast response algorithm before lock is achieved to a slow response algorithm

HSI ISR Capture time neg. on Save Event Time Return from ISR Event? pos. on Compute zero crossing time - Tzcm Compute filtered Tzc, Pd, and Pd/6 from PLL algorithm Compute sum squared, S, of Phase Control No Reset Run & Lock Flags Return from ISR S<=Limit? No Yes

during the next sixth of the cycle by retrieving data from two gate firing sequence tables. Three timed events are scheduled during the output interrupt service routine: the first two events pulse two of the six gate signals high and specify at what time the events occur. The third event, an arbitrary fixed delay after the first two events, resets all HSO pins low. The third event is also programmed to generate the next HSO interrupt thus making the interrupts self perpetuating while generating gate firing pulses. By disabling HSO interrupts, this process for generating gate pulses is terminated.

HSO ISR None set Return from ISR

Flags? Run Flag Determine HSO pin states from firing table Compute HSO pin high event times from Tref, Pd, Pd/6, and Td,

Start Flag Set? Yes Set Tref=Tzc Start HSO Clear Start Flag

Determine HSO pins from sequence table Schedule pin high and pin low events Return from ISR
Fig. 8. High speed output interrupt service routine flow diagram.

Fig. 7. High speed input interrupt service routine flow diagram.

Two HSI interrupts are generated per cycle of the power system voltage and processed to determine the measured zero crossing as explained in IV. After the second, or Positive-on, generated interrupt, the measured zero crossing time, Tzcm, is calculated, becoming an input to the the phase filtering algorithm, explained in V and VI. Three variables set by this routine for use in the high speed output interrupt service routine are as follows: the zero phase time Tzc, the period of the locked frequency Pd, and the period of a signal corresponding to six times the locked frequency Pd/6. At the expense of a few more optoisolators, the sampling interval could be defined as one-sixth of a period, with an attendant improvement in command tracking. This improvement comes at the additional expense of a sixfold increase in computation burden which is still within the microcontroller's capability as demonstrated in Section X of this paper. Other methods for dividing the period are discussed in [23]. During the HSO interrupt service routine shown in Fig. 8, the processor determines which outputs are to be set high

Only when a signal from the operator first initiates the generation of the gate firing pulses, the actual zero crossing time, Tzc, is copied into the gate firing reference variable, Tref which subsequently stays synchronized with the actual zero crossing by using the periods, Pd and Pd/6, computed in the HSI interrupt service routine. Although (8) specifies that Tref is incremented by Pd, the actual time when this update occurs may shift forward and back in relation to the corresponding actual zero crossing by the amount specified by the operator for TD, the delay time. Hence, for a negative delay time TD, Tref will update before Tzc. Thus it is necessary to maintain two zero crossing time references, Tzc for the PI algorithm and Tref for scheduling the gate firing pulses.

X. OPERATIONS Fig. 9 shows the six experimental outputs to the SCR gates for a zero phase delay. The pulse widths are exaggerated for illustrative purposes and are programmable in processor code. The second firing pulse overcomes discontinuous conduction, for example, at startup, and is ordinarily deleted in continuous conduction. The range of delay is zero to 52.4 ms or from zero to over 1000 degrees for 60 Hz nominal input. The upper restriction is imposed by the crystal frequency used with the 87C196KD processor and the 16 bit timer used to schedule output events. Since the delay is incorporated on a feedforward command outside the PLL algorithm, there are no restrictions on the size of step in phase delay. The advantage of a feedforward command for delay is its improved tracking performance: Any change in the desired firing angle is implemented in its entirety at the very next instant that a new command is applied without affecting the disturbance rejection of the PLL. The waveforms generated by experimental data shown in Fig. 9 are independent of frequency within the range of 40 to 70 Hz. No changes in code or hardware are required to operate on a 50 Hz power system. There is sufficient dynamic range in the mathematics of the PLL algorithm to accommodate the period offset to 50 Hz without loss of performance.
S3 S2 S1
Gate Pulses

XI. CONCLUSION An embedded microcontroller produces a minimal parts implementation of a Phase Controlled Rectifier with phaselocked loop-based generation of gate signals. Two inexpensive optoisolators used for the phase detector reduce instrumentation requirements. Innovative analog and digital signal processing improve the accuracy of the zero crossing time. Dynamic digital phase-locked loop characteristics provide improved capture and lock performance. A feedforward method separates disturbance rejection from command tracking: Rapid, accurate response to commands occurs while rejecting a wide range of disturbances, including disturbances both faster and slower than the command. The flexibility and simplicity of the processor based design makes this converter extremely efficient and reliable. The processors capabilities will permit expansion of the control algorithms to include, for example, protective algorithms, closed loop constant voltage control, or closed loop constant current output control. XII. BIOGRAPHY Richard W. Wall born 1946 received his BSEE from the Pennsylvania State University (68) and MEEE and PhD EE from the University of Idaho(80, 89). He worked for Idaho Power Co. for 18 years in the communications, protective relaying and R&D departments before joining the University of Idaho Department of Electrical Engineering. He teaches Embedded Microcontrollers and Senior Design. His research interests include protective relaying and networked distributed control. Herbert L. Hess received his BS from the US Military Academy ('77), MS from the Massachusetts Institute of Technology ('82), and PhD from the University of WisconsinMadison ('93), where he held a Hertz Fellowship. He served on the faculty of the US Military Academy from 83-88. In 93, he joined the University of Idaho, where he is an Assistant Professor of Electrical Engineering. His research interests include analysis, design, and control of electric machines, drive systems, and power converters and their effects on the quality of electric power. XIII. ACKNOWLEDGMENT This research was supported in part by a grant from University of Idaho Instructional Media Services entitled "Power Electronic Converters for Hands-on Investigation in the Classroom."
XIV. REFERENCES [1] J.M.D. Murphy and F.G. Turnbull, Power Electronic Control of AC Motors (New York: Pergamon, 1988). [2] J. D. Ainsworth, "The Phase Locked Oscillator--A New Control System for Controled Static Converters," IEEE Transactions on Power Apparatus and Systems, Vol 87, March 1968, pp. 859-865.

S4 S5 S6 A B -20 C -10 0 10 Time - ms 20 30

Input Voltage

Fig. 9. Experimental results of HSO outputs to the SCR gate controls for a zero degree phase delay. Dual pulses are for illustration purposes.

The execution time for the HSI interrupt service routine is less than 40 s and the execution time for the HSO interrupt service routine is 18 s. This represent a 0.34% utilization. Fixed point math was used in the control algorithms with 32 bit precision. The program required 650 bytes of the possible 32K bytes of internal ROM and 75 bytes of the possible 2K bytes of internal RAM. None of the 8 analog input channels were used as well as numerous other resources provided by the 87C196KD processor. In other words, there remains a great deal of opportunity for incorporating sophisticated outer control loops using the same processor.

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