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3D Platforms for IC Integrated MEMS

Frank Niklaus, Gran Stemme


KTH - Royal Institute of Technology School of Electrical Engineering Microsystem Technology Group Stockholm, Sweden Faun AB, Sweden www.fauninfrared.com
Email: frank.niklaus@ee.kth.se Mobile: +46 76 216 73 49

Frank Niklaus, December 8, 2008

Microsystem Technology at KTH Stockholm, Sweden


Research Topic: MEMS Total Staff: 24
16 Ph.D. Students 6 Senior Ph.D.

Bio & Med IC Integrated MEMS MEMS RF MEMS

KTH Semiconductor Laboratory in Kista 1200 m2 clean room area MEMS process technologies up to 8 inch wafers
Frank Niklaus, December 8, 2008

Outline

What is heterogeneous wafer-level 3D integration? Heterogeneous 3D integration of MEMS and ICs


3D IC integrated MEMS platforms with via-last approach. 3D IC integrated MEMS platforms with via-first approach.

IC compatible wafer-level MEMS packaging

Frank Niklaus, December 8, 2008

Heterogeneous Wafer-Level 3D Integration (More than Moore)

Wafers
I/Os, A/Ds, sensors and/or MEMS Memory

3-D Chip Sequentially Stack


align, bond, thin and interconnect

Processor/Logic

I/Os, A/Ds, sensors and/or MEMS


Image source: RPI, USA

Heterogeneous integration is generally defined as the integration of two or more compounds. Heterogeneous wafer-level 3D integration can be defined as stacking and interconnecting wafers, typically prepared with diverse technologies and / or materials.
Frank Niklaus, December 8, 2008

Heterogeneous 3D Integration of MEMS and ICs Advantages:


New MEMS designs, functionalities and material combinations. High performance MEMS materials on standard foundry ICs. Very high integration densities for smaller and cheaper components.

MEMS

Disadvantages:

CMOS IC
Image source: KTH-MST

May not be economic if IC and MEMS parts are very different in size. Severe penalty in yield accumulation when stacking several layers (not typical for MEMS).
Frank Niklaus, December 8, 2008

Heterogeneous 3D Integration Concepts

Via First:

Wafer 2 Device Layer 2 El. Contacts/Vias Wafer 2 Device Layer 2

Device Layer 1 Wafer 1

Device Layer 1 Wafer 1

(a) El. via deposition prior to bonding.

(b) Wafer bonding incl. via formation.

Via Last:
Wafer 2 Device Layer 2 El. Contacts Wafer 2 Device Layer 2 Device Layer 2

Device Layer 1 Wafer 1

Device Layer 1 Wafer 1

Device Layer 1 Wafer 1

(a) Wafer preparation.

(b) Wafer bonding and device release.

(c) Via hole etching and via deposition.


Frank Niklaus, December 8, 2008

Image source: Modified from RPI, USA

Outline

What is heterogeneous wafer-level 3D MEMS integration? Heterogeneous 3D integration of MEMS and ICs
3D IC integrated MEMS platforms with via-last approach. 3D IC integrated MEMS platforms with via-first approach.

IC compatible wafer-level MEMS packaging

Frank Niklaus, December 8, 2008

Heterogeneous 3D Integration Using Via-Last Approach


Wafer 2 Device Layer 2 El. Contacts Device Layer 2 Device Layer 2

Device Layer 1 Wafer 1

Device Layer 1 Wafer 1

Device Layer 1 Wafer 1

(a) Wafer preparation.

(b) Wafer bonding and device release.

(c) Via hole etching and via deposition.

Advantages:
Extreme reduction of via and device dimensions (sub m) at high yield possible. No wafer-to-wafer alignment during bonding needed (cost efficient). Post-bond processing identical to surface micromachining.

Disadvantages:
MEMS devices must be processed after bonding. Only face-to-face bonding practical.

Image source: Modified from RPI, USA

Frank Niklaus, December 8, 2008

Wafer Bonding for Via-Last Approach


Adhesive wafer bonding:
=> Extensive R&D for 3D IC integrated MEMS ongoing (e.g. KTH, Faun).
Wafer 2 Device Layer 2 Wafer 2 Device Layer 2

Device Layer 1 Wafer 1

Device Layer 1 Wafer 1

Direct wafer bonding:


=> R&D mainly focused on 3D ICs (i.e. Ziptronix). Some R&D on IC integrated MEMS (Fraunhofer, some universities). Wafer surface treatment and planarization needed. Sensitive to particles.

Wafer 2 Device Layer 2 Wafer 2 Device Layer 2 Device Layer 1 Wafer 1 Device Layer 1 Wafer 1

Image source: Modified from RPI, USA

Frank Niklaus, December 8, 2008

Proprietary 3D IC Integrated MEMS Platform at KTH

Polymer Adhesive SOI Wafer SOI Wafer Mono-Crystalline Si IC Contact Pads IC Wafer

IC Wafer

IC Wafer

(a)
Via Holes Vias

(b)

(c)
IC-Integrated MEMS

IC Wafer

IC Wafer

IC Wafer

(d)

(e)

(f)

Frank Niklaus, December 8, 2008

3D IC Integrated MEMS Platform Features


Mono-Si MEMS can be integrated on any foundry ASIC. Polymer adhesive can be used as sacrificial layer for dry release etch. Easy migration from one ASIC technology node to the next without changing the MEMS process. MEMS foundry compatible. No wafer-to-wafer bond alignment required. No wafer surface planarization required. Works practically with any wafer material. Low-cost, easy to use and high yield process.
Frank Niklaus, December 8, 2008

Examples of 3D Integrated MEMS

Micro-mirror Arrays IR Bolometer Arrays RF MEMS devices

Frank Niklaus, December 8, 2008

Spatial Light Modulators (SLMs)

Mono-crystalline silicon micro-mirrors on ICs (FP6-Q2M)


Goal: Improvement of mechanical and surface mirror properties 3D MEMS-IC integration using adhesive wafer bonding

Applications
DUV lithography using tilting mirrors Wavefront correction using piston mirrors

KTH-MST and Fraunhofer IPMS


Frank Niklaus, December 8, 2008

Spatial Light Modulators (SLMs)


Micro-mirror arrays for DUV lithography (Tilting mirrors)
For Mask-writing systems. UV illumination. Step-and-Repeat lithography. Analogue tilt actuation in 16 steps (gray-tones) possible. 1 million mirror array. (mirror size 16 x 16 m2). Single mirror actuation possible with underlying CMOS.

Source: Zimmer, Fraunhofer IPMS

Frank Niklaus, December 8, 2008

Torsional Micromirrors

Mirror Membrane

Torsional Hinges

Distance Holders Addressing Electrode

Posts (Vias)
Source: Zimmer, Fraunhofer IPMS

Haasl, 2002

Frank Niklaus, December 8, 2008

Si Mirror Integration: SOI and IC wafer

SOI Wafer

CMOS IC
Thermistor Material (e.g.Si) SiN SiO2 MoSi Al Ti Au
Frank Niklaus, December 8, 2008

Si Mirror Integration: Dispense Glue

SOI Wafer

Glue CMOS IC

Frank Niklaus, December 8, 2008

Si Mirror Integration: Adhesive Wafer Bonding

SOI Wafer Glue CMOS IC

Frank Niklaus, December 8, 2008

Si Mirror Integration: Sacrificial Wafer Thinning

Glue CMOS IC

Frank Niklaus, December 8, 2008

Si Mirror Integration: Removal of SiO2 Etch-Stop

Glue CMOS IC

Frank Niklaus, December 8, 2008

Si Mirror Integration: Via Etch

Glue CMOS IC

Frank Niklaus, December 8, 2008

Si Mirror Integration: Via Formation

Glue CMOS IC

Frank Niklaus, December 8, 2008

Si Mirror Integration: Mirror Formation

Glue CMOS IC

Frank Niklaus, December 8, 2008

Si Mirror Integration: Mirror Release

CMOS IC

Frank Niklaus, December 8, 2008

Torsional Mono-Si Micromirror Arrays

Image source: KTH-MST

Image source: MST NEWS 2008

Frank Niklaus, December 8, 2008

SLMs for Adaptive Optics in Astronomy and Microscopy


Wave-front correction using piston mirrors

Lapisa KTH-MST, Gehner, Fraunhofer, 2008

Source: Zimmer, Fraunhofer IPMS


Frank Niklaus, December 8, 2008

Mono-crystalline silicon mirrors for AO

Lapisa KTH-MST, Gehner, Fraunhofer, 2008

Frank Niklaus, December 8, 2008

Mono-crystalline silicon mirror arrays

Lapisa KTH-MST, Gehner, Fraunhofer, 2008

Frank Niklaus, December 8, 2008

Mono-crystalline silicon mirror arrays

Lapisa KTH-MST, Gehner, Fraunhofer, 2008

Frank Niklaus, December 8, 2008

Uncooled Infrared Bolometer Arrays


Infrared Imaging

http://sirtf.caltech.edu
Frank Niklaus, December 8, 2008

Operation of Bolometer Arrays

Buttler, 1995
Frank Niklaus, December 8, 2008

Proprietary 3D IC Integration of IR Detectors at KTH / Faun


Polymer Adhesive SOI Wafer SOI Wafer Mono-Crystalline Si IC Contact Pads IC Wafer

IC Wafer

IC Wafer

(a)
Via Holes Vias

(b)

(c)
IC-Integrated MEMS

IC Wafer

IC Wafer

IC Wafer

(d)

(e)

(f)

Epitaxially grown Si/SiGe material with high TCR and low 1/f noise. Monolithic integration on IC not possible. => 3D MEMS IC integration
Frank Niklaus, December 8, 2008

Si-Based Bolometer on Fan-Out-Board

16x16 IR Bolometer Array

Frank Niklaus, December 8, 2008

RF MEMS: Radar Beam Steering with MEMS Tuneable Metamaterials


Collaboration

Tuned gradient
Applications

180

Reflection phase

car radar 77GHz

high-capacity comm. links

-180 Frequency, GHz


Image source: Sterner, KTH

Frank Niklaus, December 8, 2008

RF Metamaterial Design of Fabrication Process

gold, 0.5 um silicon, 1 um gold, 0.5 um SiN isolation 0.2 m gold, 1 um glass, 100 um BCB, 5-10 um gold, 1 um glass substrate 500 um air gap 1.5 um 3-electrode tuneable capacitor for extended tuning range

Image source: Sterner, KTH

Frank Niklaus, December 8, 2008

RF Metamaterial Fabricated Device Array

Arrayof 20052 elements

Etch hole

Springs

Gapof ~1.5m

Image source: Sterner, KTH

Frank Niklaus, December 8, 2008

RF-MEMS PZT Switch

Structural layer: Monocrystalline Silicon / SiN

Actuator: Lead zirconate titanate (PZT)

Transmission line (gold)

Image source: Saharil, KTH


Frank Niklaus, December 8, 2008

Photonic MEMS: Integration of GaAs on ICs


0.7 m GaAs Film

4-inch Silicon Wafer

Frank Niklaus, December 8, 2008

Adhesive Wafer Bonding is Key

Gluing two (wafer) surfaces together

Glue Semiconductor Wafer Semiconductor Wafer

Frank Niklaus, December 8, 2008

Working Principles of Adhesives

Contact between two solid surfaces.

Contact between a solid surface and a liquid.


Frank Niklaus, December 8, 2008

Polymer Adhesives
Polymers can transform from a liquid into a solid state by:
1. Drying (solvents or water evaporate) 2. Heating and cooling (thermoplastic polymers) 3. Curing (chemical reaction forming larger molecules, thermosetting polymers) e.g.
mixing of two components heating UV-light illumination

Frank Niklaus, December 8, 2008

Suitable Polymer Adhesives


Thermosetting polymers
BCB (Dow Chemical), chemically stable, <350C SU8 (Microresist, Germany), chemically stable <250C

Thermoplastic polymers
Polymethyl methacrylate (PMMA), easily etchable Liquid crystal polymers, low moisture uptake

Many polyimides are not suitable for high yield adhesive wafer bonding !
Frank Niklaus, December 8, 2008

Deposition of Thin Polymer Layers


Spin Coating
Liquid Polymer Wafer

Standard technology Wide thickness range of coatings (0.1 m to 50 m) Very uniform coatings

Alternative polymer deposition techniques are:


spraying, evaporation, screen printing, stamping, electro deposition, lamination, etc.
Frank Niklaus, December 8, 2008

Adhesive Wafer Bonding Process

Vacuum
Clamps Spacers
Wafer 2 Wafer 1

Bond Chamber

Bend Pin

Bond Fixture

Adhesive wafer bonding in commercial bond equipment.


Frank Niklaus, December 8, 2008

Adhesive Wafer Bonding Process

Vacuum

Bond Chamber

Force
Top Chuck HOT
Wafer 2 Wafer 2 Wafer 1

Bend Pin

Bond Fixture HOT

Adhesive wafer bonding in commercial bond equipment.


Frank Niklaus, December 8, 2008

Important Bonding Parameters


Polymer adhesive (no outgassing and no drying adhesives). Bonding pressure. Reflow time during bonding. Wafer thickness. Atmosphere in the bond chamber. Level of polymerisation (cross-linking) before bonding (for thermosetting polymers). Relation between wafer topography features and polymer thickness.

Frank Niklaus, December 8, 2008

Influence of Wafer Topography on Void Formation

H.D. Rowland et al. 2005

Image source: KTH-MST

Frank Niklaus, December 8, 2008

Cross-Linking and Viscosity of BCB Dependent on Time and Temperature

Image source: Dow

Frank Niklaus, December 8, 2008

Keyed Alignment in Adhesive Bonding

Image source: Lee, Niklaus 2006

Frank Niklaus, December 8, 2008

Outline

What is heterogeneous wafer-level 3D MEMS integration? Heterogeneous 3D integration of MEMS and ICs
3D IC integrated MEMS platforms with via-last approach. 3D IC integrated MEMS platforms with via-first approach.

IC compatible wafer-level MEMS packaging

Frank Niklaus, December 8, 2008

Heterogeneous 3D Integration Using Via-First Approach

Wafer 2 Device Layer 2 El. Contacts/Vias Wafer 2 Device Layer 2

Device Layer 1 Wafer 1

Device Layer 1 Wafer 1

(a) El. via deposition prior to bonding.

(b) Wafer bonding incl. via formation.

Advantages:
Simple process with via formation during bonding (cost efficient). Complete device preparation prior to bonding possible. Face-to-face and face-to-back wafer bonding possible.

Disadvantages:
Need for wafer-to-wafer alignment. Limitation in via-size reduction and potential yield issues. Possible air-gap between wafers.

Image source: Modified from RPI, USA

Frank Niklaus, December 8, 2008

Wafer Bonding for Via-First Approach


Metal via bonding with optional adhesive support structures:
=> Extensive R&D for 3D IC integrated MEMS ongoing (e.g. IBM Zrich, universities).
Wafer 2 Device Layer 2 El. Contacts/Vias Device Layer 1 Wafer 1 Wafer 2 Device Layer 2 Device Layer 1 Wafer 1

Metal via bonding and parallel adhesive or direct bonding:


=> R&D mainly focused on 3D-ICs E.g. parallel metal and adhesive bond (RPI) and parallel metal and direct bond (Ziptronix). => R&D for IC integrated MEMS not known. High requirements on surface planarity. Sensitive to particles.

Wafer 2 Device Layer 2 El. Contacts/Vias Device Layer 1 Wafer 1 Wafer 2 Device Layer 2 Device Layer 1 Wafer 1

Image source: Modified from RPI, USA

Frank Niklaus, December 8, 2008

IBMs Millipede Data Storage

Vettinger, 2002

Arrays of membrane tips that can create pits with a side length of about 10 nm using heating of the polymer surface. 4000 tips on a 6.4 mm x 6.4 mm area can store the data of 25 DVD.
Frank Niklaus, December 8, 2008

Manufacturing of the Millipede Read-Write Head

Vettinger, 2002

Frank Niklaus, December 8, 2008

Transferred Read-Write Cantilevers

Vettinger, 2002
Frank Niklaus, December 8, 2008

Outline

What is heterogeneous wafer-level 3D MEMS integration? Heterogeneous 3D integration of MEMS and ICs
3D IC integrated MEMS platforms with via-last approach. 3D IC integrated MEMS platforms with via-first approach.

IC compatible wafer-level MEMS packaging

Frank Niklaus, December 8, 2008

Room-Temperature Wafer-Level Hermetic Sealing of Cavities

1.

Sealing Rings Seal defining a cavity

Sealing rings on wafer 1 Overlap bonding area (black lines)

Wafer 1

a.

Wafer 2

Sealing ring on wafer 2

2.

Cold welding at overlapping areas Sealed cavities Wafer 1

Wafer 2

(b)

(a)

(c)

Decharat, 2007
Frank Niklaus, December 8, 2008

Localized Adhesive Wafer Bonding Process


Photoresist Polymer Adhesive

Polymer deposition
Silicon Wafer

Silicon Wafer

Lithographic patterning of the polymer (using photoresist mask and dry etching) Adhesive wafer bonding

Top Wafer Silicon Wafer

Frank Niklaus, December 8, 2008

Localized Adhesive Wafer Bonding

Top View

Glass Wafer Silicon Wafer

Oberhammer, 2001
Frank Niklaus, December 8, 2008

Wafer-level Packaging of MEMS

Oberhammer, 2003

Frank Niklaus, December 8, 2008

Wafer-Level Fabrication of Cavities for MEMS Packaging

Potentially cheaper than chip packaging. Protects devices during dicing. Packages need to be hermetic (gas-tight). Polymers are permeable to moisture.
Polymer Molecules
Casco Nobel, 1992
Frank Niklaus, December 8, 2008

H2O

Wafer-Level Hermetic Sealing of Cavities


Adhesive Wafer 2 (Capping Wafer) Wafer 1

Fabrication of cavities

(1)

Wafer 1

Dicing and etching of top wafer


Metal)

(2)
Sealed Cavity Diffusion Barrier (e.g. Silicon Nitride or

Wafer 1

(3)

Deposition of a diffusion barrier material


Frank Niklaus, December 8, 2008

Hermetically Sealed Cavity

PECVD SiN as aditional diffusion barrier material has been tested He leak tests show significantly less He absorbtion of sealed cavities as compared to non sealed cavities
Oberhammer, 2002

Frank Niklaus, December 8, 2008

Summary

Adhesive and direct wafer bonding techniques are being used for integrating MEMS and ICs. Via-first and via-last platforms are being used with focus currently on arrayed MEMS such as micro-mirror, IR bolometer and AFM tip arrays. Heterogeneous integration should also be attractive for IC integrated inertia sensor, pressure sensors and microphones.

Frank Niklaus, December 8, 2008

Thank You For Your Attention !

Frank Niklaus, December 8, 2008