PROCESSOR CHIPS IN NOKIA PHONES

G.GOWSALYA 11MX11 M.LOGESWARAN 11MX24 G.PACKIYA LAKSHMI 11MX30 S.ROSALINMARY 11MX41 S.VIVEK RAMJEE 11MX56
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AGENDA
INTRODUCTION FEATURES OPERATING MODES

REGISTERS
FLAGS

INSTRUCTION STYLE

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Where is ARM?

Enabling the ARM Learning in INDIA

INTRODUCTION
ARM Advanced RISC machines. Advances RISC Machines (now known as ARM) was

established as a joint venture between Acorn, Apple in November 1990.

Used in majority of Nokia phones, Iphone, Android

series of samsung and sony ericssions phones.

32 bit architecture. In ARM

Word-32bit
Half word-16bit Byte-8bit
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INTRODUCTION

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INTRODUCTION
The ARM11 microarchitecture is the first implementation of the ARMv6 instruction set architecture, and forms the basis of a new family of ARM11 cores. Improved cache architecture. Improved exception and interrupt handling Unaligned and mixed-endian data support ARM's architecture is compatible with all four major platform operating systems: Symbian OS,Palm OS, Windows CE, and Linux.

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FEATURES
2 different instruction sets 32 bit ARM instruction set 16 bit thumb instruction set

Simplified system design and increased code density.

Can address only first 8 registers. 8bit jazelle instruction set to execute java byte code.

ARM has 37 registers. Most instructions execute in a single cycle. A load/store architecture .

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FEATURES
Instruction set extension via coprocessors cost-sensitive embedded applications Simple addressing modes

High Performance
Low power consumption 8-stage pipeline

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MEMORY AND ADDRESSING

32bit addressing, a maximum of 4GB addressed. Memory is usually divided into 4 banks. Cannot read or write directly from memory .

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Operating Modes
There are 7 operating modes User mode
FIQ IRQ

Supervisor
Abort Undef System
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Operating Modes
user mode - used for running general

user applications. FIQ - fast/high priority interrupts IRQ - general purpose interrupts

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Operating Modes
Supervisor - protected mode for

operating systems Abort - instruction prefetch halt. ie when fetching the upcoming instructions to reduce wait times and the fetch fails. Undef - to handle undefined instruction exception handling System - mode for operating systems
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Registers
37 registers, each 32bits
1 dedicated PC 1 dedicated program status/flag register 5 dedicated saved program status registers 30 general purpose registers

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Register Organization
User
r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 (sp) r14 (lr)

FIQ

IRQ

SVC

Undef

Abort

User mode r0-r7, r15, and cpsr

r8 r9 r10 r11 r12 r13 (sp) r14 (lr)

User mode r0-r12, r15, and cpsr

User mode r0-r12, r15, and cpsr

User mode r0-r12, r15, and cpsr

User mode r0-r12, r15, and cpsr

r13 (sp) r14 (lr)

r13 (sp) r14 (lr)

r13 (sp) r14 (lr)

r13 (sp) r14 (lr)

r15 (pc)
cpsr spsr spsr spsr spsr spsr

Note: System mode uses the User mode register set

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Program Status Registers

Condition code flags Interrupt Disable bits.

N = Negative result from ALU I = 1: Disables the IRQ.( general purpose interrupt ) Z = Zero result from ALU F = 1: Disables the FIQ. (Fast C = ALU operation Carried interrupt) out T Bit V = ALU operation Architecture xT only overflowed T = 0: Processor in ARM Q flag state Sticky Overflow flag T = 1: Processor in Thumb J bit state J = 1: Processor in Jazelle Mode bits 7/20/2012 15 state

Flags
These register's functions are: Hold information about the most recently

performed ALU operation. Control the enabling and disabling of interrupts. Set the processor operating mode.
Q - You can set the Sticky Overflow, Q flag, to 1 by

executing certain multiply and fractional arithmetic instructions. When set to 1 conditional instructions cant be executed. Q flag must be explicitly cleared.
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Program Status Registers

Condition Code Flags The N, Z, C and V are condition code flags may be changed as a result of arithmetic and logical operations in the processor may be tested by all instructions to determine if the instruction is to be executed Control Bits The I, F, T and M[4:0]) bits will be changed when an exception arises. If the processor is operating in a privileged mode, they can also be manipulated by software.
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Program Status Registers

T bit: This reflects the operating state. When this bit is set, the processor is executing in THUMB state, otherwise it is executing in ARM state. This is reflected on the TBIT external signal. Note that the software must never change the state of the TBIT in the CPSR. If this happens, the processor will enter an unpredictable state.

Interrupt disable bits:

The I and F bits are the interrupt disable
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bits. When set, these disable the IRQ and FIQ interrupts respectively. 7/20/2012

Mode bits: The M4, M3, M2, M1 and M0 bits (M[4:0]) are the mode bits. These determine the processor's operating mode. Not all combinations of the mode bits define a valid processor mode. Only those explicitly described shall be used. The user should be aware that if any illegal value is programmed into the mode bits, M[4:0], then the processor will enter an unrecoverable state. If this occurs, reset 7/20/2012 19 should be applied.

Mode bits
M[4:0] MODE

10000
10001 10010

User
FIQ IRQ

10011
10111 11011

Supervisor
Abort Undefined

11111

System

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Program Counter
When the processor is executing in ARM state: All instructions are 32 bits wide All instructions must be word aligned Therefore the pc value is stored in bits [31:2] with bits [1:0] undefined (as instruction cannot be halfword or byte aligned). When the processor is executing in Thumb state: All instructions are 16 bits wide All instructions must be halfword aligned Therefore the pc value is stored in bits [31:1] with bit [0] undefined (as instruction cannot be byte aligned). When the processor is executing in Jazelle state: All instructions are 8 bits wide 7/20/2012 21 Processor performs a word access to read 4 instructions at

ARM11 - Key Features

Branch prediction Pipeline parallelism Improved memory access 64-bits datapaths

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Pipelining
user 8 stages of Pipelining

mul & load/store or ALU/shift &

load/store can occur simultaneously.

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8 stages in normal pipeline Fe1 Address is sent and instruction received Fe2 Much of the branch prediction goes here De Decode instruction Iss Read registers and issue instruction Sh Perform shift operations ALU Perform integer operations Sat Saturate results WB Write back data to registers 7/20/2012 24

MP11 CPU Pipeline Stages

Stage 1

Stage 2

Stage 3

Stage 4

Stage 5
Shifter Stage (Sh)

Stage 6
ALU Operation (ALU) 2nd multiply acc. Stage (MAC2) Data cache 1 (DC1)

Stage 7
Saturation Stage (Sat)

Stage 8

1st Fetch Stage (Fe1)

1st Fetch Stage (Fe2)

Instruction Decode (De)

Reg. read and issue (Iss)

1st multiply acc. Stage (MAC1) Address Generation (ADD)

3rd multiply acc. Stage (MAC3) Data cache 2 (DC2)

Write back Mul/ALU (WBex)

Write back from LSU (WBIs)

Notes 1) To minimize power consumption, each of the MAC and ALU stages is only clocked when required. 25 7/20/2012

Instruction code style

ARM instructions can be made to

execute conditionally by post fixing them with the appropriate condition code field. This improves code density and performance by reducing the number of forward branch instructions.
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Conditional Execution and Flags

BEQ - Branch on Equal to -similarly Bxx Branch on xx (xx is condition) By postfixing the EQ (equal to), NE (not equal) in other instructions perform the job branching for single instruction without having to use 2 separate instructions, Increasing code density. Eg. cmp r3, #3 beq skip add r0, r1, r2 skip: can be coded simply as cmp r3, #3 addne r0, r1, r2
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Subroutine
Need not stack flags/status or return addresses.

It is done using the additional program

flags/status registers (spsr - stored program status register). And return addresses are restored using the link register (r14) to the program counter (r15). If the program take up multiple branches then LR has to be stacked (r13 - stack pointer).
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conclusion

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