Beruflich Dokumente
Kultur Dokumente
and Design
s
5-1
Instruction Cycle
sequence(control) A instruction is a binary code that specifies a sequence of microoperations Instruction codes together with data are stored in memory(=Stored Program Concept) The computer reads each instruction from memory and places it in a control register. The control then interprets the binary code of the instruction and proceeds to execute it by issuing a sequence of microoperations. Instruction Code :
q q
15 12 11 0 Operation Code : Op. Code Address q The most basic part of an instruction code q A group of bits that define such operations as add, subtract, multiply, shift, and complement(bit 12-15 : 24 = 16 distinct operations)
Computer System Architecture
A group of bits that instruct the computer to perform a specific operation It is usually divided into parts(refer to Fig. 5-1 instruction format) Instruction Format
5-2
Stored Program Organization : Fig. 5-1 q The simplest way to organize a computer
One processor register : AC(Accumulator)
s
The operation is performed with the memory operand and the content of AC Op. Code : specify 16 possible operations(4 bit) Address : specify the address of an operand(12 bit) If an operation in an instruction code does not need an operand from memory, the rest of the bits in the instruction(address field) can be used for other purpose( 16 instruction : Tab. 5-2 , 25 instruction) Store each instruction code(program) and operand (data) in 16-bit memory word
Instruction code format with two parts : Op. Code + Address Exam) Clear AC, Increment AC, Complement AC, ...
s s s
One bit of the instruction code is used to distinguish between a direct and an indirect address : Fig. 5-2(a)
Chap. 5 Basic Computer Organization and Design Dept. of Info. Of Computer
5-3
Effective Address q The operand address in computation-type instruction or the target address in a branch-type instruction
s
5-4
q q
Input Register(INPR) : receive an 8-bit character from an input device Output Register(OUTR) : hold an 8-bit character for an output device
Common Bus System q The basic computer has eight registers, a memory unit, and a control unit(in Sec. 5-4) q Paths must be provided to transfer information from one register to another and between memory and registers q A more efficient scheme for transferring information in a system with many registers is to use a common bus(in Sec. 4-3) q The connection of the registers and memory of the basic computer to a common bus system : Fig. 5-4
The outputs of seven registers and memory are connected to the common bus The specific output is selected by mux(S0, S1, S2) :
s s s s
Memory(7), AR(1), PC(2), DR(3), AC(4), IR(5), TR(6) Device AC INPR OUTR mux memory register bus When LD(Load Input) is enable, the particular register receives the data from the bus
Control Input : LD, INC, CLR, Write, Read Address Register : Address bus ( Bus address data )
s s
AC DR memory read (p. 146, LDA ) Memory write AC write (p. 147, STA ) Chap. 5 Basic Computer Organization and Design Dept. of Info. Of Computer
5-5
Accumulator(AC) : 3 Path
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1) Register Microoperation : clear AC, shfift AC, 2) Data Register : add DR to AC, and DR to AC( AC End carry bit set/reset), memory READ(DR ) 3) INPR : Device (Adder & Logic )
s2 s1 s0 M e m o r y u n it 4 0 9 6 1 6 A d d r e s s
B 7
u s
r ite A R
L D IN R C
R e a d
1
L R
P C
L D IN R C L R
Note) Two microoperations can be executed: ats the 100(4), DR(load ) DR AC s s = same time
2 1 0
D
L D IN R
R
C L R
A d d e rE a n d lo g ic
L D IN
A C
R C L R
IN P R
I R
L D
T R
L D IN R C L R
O
L D
T R C lo c k
1 6 -
b it
c o m
o n
b u s
5-6
15 14
12 11
I Opcode
Address
Register-reference instruction
7xxx (7800 ~ 7001) : CLA, CMA, .
15 14 12 11 0
0 1 1 1
Register Operation
Input-Output instruction
Fxxx(F800 ~ F040) : INP, OUT, ION, SKI, .
15 14 12 11 0
Symbol AND ADD LDA STA BUN BSA ISZ CLA CLE CMS CMEm CIR CIL INC SPA SNA SZA SZE HLT INP OUT SKI SKO ION IOF
Hex Code I =0 I =1 0xxx 8xxx 1xxx 9xxx 2xxx Axxx 3xxx Bxxx 4xxx Cxxx 5xxx Dxxx 6xxx Exxx 7800 7400 7200 7100 e 7080 7040 7020 7010 7008 7004 7002 7001 F800 F400 F200 F100 F080 F040
Description And memory word to AC Add memory word to AC Load memory word to AC Store content of AC in memory Branch unconditionally Branch and Save return address Increment and skip if zero Clear AC Clear E Complement AC Comp Circulate right AC and E Circulate left AC and E Increment AC Skip next instruction if AC positive Skip next instruction if AC negative Skip next instruction if AC zero Skip next instruction if E is 0 Halt computer Input character to AC Output character from AC Skip on input flag Skip on output flag Interrup Inter
1 1 1 1
I/O Operation
5-7
If the computer includes a sufficient number of Instruction Set Completeness instructions in each of the following categories q Arithmetic, Logical, and shift : CMA, INC, .. q Moving information to and from memory and AC : STA, LDA q Program control : BUN, BSA, ISZ q Input/Output : INP, OUT
5-8
1 5
1 4
1 3
1 2
1 1
Control Unit = Control Logic Gate + 3 X 8 Decoder + Instruction Register + Timing Signal Timing Signal = 4 X 16 Decoder + 4-bit Sequence Counter Exam) Control timing : Fig. 5-7
Sequence Counter is cleared when D3T4 =1 : D3T4 : SC 0
I
3 8 d e c o d e r 6 5 4 3
t h e r
in p u t s
0 D0
D7 .
. .
o n t r Co ol n t r o l o u t p u t s lo g ic g a t e s
T1 T0 1 5 1 4 4 1 6 d e c o d e r
. . . . . .
4 - b it s e q u e n c e C le a r ( C L R ) c o u n t e r ( S C )
C lo c k
In c r e m
e n t ( IN
. . . )
5-9
Exam) Register transfer statement : T0 : AR PC q A transfer of the content of PC into AR if timing signal T0 is active
1) During T0 active, the content of PC is placed onto the bus ( S2 S1S0 ) 2) LD(load) input of AR is enabled, the actual transfer occurs at the next positive transition of the clock(T0 rising edge clock) T0 : Inactive 0000(T0 ) 0000 (T1 ) 3) SC(sequence counter) is incremented : T1 : Active
T0 = 1
T0 : AR PC
1) Place the content of PC onto the bus by making the bus selection inputs S2S1S0=010 2) Transfer the content of the bus to AR by enabling the LD input of AR
Computer System Architecture
5-10
T1 = 1
T1 : IR M [ AR ], PC PC + 1
1) Enable the read input memory 2) Place the content of memory onto the bus by making S2S1S0= 111 3) Transfer the content of the bus to IR by enable the LD input of IR 4) Increment PC by enabling the INR input of PC
Instruction Decode : T2
T2 : D0 ,...., D7 Decode IR(12 14), AR IR (0 11), I IR (15)
T1=1 T0=1
M M ee m m oo rr yy uu nn ii tt A d d r e s s R e a d
s2 s1 s0
u s
Op.code
P
Address Di/Indirect
0 1 0
1 1 1
IR(12-14) Fig. 5-6 D0 - D7 Register(I=0) I/O (I=1) D7IT3(Execute) D7IT3 (Execute) Direct (I=0) Read effective Address
L D
D7=1
A R
] D7IT3( AR M [ AR)
P C
I N R
nothing in T3
Register I/O T3 Memory Ref. T3 Operand effective address Memory Ref. T4, T5, T6 : Fig. 5-11
IR
L D
lo c k
o m
o n
b u s
Flowchart for instruction cycle(Initial Chap. 5 Basic Computer Organization and Design Computer Configuration) : Fig. 5-9 System Architecture
5-11
Address
IR(i) = Bi
IR(0 -11)
Decoder
5-6 Memory Ref. InstructionIR(12,13,14) 3X8 D7 : Register or I/O = 1 = 111 D6 - D0 : 7 Memory Ref.
D0T4 : DR M [ AR ]
e c o d e A R
T2 o p e r a t io n c o d e in I R ( 1 2 IR ( 0 - 1 1 ) , I I( 1 5 )
1 4 )
( R e g is t e r
o r
I / O 0) I
1 M (
e m
o r y -
r e f e r e n c e
Instruction(Tab. 5-4)
( I/ O
1 I
( r e g is t e r ) ( in d ir e c t ) I
( d ir e c t )
AND to AC
D0T5 : AC AC DR, SC 0
T3 E x e c u t e E i n p u t - o u t p ur et g i in s t r u c t io n in S C 0 S
T3 x e c u t e A R s t e r - r e f e r e n c e s t r u c t io n C 0
T3 M [ A R ] N
T3 o t h in g
E x e c u t e e m o r y - r e f e r e n c e in s t r u c t io n S C 0
D2T5 : AC DR, SC 0
Chap. 5 Basic Computer Organization and Design Dept. of Info. Of Computer
5-12
135 PC = 136
Return Address : save return address ( 135 21 ) D5T4 : M [135] 21( PC ), 136( AR ) 135 + 1 Subroutine Call : Fig. 5-10
D5T5 : 136( PC ) 136( AR ), SC 0
Control Flowchart : Fig. 5-11 q Flowchart for the 7 memory reference instruction
The longest instruction : ISZ(T6) 3 bit Sequence Counter ( 4 )
Computer System Architecture
5-13
IR(i) = Bi
IR(6 -11)
5-14
In s tru c tio n
c y c = l e0
= 1
In te rru p t
c y c le
F e t c h a n d d e c o d e in s tr u c t io n
S to r e r e tu r n a d d in lo c a t io n 0 M [ 0 ] P C
cycle
s
= 1
B r a n c h P C F G I = 0
to
lo c a t 1
IEN = 1 : the control circuit checks the flag bit, If either flag
= 1
O = 0
IE N R
0 0
The memory location at address 0 as the place for storing the return address Interrupt Branch to memory location 1 0 256(return address) Interrupt cycle IEN=0 ( ISR Interrupt 0 BUN 1120 PC = 1 T0'FGI + FGO ) : R 1 ) T1'T2' ( IEN )( ION ISR Main Program 255 q The condition for R = 1 Interrupt 256 Here Save ReturnModified Fetch Phase PC q RT0 : AR 0, TR Address(PC) at ModifiedM [ AR ]andTR, PC 0 0 RT : Fetch Decode Phase
1
1120 1
Jump to 1(PC=1)
RT2 : PC PC + 1, IEN 0, R 0, SC 0
Chap. 5 Basic Computer Organization and Design
5-15
Section
decoder(Fig. 5-6)
q q q
5. A 16-bit common bus(Fig. 5-4) 6. Control Logic Gates : Fig. 5-6 Box Control Output 7. Adder and Logic circuit connected to the AC input
Control Logic Gates q 1. Signals to control the inputs of the nine registers q 2. Signals to control the read and write inputs of memory q 3. Signals to set, clear, or complement the F/Fs q 4. Signals for S2 S1 S0 to select a register for the bus q 5. Signals to control the AC adder and logic circuit
Computer System Architecture
5-16
Register Control : AR q Control inputs of AR : LD, INR, CLR q Find all the statements that change the AR AR ?
F r o m
1 2 B u s
A R
1 2
T o C
B u
in Tab. 5-6
R ' T0 : AR PC
D 7' I T3 T2 R T0 D
5
L D
IN
L R
lo c k
LD( AR ) = R' T0 + R' T1 + D7 ' IT3 D7 ' IT3 : AR M [ AR ] CLR( AR ) = RT0 RT0 : AR 0 INR ( AR ) = D5T4 D5T4 : AR AR + 1
Control functions
R ' T1 : AR IR (0 11)
T4
Memory Control : READ M [ AR ] ? q Control inputs of Memory : READ, WRITE q Find all the statements that specify a read operation in Tab. 5-6 q Control function
READ = R' T1 + D7 ' IT3 + ( D0 + D1 + D2 + D3 )T4
IEN ?
D 7' I T3
? M [ AR ]
J K Q 1 (t+ ) 0 1 0 1 0 1
S E T
B7 C B6 R T2 lo c k
J K
Q
IE N
L R
5-17
x1 = 1 :
x2 = 1 :
x1 x2 x3 x4 x5 x6 x7
S0
Encoder
S1 S2
x7 = 1 :
5-18
Fig. 5-21
1 6 1 6
Fig. 2-11
F r o m F r o m
D
8
R P R
IN
A d d e r a n d lo g ic c ir c u it
1 6
A c c u m u la t o r1 6 r e g is t e r ( A C ) T o
B u s
L D
IN
L C R
lo c k
Fig. 5-20
o n t r o l g a t e s
5-19
A C
1 6
T o C
u s
lo c k
A N A D D IN
1
D D
IN
L R
D0T5 : AC AC DR D1T5 : AC AC + DR D2T5 : AC DR pB11 : AC (0 7) INPR rB9 : AC AC rB7 : AC shr AC , AC (15) E rB6 : AC shr AC , AC (0) E rB11 : AC 0 rB5 : AC AC + 1
CLR INR LD
T5 D1 D2 T5 p B1 r B B
9
R P R O M R L C L R
S H
7
S H B
6
IN B
5
C B1
1
5-20
( O A N C
i
u t p u t
o f L D
g a t e
in
F ig .
5 -
2 0 )
D D
J K Q 1 (t+ ) 0 1 0 1 0 1
A D D R
F A C
i+ 1
Ii ( F i g . 2 -
1 1 )
A C
( i)
IN P R F r o m I N P R b i t ( i )C O M S H A C A C R
lo c k
( i+ 1 ) S H L ( i1 )
Mano Machine
5-21
s s s
Integration !
Fig. 5-4 : Common Bus(p.130) Fig. 2-11 : Register(p. 59) Fig. 5-6 : Control Unit(p. 137) Fig. 5-16, 17,18 : Control Logic Gate(p.161- 163)
Fig. 5-4 Component Control Input Register, Memory, F/Fs, Bus Selection
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Due Date : 1