Types of analysis

Dynamic timing analysis Static timing analysis

Dynamic Timing Analysis

A series of vectors over a time are applied during a simulation run, simulation calculates the logic value and delays over that time.

RTL Functional Simulation Synthesis Gate Level Simulation Testbench

Scan Gates

Place

Clock Tree

Route

Static Timing Analysis

Static timing analysis is a method for determining if a circuit meets timing constraints without having to simulate
RTL Domain

Functional Simulation

Module Testbench

IP

Synthesis Equivalence Checking Netlist Enhancements (Scan, Place, Route, Clock) Static Timing Analysis
Functional Simulation Sign Off

Gate-Level Domain

Comparison Of Analysis
Dynamic timing Requires exhaust set of vectors Mixing both functional and timing problems Requires more resources like run time, cpu memory, etc. Static timing Doesn't requires any set of vectors Doesn't have any problem of mixing violations Requires less resources Than DTA

Can work with any type of Logic Can work best with Synchronous logic. either synchronous or asynchronous Easy to learn Difficult to learn

Why Static timing Analysis?

1. 2. 3. 4. To analyze the timing relationships of a given circuit to verify that the circuit works at the specified frequency (verification). 100 % path coverage is possible because no design specific pattern is required. You cant achieve the clock speed without it. All paths are assumed critical.

5.
6. 7.

Process variation across die can be modeled.

Constraints and reports are concise and easy to interpret. It can detect other serious problems like glitches, slow paths and clock skew.

Note: This analysis is done to provide the engineer feedback in order to help modify the design and/or modify the constraints to improve the timing quality of the design.

Place of STA in the ASIC Flow

SPEC S

Top Level Design and Architecture

Wireload models

RTL Coding

RTL Simulation/Verification

Synthesis

Cell Libraries
DFT insertion

Gate level Simulation

Static Timing Analysis

Conventional Front End Back End Divide

Floor planning/P&R/Timing Closure/Design Closure

Parasitic Extraction (SPEF)

Back annotation ( SDF)

FAB

Chip Testing

Why we do STA, Pre-Layout & Post-Layout???

Pre-Layout STA Clock skews Ideal clock assumed with estimated skew Post-Layout STA Actual clock delays (Propagated clock)

Net Delays Use

Wire load model To verify the flow, for estimation

Parasitics (SPEF) Final Sign off

Wire Load Models

Wire Loads Estimate interconnect length Statistical Analysis of Previously Routed Chips Predict the interconnect capacitance as a function of net fan-out and block size.
Wire Load Table

Net Load Net fanout Net fanout

1 0.015

Net Resistance
1 0.012

2
3 4

0.030 0.045
0.060

2
3 4

0.016
0.020 0.024

Steps in Static Timing Analysis

Path X A D Q OUT Z

CLK

STA involves three main steps:

1

Design is broken down into sets of timing paths Delay of each path is calculated Path delays are checked to see if timing constraints have been met

Basic STA concepts: Timing Paths

A CLK
D Q FF1
QB --

D Q FF2
QB --

Each path has a startpoint and an endpoint Starpoints: Input ports (A,Q) Clock pins of sequential devices (CLk) Endpoints: Output ports (D,Z) Data input pins of sequential devices (D)

Basic Timing Paths

Generally recognizes five types of default timing paths:

1. 2. 3. 4. 5.

Clock to setup Clock to pad Paths ending at clock pin of flip flops Pad to pad Pad to set up

Clock to setup : A clock to setup path starts at flip flop clock inputs, propagates through the flip flop Q out put and any number of levels of combinational logic , and ends at non clock flip flop register inputs .
A D B D ff1 clk Q ff2 Q

Contd..
Clock to pad : It starts at a clock input of a flip-flop, propagates through the flip-flop Q output and any number of levels of combinational logic , and ends at an output pad.
A D
Q
Logic and interconne cts

pad

clock

Paths ending at clock pin of flip flops : A clock input path starts at an input of the chip. It propagates through any number of levels of combinational logic and ends at any clock pin on a flip-flop or latch enable D Q
A Inter connect logic source

Contd..
Pad to Pad up : A pad to pad path starts at an input of the chip, propagates through one or more levels of combinational logic, and end at an output pad of the chip.
pad Logic interconnect logic pad

Pad to Set up : A pad to setup path starts at an input pad of chip and ends at flip flop input.
Set up

pad

D D

Q Q

Logic and interconne cts

clock

Timing Violations
Setup or Hold violation: Leads to improper operation of the flip flop and the connected components. The output of the flip flop goes into a state of metastability in the case of Setup/Hold violations. Recovery and Removal Violations : Violations of Preset and Clear signal w.r.t. the Clock.

Setup Time
Setup time: the time required for the data to be stable before the clock edge

D1 Q1
FF1
0.4ns

Combo logic

D2 Q2 FF2

4.5ns

CLK
CLK
setup violation
Launch Edge Capture Edge

D2
4.9

setup time

CLK
0 0.3 4.7 5

Hold Time
Hold time: the time required for the data to remain stable after the clock edge
D1 Q1 FF1 CLK1
0.4ns 0.3ns

D2 Q2 FF2 CLK2

CLK1
Launch Edge Capture Edge

D2=Q1

CQ

0.4 Hold violation hold time

CLK2

0.2

0.3 0.5

WHY SETUP & HOLD?

Setup & Hold times are because of the intrinsic delays of the flip flop.

Intrinsic delays are the actual delays of the transistors inside the cell.
Setup and Hold are the times required for charging the capacitances present inside in cell.

Delay of an Inverter
VDD
When Vi = Logic 0 t = Rp * C The delay is decided by the resistance of Pmos and the output capacitance.

Vi Rp

Vo

GND Rp

Rn

The product RC is called the TIME CONSTANT This determines the delay of the cell

When Vo = Logic 1 t = Rn * C

Rn

The delay is decided by the resistance of Nmos and the output capacitance.

How to remove Setup & Hold violations

To solve setup violation 1. optimizing/restructuring combination logic between the flops. 2. Tweak flops to offer lesser setup delay [DFFX1 -> DFFXx] 3. Tweak launch-flop to have better slew at the clock pin, this will make CK->Q of launch flop to be fast there by helping fixing setup violations 4. Play with skew [tweak clock network delay, slow-down clock to capturing flop and fasten the clock to launch-flop] otherwise called as Usefulskews) To solve Hold Violations 1. Adding delay/buffer [as buffer offers lesser delay, we go for spl Delay cells whose functionality Y=A, but with more delay] 2. Making the launch flop clock reaching delayed

STA Critical terms

Critical path: The path between an input and an output with the maximum delay. Recovery time: It is the minimum time that an asynchronous control must be stable before the clock active-edge transition. Removal time: It is the minimum length of time that an asynchronous control must be stable after the clock active-edge transition.

clock recovery time async_in removal time

STA Critical terms cont..

Jitter - Variation in period from clock source (PLL)

Insertion Delay
The delay between the clock root pin and clock sink pin of the flip flop.

Glitch- A glitch is a short-lived fault in a system.

An electrical pulse of short duration that is usually the result of a fault or design error, particularly in a digital circuit

Input Delay

Output Delay

Single Cycle Paths

By default, static timing tools assume all timing paths to be single cycle paths

There could be exceptions defined to the above behavior: Multicycle paths False paths

Multi-Cycle Paths
Those paths that require more than one clock period for execution are called

as multi-cycle paths.
Its essential that multi-cycle paths in the design be identified both for

synthesis and STA.

False Paths
A path that can never be sensitized in the actual circuit These paths are those that are logically/functionally impossible The goal in static timing analysis is to do timing analysis on all true timing paths, these paths are excluded from timing analysis.

Combinational Loop
A

U1
Z

D Q
QB

U0
A Z B

D Q QB

Most STAs cant leave combinational loops in the design, because a race condition will occur. AT

1.1 3.1 5.1

Clock skew
Clock skew (timing skew) Clock signal in synchronous circuits arrives at different components at different times.

clock skew = clock insertion delay of FF1 - clock insertion delay of FF2

Clock skew
Reasons Wire-interconnect length Temperature variations

Variation in intermediate devices

Capacitive coupling Material imperfections. Two Types of Clock Skew: negative skew positive skew Positive skew Occurs when the clock reaches the receiving register later than it reaches the register sending data to the receiving register. Negative skew Is the opposite:- the receiving register gets the clock earlier than the sending register.

Clock Source latency and Network latency

Slack
Slack is generally defined as the difference between the Required Times and Arrival Times at an end point.

Input arrival time of 1 Wire delay 0.2,cell delay 0.5

Cont..

Calculation of RT from level n to level 1 Assumptions: output required time of 2.8 gate delay 0.5, wire delay 0.5

Calculation Of Slack
what is the slack..? Slack =RT -AT

Rectification Of Violations
Swapping pins -swap connections on cumulative pins or among equivalent nets

Resize cell: -up size -down size

fan-out is more capacitance loading is more

Cont..
Buffering - to improve the signal strength - to provide delay

Cloning

- to distribute the load

Cont..
Re-design Fanout Tree:

Cont..
Re-design Fan-in Tree:

Cont..
Decomposition:

Requirements in the perspective of EDA tools

Inputs & Outputs of STA

Inputs Netlist (.v) : The gate level circuit description. Constraints (.sdc) : Synopsys Design Constraint SDF(.sdf) : Standard Delay Format File containing back-annotated delays. OR Standard Parasitic Exchange Format (.spef) : These are the parasitics of the design extracted from physical design tools. Liberty File (.lib): The delay model of every cell in the library. Outputs Reports : The timing paths report which can be used for debugging.

Various tools used in STA

Prime Time (PT) - Synopsys Design Time (DT) - Synopsys Nano Time - Synopsys Path Mill - Synopsys Pearl - Cadence Velocity - Mentor Graphics Eins Timer - IBM Eins TLT - IBM Motive Viewlogic (Now owned by Synopsys) Time Craft - Incentia

Thank You