Cmos Fully Integrated Heterodyne RF Receivers

By Sonam kandalgaonkar

Contents
Introduction Overview of receiver architectures Proposed receiver architecture Conclusion References

Introduction

RF circuit designers are facing an increasing demand for low-cost and small size circuits. Many efforts are ongoing on the integration of RF receivers in low-cost CMOS technologies. Fully integrated 5GHz RF receivers have recently been implemented.

Contd..

Objective: The feasibility of implementing fully integrated heterodyne 5GHz front end receivers in a standard CMOS 0.18m technology. It does not use automatic tuning, DC offset cancellation or calibration circuits. The main idea relies on cascading two image reject notch filters, which results in strong and wide bandwidth image rejection.

Overview of Receiver Architecture

The specifications of 5GHz RF receivers for the 802.11a WLAN applications are summarized in Table 1. Different RF receiver architectures that could meet these requirements have been introduced

Receivers Architecture

Contd..
Figure 1a shows the basic structure of a homodyne receiver. In this scheme, the RF signal is directly down converted by the mixer to baseband. As a result, the image signal is the same as the RF signal, and this type of architecture does not suffer from the image problem. The noise performance of a homodyne receiver is also affected by the 1/f noise. The noise limitations of homodyne receivers can be mitigated by employing architectures with intermediate frequency (IF), such as the Weaver architecture or the image-reject topology.

Weaver architecture
Shown in Fig. 1b, the Weaver receiver exploits the fact that the image and the desired signal are out of phase after down conversion. By down converting the detected RF signal through two different paths using a set of quadrature mixers, cancellation of the image signal can be realized. This technique would offer a suitable solution for implementing 5GHz front-end receivers, only if perfect matching in the gains and phases of the two paths could be achieved 5GHz frequency range, a CMOS Weaver architecture practically generates only between 25 to 35 dB of image rejection.

Image reject mixer based architecture

Shown in Fig. 1c, the image-reject down converter is yet another implementation of an IF homodyne receiver. It uses constant gain broadband 90 degrees phase shifters

Heterodyne structures

Contd..
Typically, a heterodyne receiver employs offchip image reject filters, which increases the cost and the complexity of the overall design. The first IF (2.6GHz) of the receiver is set at half the frequency of the RF input signal (5.2 GHz), while the second IF is chosen to be at baseband. As a result, at the first mixer, the image signal is at very low frequencies (DC), and therefore is heavily attenuated by the antenna and the prefiltering RF blocks.

Proposed Architecture

Contd..
Figure 3 shows the proposed architecture. The signal detected by the antenna is typically in the micro-volts range, which explains the need of preamplifying it before further processing. This task is performed by a low-noise amplifier (LNA) which, in this work, incorporates dual image reject notch filters. For a 5.2GHz receiver with a 1GHz IF, and a mixer frequency of 6.2GHz, the image signal would lie in the vicinity of 7.2GHz. Finally, by adding two notches to the LNA, a wide image rejection bandwidth is obtained, and no extra notch tunning circuits are needed.

Double balanced mixer

Contd..

The mixer used in the front-end is shown in Fig. 5. It is implemented as a double balanced active Gilbert structure. The linearity of the mixer was maximized by grounding the sources of the differential RF input pair. Current sources I1 and I2 were added in order to decrease the biasing currents of the switching transistors M1-M4, thus reducing their noise, while ensuring a proper biasing of the RF differential pair. Finally, a complementary-gm voltage controlled oscillator was used for the LO+ and LO- signals generation .

Simulation results

Summary

Conclusion

A new approach for implementing 5GHz frontend heterodyne receivers was proposed. The circuit does not employ automatic circuits nor off-chip components. Simulation results showed that the specifications for the IEEE 802.11a WLAN standard can be met using a standard CMOS technology.

references
K. Lee and M.N. El-Gamal A very low-voltage (0.8V) CMOS receiver frontend for 5GHz RF applications, Proceedings of the 2002 IEEE International Symposium on Circuits and Systems, pp. 125 -128, May 2002. H. Samavati, H.R. Rategh, and T.H. Lee, A 5GHz CMOS wireless LAN receiver front end, IEEE Journal of Solid-State Circuits, Vol. 35, pp. 765-772, May 2000. J.R. Long, A low-voltage 5.1-5.8-GHz imagereject downconverter RF IC, IEEE Journal of Solid-State Circuits, Vol. 35, pp.1320-1328, Sep. 2000.

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