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Bhautik D. Pandya M.E 1st Sem (VLSI System Design) ME_VSD_110110

1. Introduction 2. Partially Depleted (PD) SOI 3. Parasitic Bipolar Effect 4. Major Design Issue 5. Double Gate MOSFET 6. Features Of FINFET 7. Application 8. Conclusion

The FinFET is a double gate device, one of a number of geometries being introduced to multigate devices, the effects of short channel & reduce drain induced barrier lowering. FinFET are design to use multiple fins to achieve larger channel width. Source/Drain pads contacts, the fin is parallel. As the Fin increased the current through the device increases. E.g. A 5 Fin device has 5 times more current than single Fin device.

What are FinFETs?

A FinFET is like a FET, but the channel has been turned on its edge and made to stand up. FinFETs are candidates as replacements for bulk MOSFETs Better control of short channel effects Double drive current Compact model development Compact model required for circuit design No (public domain) FinFET models available This structure is called FinFET because of its silicon body resembles the back fin of a fish

What are FinFETs?

The ultra-thin-body fully depleted (FD) SOI and the non-planar FinFET device structures promise to be the potential future technology/device choices.

Si Fin

Schematic Diagram
Schematic explaining the parts of a FinFET

Partially Depleted(PD) SOI

The PD floating-body MOSFET was the first SOI transistor generically adopted for high-performance applications, primarily due to device and processing similarities to bulk CMOS device. & it is the first technology for high performance microprocessor applications. The PD SOI device is largely identical to the bulk device, except for the addition of a buried oxide(BOX) layer.

Partially Depleted(PD) SOI

The device offers several advantages for performance/ power improvement: 1) reduced junction capacitance, 2) lower average threshold due to positive V BS during switching. 3) dynamic loading effects,in which the load device tends to be in high VT state during switching. The performance comes at the cost of some design complexity resulting from the floating body of the device, such as 1) parasitic bipolar effect and 2) hysteretic VT variation.

Parasitic Bipoler Effect

In PDSOI an n-p-n transistor is formed with source and drain as emitter & collector respectively and body as the base. The topology involves an OFF transistor with the source & drain voltage set up in HIGH state. When the source is subsequently pulled down large overdrive produced across body-source junction, causing bipolar current to flow through the lateral parasitic bipolar transistor. This may cause circuit failure.

Histeretic Vt Variation
The hysteretic VT variation due to long time constants of various body charging/discharging mechanisms. A commonly used gauge for hysteretic VT variation is the disparity in the body voltages and delays between the so-called first switch(i/p low) and second switch(o/p high) .

Major Design Issues

1. Gate Oxide Tunneling Leakage:- As the gate oxide thickness is scaled to maintain gate control Vt & performance, gate insulator direct current 2. Self heating:- It is dominated by phonon transport in semiconductor & by e transport in metals.(biasing elements, current source) 3. Soft Error Rate:- -generated in SOI devices are subsequently less than in bulk device in presence of buried oxide. ( hits the channel region). 4. Strained-Si channel:- Extending scaling for future high performance applications due to higher mobility.

Introduction To Double Gate CMOS

Double-gate CMOS (DGCMOS) offers distinct advantages for scaling to very short gate lengths. Fabrication of FinFET-DGCMOS is very close to that of conventional CMOS process, with only minor disruptions, offering the potential for a rapid deployment to manufacturing. Planar product designs have been converted to FinFET-DGCMOS without disruption to the physical area, thereby demonstrating its compatibility with todays planar CMOS design methodology and automation techniques.

Double Gate CMOS

Overcoming Obstacles By Doubling Up rapidly progress from 2m to 90 nm rules, two obstacles, namely subthreshold and gate-dielectric leakages(have become the dominant barrier for further CMOS scaling, even for highly leakage-tolerant application such as microprocessors). Double-gate (DG) FETs, in which a second gate is added opposite the traditional (first) gate, have better control over short-channel effects [SCEs]. SCE limits the minimum channel length at which an FET is electrically well behaved.

Double Gate CMOS

Figure schematically illustrates the advantage of DG-FETs.

As the channel length of an FET is reduced, the drain potential begins to strongly influence the channel potential

further decrease of the depletion region XD degrades gate influence on the channel and leads to a slower turn on of the channel region

Double Gate CMOS

In Figure, simulations of the IDSVGS characteristics of DG and SG FETs shows the steeper turn on of the DG-FET, which results from the gate coupling advantage. This property enables the use of lower threshold voltage for the DG-FET for a given offcurrent. As a direct result, higher drive currents at lower power-supply voltages VDD are attainable.

Process Flow Of FinFET


Featurs Of FinFETS
Main Features of Finfet are 1. Ultra thin Si fin for suppression of short channel effects 2. Raised source/drain to reduce parasitic resistance and improve currrent drive 3. Gate_last process with low_T,high_k gate dielectrics 4. Symmetric gates yield great performance,but can built asymmetric gates that target VT

DG devices like Fin FETs offer unique opportunities for microprocessor design. FinFETs have reduced channel and gate leakage currents. - power reductions when converting a planar design to fin FET technology. - Utilizing fin FETs would lead to a reduction in total power, without compromising performance. Another possibility to save power arises when both gates can be controlled separately. The second gate can be used to control the threshold voltage of the device, thereby allowing fast switching on one side and reduced leakage currents when circuits are idle.

FinFETs a necessary semiconductor evolution step because of bulk CMOS scaling problems beyond 32nm. Structure was fabricated by forming the S/D before the gate. Use of the FinFET back gate leads to very interesting design opportunities Rich diversity of design styles, made possible by independent control of FinFET gates, can be used effectively to reduce total active power consumption. Time has arrived to start exploring the architectural trade-offs made possible by switch to FinFETs.