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Unit -1
Logic Gates
Digital Computers - Imply that the computer deals with digital information - Digital information: is represented by binary digits (0 and 1) Functions of gates can be described by : - Truth Table - Boolean Function - Karnaugh Map
GATES
Gates blocks of HW that produce 1 or 0 when input logic requirements are satisfied
Gate
Binary digital input signal
GATE
Combinational Gates
BOOLEAN ALGEBRA
Boolean Algebra * Algebra with Binary(Boolean) Variable and Logic Operations * Boolean Algebra is useful in Analysis and Synthesis of Digital Logic Circuits - Input and Output signals can be represented by Boolean Variables, and - Function of the Digital Logic Circuits can be represented by Logic Operations, i.e., Boolean Function(s) - From a Boolean function, a logic diagram can be constructed using AND, OR, and I Truth Table * The most elementary specification of the function of a Digital Logic Circuit is the Truth Table - Table that describes the Output Values for all the combinations of the Input Values, called MINTERMS - n input variables 2n minterms
Equivalent Circuits
Combinational Circuits
- Multiplexer - Encoder - Decoder - Adders
MULTIPLEXER
4-to-1 Multiplexer Select S1 S0 0 0 0 1 1 0 1 1 Output Y I0 I1 I2 I3
I0
I1 I2 I3 Y
S0 S1
ADDERS
Half Adder
y 0 0 x 0 1
x 0 0 1 1 y 0 1 0 1 c 0 0 0 1 s 0 1 1 0
y 0 1 x 1 0
c = xy
s = xy + xy =x y
x y
Full Adder
Full Adder x y 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 x y cn-1 cn cn-1 cn 0 0 1 0 0 0 1 1 0 0 1 1 0 1 1 1 s 0 1 1 0 1 0 0 1 y
0 0 0 1 c n-1 1 1 0 1
y
1 0 c n-1 1 0
1 0
0 1
cn
Encoder
Flip Flops
D Flip Flop
Latch
A latch is a kind of bistable multivibrator, an electronic circuit which has two stable states and thereby can store one bit of information. Today the word is mainly used for simple transparent storage elements, while slightly more advanced non-transparent (or clocked) devices are described as flip-flops. Informally, as this distinction is quite new, the two words are sometimes used interchangeably.
S - R Latch
SR latch operation S 0 The symbol for an SR latch. 0 R 0 1 Action Keep state Q=0
Flip Flops
D-LATCH
D-Latch Forbidden input values are forced not to occur by using an inverter between the inputs
D Q E (enable) Q D(data) Q
E
D
Q
Q
D 0 1
Q(t+1) 0 1
EDGE-TRIGGERED FLIP FLOPS or Characteristics - State transition occurs at the rising edge
falling edge of the clock pulse Latches
Flip Flops
Registers
A0 Q Clock I0 I1 I2
D C
Sequential Circuits
A1 Q
D C
A2 Q
D C
A3 Q
D C
Shift Registers
Serial Input Clock D Q C D Q C D Q C
I3 Serial Output
D Q C
A0 Q
D C
A1 Q
D C
A2 Q
D C
A3 Q
D C
4x1 MUX
4x1 MUX
4x1 MUX
4x1 MUX
Clock
S0S1 SeriaI I0
Input
I1
I2
Serial I3 Input
Ring counter
Johnson Counter