UNIT-II

Contents
Basic electrical properties of MOS Circuits
I
ds
V
ds
relationships
MOS transistor threshold voltage
g
m
, g
ds
, figure of merit
o

Pass transistor
NMOS Inverter
Various Pull Ups
CMOS Inverter analysis and design
Bi-CMOS Inverter
The whole concept of the MOS transistor
evolves from the use of a voltage on the
Gate to induce a charge in the channel
The charge moves from the S to D under
the influence of an electric field V
ds
The I
ds
is dependent on both the V
gs
and
V
ds
.
) 1 .......(
) (
) ( arg
t Time Transit Electron
Q channel in induced e Ch
I I
c
sd ds
= =
) (
) (
v Velocity
L channel of Length
sd
= t

But, velocity,
ds
E v =
Where,
= electron or hole mobility (surface)
E
ds
= electric field (drain to source)
) 2 ..( ..........
2
ds
sd
ds
ds
ds
V
L
L
V
v
Theref ore
L
V
E
Now

=
=
=
The typical values of at room
temperature are :

n
= 650 cm
2
/V sec

p
=240 cm
2
/V sec
The non saturated region:
The charge induced in the channel is due
to the voltage difference between the gate
and the channel, V
gs
The voltage along the channel varies
linearly with the distance X from the
Source due to the IR drop in the channel.
Assume that the device is not saturated
then the average value is V
ds
/2.
The effective gate voltage V
g
=V
gs
-V
th.
The threshold voltage is the voltage
needed to invert the charge under the gate
and establish the channel
The charge per unit area = E
g

ins

o



The charge per unit area= E
g

ins

o
WL
Where
E
g
= average electric field gate to channel

ins
=relative permittivity of insulation between
the gate and the channel ( 8.85x10
-14
F cm
-1
)

o
= permittivity of free space (4.0 for SiO
2
)

( )
thickness oxide the is D
where
D
V
V V
E
Now
ds
th gs
g
(

=
2
,
( ) ) 3 ......(
2
(

=
ds
t gs
o ins
c
V
V V
D
WL
Q
c c
Now, combine equations (2) and (3) in equation (1)
( )
) 4 ......( ..........
2
ds
ds
t gd
o ins
ds
V
V
V V
L
W
D
I
(

=
c c
( ) ) 4 ...( ..........
2
2
(

=
ds
ds t gs ds
V
V V V
L
W
K I
In the non-saturated region where V
ds
< V
gs
-V
t
and
K=
ins

o
/D
The factor W/L is of course contributed by the
geometry and it is common practice to write:


So that,


L
W
K = |
( ) ) ( 4 ..........
2
2
a
V
V V V I
ds
ds t gs ds (

= |
WL
C
K
and
D
WL
C
ce capaci channel gate The
g
o ins
g

c c
=
=
tan /
Now

( ) ) ( 4 .......
2
2
2
b
V
V V V
L
C
I
ds
ds t gs
g
ds (

=

It is sometimes convenient to use gate capacitance per unit
area C
o
(C
ox
) rather than C
g
in this and other expressions.

C
g
=C
o
WL
( ) ) ( 4 .......
2
2
c
V
V V V
L
W
C I
write also may We
ds
ds t gs o ds (

=
The saturated Region
Saturation begins when V
ds
= V
gs
-V
t
At this point the IR drop in the channel
equals the effective gate to channel
voltage at the drain
The current remains fairly constant as V
ds

increases further.
) ( 5 .. .......... ) (
2
) ( 5 ....... .......... ) (
2
) ( 5 . .......... .......... ) (
2
) 5 .......( ..........
2
) (
2
2
2
2
2
c V V
L
W
C I
or
b V V
L
C
I
or
a V V I
or
V V
L
W
K I
t gs o ds
t gs
g
ds
t gs ds
t gs
ds
=
=
=

|
MOS Transistor Threshold Voltage
The electrical Gate structure consists of
charges stored in the dielectric layers and
in the surface to surface interfaces as well
as in the substrate itself.
To switch ON the enhancement MOS
transistor, apply sufficient Gate voltage to
neutralize these charges and enabling the
underlying silicon to undergo an inversion
due to the electric field from the gate.
Derivation -II
Consider a semiconductor bar carrying a
current I
Let the charge density along the direction
of current is Q
d
Let the velocity of charge is v
Then
I=Q
d
.v..(1)
Consider an NMOS whose S and D are
connected to ground
The onset of inversion occurs at V
GS
=V
TH
The inversion charge density produced by the
gate oxide capacitance is proportional to V
GS
-
V
TH
.
For V
GS
V
TH
any charge placed on the gate
must be mirrored by the charge in the channel,
results in a uniform channel charge density.
Q
d
= WC
OX
(V
GS
-V
TH
)
C
OX
is multiplied by W to represent the total
capacitance per unit length
Now let the D voltage be greater than zero.
Now the channel potential varies from 0 at the S
to V
D
at D
The local voltage difference between the G and
the channel varies from V
G
to V
G
-V
D
.
The charge density at a point x along the
channel is:
Q
d
(x)= WC
OX
[V
GS
- v(x)-V
TH
]

V(x) is the charge potential at x
The current is:
I
D
= -WC
OX
[V
GS
-V(X)- V
TH
]v

The negative sign is because the charge
carriers are negative
v=E




and E(x)= - dV(x)/dx
Mobility of charge carriers
Electric field
]
2
1
) [(
) ( [
sin
) (
] ) ( [
2
0 0
DS
DS TH GS ox n D
V V
V
TH GS n ox
L x
x
D
n TH GS OX D
V V V V
L
W
C I
V x V V WC dx I
conditions boundary g u
dx
x dV
V x V V WC I
DS
=
=
=
} }
=
=
=
=

The above equation is a parabola

The current capability of the device increases
with V
GS

Calculating it can be seen that the peak

current occurs at V
DS
=V
GS
-V
TH
.

DS
D
V
I
c
c
2
max ,
) (
2
1
TH GS ox n D
V V
L
W
C I =
We call the V
GS
-V
TH
as over drive voltage

If V
DS
V
GS
-V
TH
it is called Triode Region
If V
DS
2(V
GS
-V
TH
), then,



As seen the drain current is a linear function of
the drain source voltage
The linear relationship implies that the path from
the source to the drain can be represented by a
resistor.
DS TH GS ox n D
V V V
L
W
C I ) ( ~
) (
1
TH GS ox n
ON
V V
L
W
C
R

A MOSFET can operate as a Resistor whose value is

controlled by the Over drive voltage Deep Triode Region
Now if the D-S voltage exceeds V
GS
-V
TH
In reality the drain current does not follow
the parabolic behavior for V
DS
> V
GS
-V
TH
ID becomes relatively constant, the device
operates in the saturation region
As we know the charge density of the
inversion layer is proportional to the V
GS
-
V(x)-V
TH
If V(x) approaches V
GS
-V
TH
then Q
d
(x)
drops to zero.
If VDS is slightly greater than V
GS
-V
TH,
then
the inversion layer stops at x L.
The channel is pinched OFF

Pinch OFF
x=0 x=L
As V
DS
increases further, the point at
which the Q
d
equals zero gradually moves
towards the Source.

Pinch OFF
x=0 x=L
note
Switching a depleted MOS transistor from
the ON state to the OFF state consists in
applying enough voltage to the gate to add
to the stored charge and invert the n
implant region to p.
The threshold voltage V
th
may be expressed as:

area gate unit per ce capaci C
erf ace SiO Si at density e ch Q
oxide the beneath layer
depletion the in area unit per e ch the Q
where
C
Q Q
V
O
SS
B
fN
O
SS B
ms th
tan
int : arg
arg
2
2
=
=
=
+

= | |
Si bulk and
surf ace inverted between potential level Fermi
Si gate between dif f erence f unction work
fN
ms
=
=
|
| &
To evaluate V
th
, each term is determined as
follows:

2 8
2
/ 10 ) 8 5 . 1 (
ln
/ ) 2 ( 2
m coulomb to Q
Volts
n
N
q
kT
m coulomb V qN Q
SS
i
fN
SB fN Si O B

=
=
+ =
|
| c c
K joule t cons s Boltzmann k
cm
ion concentrat electron rinsic n
silicon of y permitivit relative
substrate the in
ion concentrat impurity N
coulomb q
voltage bias substrate V
o
i
Si
SB
/ 10 4 . 1 tan '
) / 10 6 . 1 (
int
7 . 11
10 6 . 1
23
3 10
19

= =

=
~
=
=
=
=
c
Body Effect on threshold voltage:
This is also considered as the substrate is
biased w.r.t. the source
Increasing VSB causes the channel to be
depleted of charge carriers
This increases the threshold volatge
doping substrate
the on depends which t cons a is
V V
by given is V in Change
SB th
th
tan
) (
2
1

= A
If the substrate is lightly doped, the body effect will
be smaller.
0 ) 0 (
) ( 2 ) 0 (
2
1
=
|
|
.
|

\
|
+ =
SB th
SB Si o
o ins
th th
V f or voltage threshold the is V
where
V QN
D
V V c c
c c
g
m
, g
ds
, figure of merit
o

Trans conductance expresses the relationship
between the output current Ids and the input
voltage V
gs
.
It is defined as:

ant const V
V
I
g
ds
gs
ds
m
= =
o
o
To find an expression for g
m
in terms of circuit
and transistor parameters consider the charge
in channel Q
c
such that

ds
c
ds
ds
c
Q
I
current in change the
time transit the is where
I
Q
t
o
o
t
t
=
=
2
2
L
V Q
I
V
L
Now
ds c
ds
ds
ds
o

t
= c
=
2
arg
L
V V C
I
that so
V C Q
e ch in change but
ds gs g
ds
gs g c
o
o
o o
=
=
2
L
V C
V
I
g
Now
ds g
gs
ds
m

o
o
= =
) (
) (
) (
2
th gs m
th gs
o ins
m
o ins
g
th gs
g
m
th gs ds
V V g
or
V V
L
W
D
g
D
WL
C and
V V
L
C
g
V V V
saturation in
=
=
=
=
=
|
c c
c c

It is possible to increase the g

m
of a MOS
device by increasing its width
This will also increase the input
capacitance and area occupied.
A reduction in the channel length results in
an increase in
0
owing to the higher g
m
.
The gain of the MOS device decreases
owing to the strong degradation of the
output resistance=1/g
ds
.
)
1
(
2
L
I
V
I
g
ds
gs
ds
ds
o
o
o
= =
Figure of Merit
The indication of the frequency response is obtained from the
parameter
0










This shows that the switching speed depends on the gate voltage
above threshold and on carrier mobility and inversely proportional
to the square of the channel length.
Note: A fast circuit requires that g
m
is as high as possible.
sd
t gs
g
m
V V
L C
g
t

=
1
) (
2
0
=
= =
More.
In a saturated device the integral on the left is
taken from x=0 to x=L, L is the point at which
the Q
d
drops zero.
The integral on the right is taken from V(x)=0 to
V(x)=V
GS
-V
TH
.



I
D
is relatively independent of V
DS
.
2
) (
' 2
1
TH GS ox n D
V V
L
W
C I =
Example-1
For the arrangement shown in the figure
below, plot the on-resistance of as a
function of V
G
. Assume
n
C
ox
=50 A/V
2

and V
TH
=0.7V. Note that the drain terminal
is open.

V
G
M
1
1V
Solution..
The Drain terminal is open, I
D
=0.
If the device is ON, it operates in the deep triode
region.
For V
G
<1 V+V
TH
, M1 is OFF, R
ON
=
For V
G
> 1V+V
TH
,

) 7 . 0 1 ( 10 / 50
1
2
V V V V A
R
G
on

=

Trans Conductance
A saturated MOS can be used as a
constant current source connected
between the drain and source.
The current produced is in response to the
gate source overdrive voltage
Then a figure of merit can be defined that
indicates how well a device converts a
voltage to a current.
Specifically we define the figure of merit as the
change in the drain current divided by the change
in the gate-source voltage- Transconductance
(g
m
)


) (
|
tan ,
TH GS ox n
t cons DS
GS
D
m
V V
L
W
C
V
V
I
g
=
c
c
=

g
m
represents the sensitivity of the device
For high g
m
, a small change in the V
GS

results in a large change in the I
D
.
g
m
in the saturation region is equal to the
inverse of the R
on
in the deep triode
region.

g
m
can also be represented as

TH GS
D
D ox n m
V V
I
I
L
W
C g

=
=
2
2
MOS as Capacitor
If the S,D and Bulk of the NMOS are
grounded and the Gate voltage rises, an
inversion layer begins to form for V
GS
V
TH
.
For 0<V
GS
<V
TH
,the device operates in the
sub threshold region.


+ + + + + + + + + + +
+ + + + + + + + + + +
0
0
V
G
The transistor can be considered as two terminal
device
The capacitance can be examined for different
gate voltages.
First let the gate source voltage be very
negative.
This negative gate voltage attracts the holes in
the substrate to the oxide interface.
The MOSFET operates in the accumulation
region.
The two terminal device can be viewed as
a capacitor having a unit area capacitance
of C
ox
, because the two plates of the
capacitor are separated by t
ox
(D)
As V
GS
rises, the density of holes at the
interface falls.
The device enters the weak inversion.
In this mode the capacitance consists of
the series combination of C
ox
and C
dep
.
As V
GS
exceeds the V
TH
the oxide silicon
interface sustains a channel and the unit
area capacitance returns to C
ox
.
Accumulation
Strong Inversion
V
TH
C
GS
V
GS
Pass Transistor
The MOS transistors have isolated nature
of the gate (unlike bipolar transistors)
MOS can be used as a switches in series
This application of MOS Transistor is
called the Pass Transistor.

nMOS Pass Transistor Logic
1 Transfer
nMOS Pass Transistor
Logic 0 Transfer
PASS TRANSISTORS IN SERIES
nMOS Inverter
An inverter is the basic requirement for
producing a complete range of logic circuits.
The basic inverter circuit requires a transistor
with the Source connected to ground and a load
resistor of some sort connected from the Drain
to the positive supply rail V
DD
.
The output is taken from the drain and the input
applied between Gate and Ground.
Note: Resistors are not conveniently produced
on the silicon, use depletion mode transistor
instead.
V
DD
V
out
GND
V
in
With no current drawn from the output, the
current I
ds
for both the transistors must be
equal.
For the depletion mode transistor, the gate
is connected tot the source so it is always
on.
Only the characteristic curve V
gs
=0 is
relevant.
In this configuration the depletion mode
device is called the pull-up (p.u.) and the
enhancement mode device is called the
pull-down (p.d.) transistor.