IMPACT OF MOSFET PARAMETERS ON ITS PARASITIC CAPACITANCES

PRESENTED BY
S.GOVINDA ROLL NO:3122603

CONTENTS:
HOW PARASITIC CAPACITANCES ARE FORMED CALCULATION OF PARASITIC CAPACITANCES DEPENDECY ON MOSFET PARAMETERS CONCLUSIONS REFERENCES

NEED TO KNOW ABOUT PARASITIC CAPACITANCES

Consider an amplifier frequency response From our small signal model the gain should be constant at all frequencies But it is decreasing with increasing of frequency

HOW PARASITIC CAPACITANCES ARE FORMED?

These capacitances are the result of charge stored in the device. The stored charges are
The inversion charge ( Q i ) in the channel region
The bulk charge (Q b ) in depletion region underlying the channel The gate charge( Q g at gate terminal ) The charges due to source/drain pn junctions

THE CAPACITANCES DUE TO THE STORED CHARGES IS SHOWN IN FIG.

THESE CAPACITANCES DIVIDED INTO TWO PARTS INTRINSIC PART EXTRINSIC PART
INTRINSIC PART: CHARGES :

Qi , Q b & QG
CAPACITANCES:

CGS , CGD & CGB

EXTRINSIC PART: The source/drain pn junction with bulk leads to junction capacitances The overlap between source/drain and gate leads to overlap capacitances These capacitances are called extrinsic capacitances or parasitic capacitances

JUNCTION CAPACITANCE
These capacitances are due to reverse biased pn junctions. Three dimensional shape of n+ will form five planer pn-junctions with the surrounding p-type substrate indicated with numbers from 1 to 5.

To calculate the depletion capacitance of a reverse-biased abrupt pn-junction, firstly we consider the depletion region thickness, which is

Where
Xd

In normal operating region pn-junctions are reverse-biased, therefore amount of electric charge which is stored in depletion region is found by:

Where a indicates junction area

The junction capacitances associated with the depletion region are defined as:

dQ J j dV

After differentiating with V

The zero-bias junction capacitance per unit area is defined as CJ0

The problem of calculating the junction capacitances value under changing bias conditions can be simplified if we calculate a large-signal average junction capacitance as in the case of logic circuit

Equivalent large-signal capacitance can be defines as

If m=1/2 we have

OVERLAP CAPACITANCES
Assuming that both the source and the drain diffusion regions are identically, the overlap capacitances can be calculated as:

CGSOV WLov COX CGDOV WLov COX

Plot of the overlap capacitance (including fringing) versus overlap distance using parallel plate capacitance formula and exact numerical solution

MOSFET overlap capacitance can be approximated by the parallel combination of Direct overlap capacitance C1, between the gate and the source/drain Fringing capacitance C 2 , on the outer side between the gate and source/Drain Fringing capacitance C , on the channel side (inner side) between the gate and side wall of the source/drain junction
3

Intrinsic capacitances CGS , CGD & CGB depend on bias conditions (they are voltage-dependent) as: TRIODE REGION: When MOSFET is operating in triode region, channel is considered to be uniform from the source to the drain. Therefore, in this case the gate-channel capacitance will be WLCOX and can be modelled as
CGS CGD AND CGB 0 1 WLCOX 2

SATURATION REGION When MOSFET is operating in saturation mode, the channel has tapered shape and is pinched off at or near the drain end, thus the channel will not be uniform.
In this case the gate-channel capacitance will be approximately 2 WLC and can be modelled as
3
OX

2 CGS WLCOX 3 , , CGD 0 & CGB 0

CUT-OFF REGION When MOSFET is in cut-off mode, channel is not inducted, thus in this case capacitive effect can be modeled as:

CGS 0, CGD 0 & CGB WLCOX

DEPENDENCY ON L:
When channel length is reduced by keeping supply voltage constant The maximum electric field experienced by the carriers in the channel region near the drain end is increased Leads impact ionization Carriers enter into the oxide

DEPEDENCE ON AREA ( W*L):

The dependence of equivalent capacitance from the width of drain regions (w) for parametrical length value(y) and depth value of drain

CONCLUSIONS: We see the dependence of the gate capacitive effect and the junction parasitic capacitance on the MOSFET dimensions.

Therefore, we can conclude that the value of the gate capacity effect can be reduced by smaller values of channel dimensions (w and L) as per technological process possibilities. Furthermore, the parasitic junction capacitances will be smaller if the dimensions of drain and source regions are smaller.
To achieve the higher speed of operation, the dimensions of MOSFET device should be as smaller as possible.

REFERENCES: [1] Neamen, D. A. Electronic Circuit Analysis and Design, 2th edition, New York: McGraw-Hill, 2001. [2] Sedra, A. C. and K. C. Smith, Microelectronic Circuits, 5th edition, Oxford University Pres 2004 [3] Narain Arora, MOSFET Modeling For VLSI Simulation Theory and Practice, World Scientific,2007 [4] Donald A. Neamen ,Semiconductor Physics and Devices Basic Principles, McGraw-Hill,2003 [5] R. Shrivastava and K. Fitzpatrick, A simple model for the overlap capacitance of a VLSI MOS device, IEEE Trans. Electron Devices, vol. ED-29, pp. 18701875, 1982 [6] M. I. Elmasry, Capacitance calculations in MOSFET VLSI, IEEE Electron Device Lett., vol. EDL-3, pp. 67, 1982.