Chapter 10

Digital Integrated Circuits
A Design Perspective
Jan M. Rabaey Anantha Chandrakasan Borivoje Nikoli
Timing Issues
January 2003
EE141 Digital Integrated
Circuits2nd
Timing Issues
Synchronous Timing
CLK In R1 Cin Combinational Logic Cout R2
Out
Circuits2nd
Timing Issues
Timing Definitions
Circuits2nd
Timing Issues
Latch Parameters
D Q Clk
T
Clk D tc-q PWm thold td-q tsu
Delays can be different for rising and falling data transitions

Circuits2nd
Timing Issues
Register Parameters
D Q Clk
T
Clk D tsu Q tc-q Delays can be different for rising and falling data transitions
thold
Circuits2nd
Timing Issues
Clock Uncertainties
4 Power Supply 3 Interconnect Devices 6 Capacitive Load 7 Coupling to Adjacent Lines
5 Temperature 1 Clock Generation
Sources of clock uncertainty

Circuits2nd
Timing Issues
Clock Nonidealities
Clock skew
Spatial variation in temporally equivalent clock edges; deterministic + random, tSK
Clock jitter
Temporal variations in consecutive edges of the clock signal; modulation + random noise Cycle-to-cycle (short-term) tJS Long term tJL
Variation of the pulse width

Important for level sensitive clocking
Circuits2nd
Timing Issues
Clock Skew and Jitter

Clk
tSK
Clk
tJS
Both skew and jitter affect the effective cycle time Only skew affects the race margin
Circuits2nd
Timing Issues
Clock Skew
# of registers Earliest occurrence of Clk edge Nominal /2 Latest occurrence of Clk edge Nominal + /2
Insertion delay Max Clk skew
Clk delay
Circuits2nd
Timing Issues
Positive and Negative Skew

In CLK R1 D Q tCLK1 delay (a) Positive skew R1 D Q tCLK1 delay
(b) Negative skew
10
Combinational Logic
R2 D Q tCLK2
delay Combinational Logic
R3
D Q
tCLK3
In
Combinational Logic
R2 D Q tCLK2 delay Combinational Logic
R3 D Q tCLK3 CLK
Circuits2nd
Timing Issues
Positive Skew
TCLK + d CLK1 1
d
TCLK
CLK2
2
d + th
Launching edge arrives before the receiving edge

11
Circuits2nd
Timing Issues
Negative Skew
TCLK + d
CLK1
TCLK
CLK2
Receiving edge arrives before the launching edge

12
Circuits2nd
Timing Issues
Timing Constraints
In R1
D Q
R2 Combinational Logic
D Q
CLK tc - q
tCLK1 tlogic
tlogic, cd tc - q, cd tsu, thold
tCLK2
Minimum cycle time: T - = tc-q + tsu + tlogic

Worst case is when receiving edge arrives early (positive )
Circuits2nd
Timing Issues
13
Timing Constraints
In R1
D Q
R2 Combinational Logic
D Q
CLK tc - q
tCLK1 tlogic
tlogic, cd tc - q, cd tsu, thold
tCLK2
Hold time constraint: t(c-q, cd) + t(logic, cd) > thold +

Worst case is when receiving edge arrives late Race between data and clock
Circuits2nd
Timing Issues
14
Impact of Jitter
CLK
TC LK
t j itter -tji tte r
In
REGS
Combinational Logic t log ic t log ic, cd
CLK tc-q , tc-q, ts u, thold tjitter
cd
Circuits2nd
Timing Issues
15
Longest Logic Path in Edge-Triggered Systems

TSU Clk TClk-Q TLM T
TJI +
Latest point of launching
Earliest arrival of next cycle
Circuits2nd
Timing Issues
16
Clock Constraints in Edge-Triggered Systems

If launching edge is late and receiving edge is early, the data will not be too late if:
Tc-q + TLM + TSU < T TJI,1 TJI,2 -

Minimum cycle time is determined by the maximum delays through the logic
Tc-q + TLM + TSU + + 2 TJI < T

Skew can be either positive or negative
Circuits2nd
Timing Issues
17
Shortest Path
Earliest point of launching
Clk
TClk-Q TLm
Clk
TH
Data must not arrive before this time
Nominal clock edge
Circuits2nd
Timing Issues
18
Clock Constraints in Edge-Triggered Systems

If launching edge is early and receiving edge is late:
Tc-q + TLM TJI,1 < TH + TJI,2 +

Minimum logic delay
Tc-q + TLM < TH + 2TJI+
Circuits2nd
Timing Issues
19
How to counter Clock Skew?

Negative Skew
REG
REG
REG
REG
log
Out
In
Positive Skew Clock Distribution
Data and Clock Routing

20
Circuits2nd
Timing Issues
Flip-Flop Based Timing

Skew
Logic delay TSU
Flip-flop delay
Flip -flop
TClk-Q
=0
Logic
=1
Representation after M. Horowitz, VLSI Circuits 1996.

Circuits2nd
Timing Issues
21
Flip-Flops and Dynamic Logic

Logic delay TSU TClk-Q TClk-Q TSU
=0
=1
=0
=1
Logic delay Precharge
Evaluate
Evaluate
Precharge
Flip-flops are used only with static logic

Circuits2nd
Timing Issues
22
Latch timing
tD-Q
D Clk Q
When data arrives to transparent latch Latch is a soft barrier
tClk-Q
When data arrives to closed latch Data has to be re-launched
Circuits2nd
Timing Issues
23
Single-Phase Clock with Latches

Latch
Logic
Tskl Clk
Tskl
Tskt
Tskt
PW P
Circuits2nd
Timing Issues
24
Latch-Based Design
L1 latch is transparent when = 0
L2 latch is transparent when = 1
L1 Latch
Logic
L2 Latch
Logic
Circuits2nd
Timing Issues
25
Slack-borrowing
In L1 D Q a CLB_A t p d,A b L2 D Q c CLB_B t p d,B L1 d D Q e
CLK1
CLK2 TC LK
CLK1
CLK1
CLK2 slack passed to next stage t pd,A a valid tD Q tpd,B t DQ e valid d valid
26
b valid c valid
Circuits2nd
Timing Issues
Latch-Based Timing
Static logic
Skew
L1 Latch
Logic
L2 Latch
=1
L1 latch
L2 latch
Logic
Long path
=0
Can tolerate skew!

Short path
Circuits2nd
Timing Issues
27
Clock Distribution
H-tree
CLK
Clock is distributed in a tree-like fashion

Circuits2nd
Timing Issues
28
More realistic H-tree
[Restle98]
Circuits2nd
Timing Issues
29
The Grid System

GCL K Driver
Driver
Driver
GCLK
GCLK
No rc-matching Large power

Driver GCL K
Circuits2nd
Timing Issues
30
Example: DEC Alpha 21164

Clock Frequency: 300 MHz - 9.3 Million Transistors Total Clock Load: 3.75 nF Power in Clock Distribution network : 20 W (out of 50) Uses Two Level Clock Distribution: Single 6-stage driver at center of chip Secondary buffers drive left and right side clock grid in Metal3 and Metal4 Total driver size: 58 cm!
Circuits2nd
Timing Issues
31
21164 Clocking
tcycle= 3.3ns trise = 0.35ns tskew = 150ps

Clock waveform
final drivers
2 phase single wire clock, distributed globally 2 distributed driver channels

Reduced RC delay/skew Improved thermal distribution 3.75nF clock load 58 cm final driver width
pre-driver
Location of clock driver on die

Local inverters for latching Conditional clocks in caches to reduce power More complex race checking Device variation
Timing Issues
32
Circuits2nd
Clock Drivers
Circuits2nd
Timing Issues
33
Clock Skew in Alpha Processor
Circuits2nd
Timing Issues
34
EV6 (Alpha 21264) Clocking 600 MHz 0.35 micron CMOS

tcycle= 1.67ns
trise = 0.35ns Global clock waveform
tskew = 50ps 2 Phase, with multiple conditional buffered clocks

2.8 nF clock load 40 cm final driver width

PLL
Local clocks can be gated off to save power Reduced load/skew Reduced thermal issues Multiple clocks complicate race checking
Timing Issues
35
Circuits2nd
21264 Clocking
Circuits2nd
Timing Issues
36
EV6 Clock Results

ps 5 10 15 20 25 30 35 40 45 50 GCLK Skew
(at Vdd/2 Crossings)
ps 300 305 310 315 320 325 330 335 340 345 GCLK Rise Times
(20% to 80% Extrapolated to 0% to 100%)
Circuits2nd
Timing Issues
37
EV7 Clock Hierarchy

Active Skew Management and Multiple Clock Domains
NCLK (Mem Ctrl)
+ widely dispersed drivers

DLL
DLL
DLL
+ DLLs compensate static and lowfrequency variation + divides design and verification effort
L2L_CLK (L2 Cache)
L2R_CLK (L2 Cache)
PLL
GCLK (CPU Core)
- DLL design and verification is added work
SYSCLK
+ tailored clocks
Timing Issues
38
Circuits2nd
Self-timed and Asynchronous Design

Functions of clock in synchronous design 1) Acts as completion signal 2) Ensures the correct ordering of events Truly asynchronous design 1) Completion is ensured by careful timing analysis 2) Ordering of events is implicit in logic Self-timed design 1) Completion ensured by completion signal 2) Ordering imposed by handshaking protocol
Circuits2nd
Timing Issues
39
Synchronous Pipelined Datapath

In
R1 D Q tpd,reg
Logic Block #1 tpd1
R2 D Q
Logic Block #2 tpd2
R3 D Q
Logic Block #3 tpd3
R4 D Q
CLK
Circuits2nd
Timing Issues
40
Self-Timed Pipelined Datapath

Req Ack HS Start Req Ack Done HS Start Req Ack Done HS Start Req ACK Done
In
R1
F1
R2
F2
R3
F3
Out
tpF1
tpF2
tpF3
Circuits2nd
Timing Issues
41
Completion Signal Generation

LOGIC In NETWORK Out
Start
DELAY MODULE
Done
Using Delay Element (e.g. in memories)
Circuits2nd
Timing Issues
42
Completion Signal Generation
Using Redundant Signal Encoding
Circuits2nd
Timing Issues
43
Completion Signal in DCVSL

VDD Start VDD B0 Done
B1
B0
In1 In 1 In 2 In 2
B1
PDN
PDN
Start
Circuits2nd
Timing Issues
44
Self-Timed Adder
VDD Start C0 C0 Start VDD Start C0 C0 Start (a) Differential carry generation
45
VDD C3 P3 G3 Start C4 C4 C4 C3 C2 C1 Start Done C4 C3 C2 C1
P0 G0
C1
P1 G1
C2
P2 G2
P0 K0
C1
P1 K1
C2
P2 K2
C3
P3 K3
C4
C4
(b) Completion signal
Circuits2nd
Timing Issues
Completion Signal Using Current Sensing

Input Register
VDD Static CMOS Logic
Start Output A toverlap

A Done Done B tMDG
Inputs Start
tdelay
GNDsense
Current Sensor
tpd-NOR
valid
Min Delay Generator
B Output
Circuits2nd
Timing Issues
46
Hand-Shaking Protocol
Two Phase Handshake
Circuits2nd
Timing Issues
47
Event Logic The Muller-C Element

A A
C F
B 0 1 0 1
Fn+1 0 Fn Fn 1
0 0 1 1
(a) Schematic
VDD A A B S R (a) Logic Q F B VDD B
(b) Truth table

VDD
F
B
B B (b) Majority Function (c) Dynamic
Circuits2nd
Timing Issues
48
2-Phase Handshake Protocol
Advantage : FAST - minimal # of signaling events (important for global interconnect) Disadvantage : edge - sensitive, has state
Circuits2nd
Timing Issues
49
Example: Self-timed FIFO

In Out R1 En Reqi C Acki C C Acko Done Req0 R2 R3
All 1s or 0s -> pipeline empty Alternating 1s and 0s -> pipeline full

Circuits2nd
Timing Issues
50
2-Phase Protocol
Circuits2nd
Timing Issues
51
Example
From [Horowitz]
Circuits2nd
Timing Issues
52
Example
Circuits2nd
Timing Issues
53
Example
Circuits2nd
Timing Issues
54
Example
Circuits2nd
Timing Issues
55
Also known as RTZ Slower, but unambiguous

Circuits2nd
Timing Issues
56

Implementation using Muller-C elements
Circuits2nd
Timing Issues
57
Self-Resetting Logic
completion detection (L1) completion detection (L2) completion detection (L3)
Precharged Logic Block (L1)
VDD
int
out
A B C
Post-charge logic
Circuits2nd
Timing Issues
58
Clock-Delayed Domino
GND
CLK1
VDD
CLK2 (to next stage)
Q1 (also D2)
D1
Pulldown Network
Circuits2nd
Timing Issues
59
Asynchronous-Synchronous Interface
fin Asynchronous system Synchronous system fCLK Synchronization
Circuits2nd
Timing Issues
60
Synchronizers and Arbiters

Arbiter: Circuit to decide which of 2 events occurred first Synchronizer: Arbiter with clock as one of the inputs Problem: Circuit HAS to make a decision in limited time - which decision is not important Caveat: It is impossible to ensure correct operation But, we can decrease the error probability at the expense of delay
Circuits2nd
Timing Issues
61
A Simple Synchronizer
CLK int I1 Q I2 CLK
Data sampled on rising edge of the clock Latch will eventually resolve the signal value, but ... this might take infinite time!
Circuits2nd
Timing Issues
62
Synchronizer: Output Trajectories

2.0
Vout
1.0 0.0 0
100
time [ps]
200
300
Single-pole model for a flip-flop
Circuits2nd
Timing Issues
63
Mean Time to Failure
Circuits2nd
Timing Issues
64
Example
Tf = 10 nsec = T Tsignal = 50 nsec tr = 1 nsec t = 310 psec VIH - VIL = 1 V (VDD = 5 V)
N(T) = 3.9 10-9 errors/sec MTF (T) = 2.6 10 8 sec = 8.3 years MTF (0) = 2.5 sec
Circuits2nd
Timing Issues
65
Influence of Noise
Uniform distribution around VM p(v)
logarithmic reduction T
VIL
VIH
Initial Distribution
Still Uniform
Low amplitude noise does not influence synchronization behavior

Circuits2nd
Timing Issues
66
Typical Synchronizers
2 phase clocking circuit
Q 1 2
Using delay line
Circuits2nd
Timing Issues
67
Cascaded Synchronizers Reduce MTF
In Sync
f
O1 Sync
O2 Sync
Out
Circuits2nd
Timing Issues
68
Arbiters
Req1 Req2 Arbiter Ack1 Req1 Ack2
Ack1
A B
Ack2
(a) Schematic symbol Req1 Req2 A B metastable Ack1 VT gap
Req2
(b) Implementation
(c) Timing diagram
Circuits2nd
Timing Issues
69
PLL-Based Synchronization
Chip 1 Data Digital System fsystem = N x fcrystal PLL fcrystal , 200<Mhz
Crystal Oscillator reference clock
Chip 2 Digital System
Divider
PLL Clock Buffer
Circuits2nd
Timing Issues
70
PLL Block Diagram

Reference clock
Up
Phase detector
Down
Charge pump
Loop filter
vcont
VCO
Local clock
Divide by N
System Clock
Circuits2nd
Timing Issues
71
Phase Detector
Output before filtering
Transfer characteristic
Circuits2nd
Timing Issues
72
Phase-Frequency Detector
Rst D Q A Rst D Q DN
B A B
B
UP
B
UP = 0 DN = 1 UP = 0 DN = 0 UP = 1 DN = 0 A
(a) schematic
A B UP DN
(b) state transition diagram

A
B
UP DN (c) Timing waveforms
Circuits2nd
Timing Issues
73
PFD Response to Frequency

A B
UP
DN
Circuits2nd
Timing Issues
74
PFD Phase Transfer Characteristic

Average (UP-DN)
VDD
-2 p 2p phase error (deg)
Circuits2nd
Timing Issues
75
Charge Pump
VDD
UP
To VCO Control Input
DN
Circuits2nd
Timing Issues
76
PLL Simulation
Circuits2nd
Timing Issues
77
Clock Generation using DLLs

Delay-Locked Loop (Delay Line Based) fREF
U
Phase Det
Charge Pump
Filter
DL
fO
Phase-Locked Loop (VCO-Based) fREF N

U
PD
CP
Filter
VCO
fO
Circuits2nd
Timing Issues
78
Delay Locked Loop
Circuits2nd
Timing Issues
79
DLL-Based Clock Distribution

VCDL
Digital Circuit
CP/LF Phase Detector GLOBAL CLK
VCDL
Digital Circuit
CP/LF Phase Detector

Circuits2nd
Timing Issues
80

Chapter 10

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Digital Integrated Circuits

CLK In R1 Cin Combinational Logic Cout R2

EE141 Digital Integrated

EE141 Digital Integrated

Delays can be different for rising and falling data transitions

5 Temperature 1 Clock Generation

Sources of clock uncertainty

Variation of the pulse width

EE141 Digital Integrated

Clock Skew and Jitter

EE141 Digital Integrated

Insertion delay Max Clk skew

EE141 Digital Integrated

Positive and Negative Skew

R2 D Q tCLK2 delay Combinational Logic

EE141 Digital Integrated

Launching edge arrives before the receiving edge

EE141 Digital Integrated

Receiving edge arrives before the launching edge

EE141 Digital Integrated

Minimum cycle time: T - = tc-q + tsu + tlogic

Hold time constraint: t(c-q, cd) + t(logic, cd) > thold +

t j itter -tji tte r

Combinational Logic t log ic t log ic, cd

CLK tc-q , tc-q, ts u, thold tjitter

EE141 Digital Integrated

Longest Logic Path in Edge-Triggered Systems

Latest point of launching

Earliest arrival of next cycle

EE141 Digital Integrated

Clock Constraints in Edge-Triggered Systems

Tc-q + TLM + TSU < T TJI,1 TJI,2 -

Tc-q + TLM + TSU + + 2 TJI < T

Nominal clock edge

EE141 Digital Integrated

Clock Constraints in Edge-Triggered Systems

Tc-q + TLM TJI,1 < TH + TJI,2 +

Tc-q + TLM < TH + 2TJI+

EE141 Digital Integrated

How to counter Clock Skew?

Positive Skew Clock Distribution

Data and Clock Routing

EE141 Digital Integrated

Flip-Flop Based Timing

Logic delay TSU

Representation after M. Horowitz, VLSI Circuits 1996.

Flip-Flops and Dynamic Logic

Logic delay Precharge

Flip-flops are used only with static logic

When data arrives to transparent latch Latch is a soft barrier

When data arrives to closed latch Data has to be re-launched

EE141 Digital Integrated

Single-Phase Clock with Latches

L2 latch is transparent when = 1

EE141 Digital Integrated

EE141 Digital Integrated

Can tolerate skew!

Clock is distributed in a tree-like fashion

More realistic H-tree

The Grid System

No rc-matching Large power

EE141 Digital Integrated