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Analog to Digital Conversion

Def: taking an analog value (voltage or current) and mapping it to a digital code that represents the analog value ADCs are used in almost all digital systems Types:
Ramp ADC Successive Approximation ADC (SAC) Flash ADC Others: tracking ADC, Delta Sigma ADC

Digital Ramp ADC

Ramp ADC Circuit

Signals

Start
A signal to indicate the start of conversion (input)

EOC
A signal to indicate the End Of Conversion (output)

Vin
the analog input Vx the output of the DAC Where is the output of the ADC ?? the output of the counter is the output of the ADC

Operation
1. START reset counter DAC output Vx = 0V 2. Vin > Vx output of comparator is HIGH input to AND gate is HIGH EOC is LOW

Operation
3. Start is LOW AND gate is enabled the clock signal goes through to the counter 4. Counter counts !!! output of DAC (Vx) increases one step

Operation
5. This continues with each clock pulse, until : Vx > Vin + Vt output of comparator goes LOW input to AND is LOW counter stops counting EOC is HIGH 6. Conversion is complete (EOC ) 7. The counter holds the output until next START

Signals

Ramp ADC
Internal voltage Vx keeps rising in steps until it is larger than the input voltage Vin. The conversion time depends on the input voltage. Higher voltages have a longer conversion time. => worst case conversion time is when Vin is equal to full scale. The resulting value is always higher than the input voltage

Ramp ADC
Advantages:
Very simple design Cheap due to its simple design

Disadvantage
Variable conversion time. Slow operation.

SAC ADC

Example
Assume:
DAC step size 1V 4 bit converter Vin = 10.5V Output = ABCD

Example
Start, control resets register => ABCD = 0000 Cycle 1:
Control sets MSB ABCD = 1000 Vx = 8V < 10.5

Example
Cycle 2:
Control sets next MSB ABCD = 1100 Vx = 12V > 10.5V Control resets bit ABCD = 1000

Example
Cycle 3:
Control sets next MSB ABCD = 1010 Vx = 10V < 10.5

Example
Cycle 4:
Control sets next MSB ABCD = 1011 Vx = 11V > 10.5 Control resets bit ABCD = 1010

No more bits to process => EOC

Timing diagram

SAC ADC
A bit is value is determined each clock cycle starting from the MSB. The conversion time depends on the number of bits of the converter. The resulting value is always lower than the input voltage

SAC ADC
Advantages:
Fast conversion time compared to the Ramp ADC Constant conversion time, irrespective of the input voltage

Disadvantage
Complex control unit, compared to an AND gate in the Ramp ADC.

Flash ADC

Components
Op-Amps Resistors, XOR gates Encoder

Encod er
I7 0 0 0 0 0 0 0 1 I6 0 0 0 0 0 0 1 0 I5 0 0 0 0 0 1 0 0 I4 0 0 0 0 1 0 0 0 I3 0 0 0 1 0 0 0 0 I2 0 0 1 0 0 0 0 0 I1 0 1 0 0 0 0 0 0 I0 1 0 0 0 0 0 0 0 O2 0 0 0 0 1 1 1 1 O1 0 0 1 1 0 0 1 1 O0 0 1 0 1 0 1 0 1

Questions
Where is the input Vin Where is the output O2O1O0 How many bits 3 bits How many Op-Amps 8 What is the encoder type 8 to 3 line encoder

Operation
Example: Assume Vref = 4V, R = 1k V0 = Vref *(R / 8R ) = 0.5V V1 = Vref *(2R / 8R ) = 1V V2 = Vref *(3R / 8R ) = 1.5V V3 =2V, V4=2.5V, V5=3V, V6=3.5V

V4

3.5V 3.0V

2.5V 2.0V

1.5V 1.0V

0.5V

V4

Assume 0V < Vin < 0.5V

0 3.5V 0 3.0V 0 2.5V 0 2.0V 0 1.5V 0 1.0V 0 0.5V 0 0 0 0 0 0 0 1

0 0 0

Example (continued)
Assume 0V < Vin < 0.5V Output of ALL Op-Amps is LOW Output of XOR (0) is high I0 = HIGH Output of XOR (1) is LOW I1 = LOW Output of XOR (2) is LOW I2 = LOW Output of XOR (3) is LOW I3 = LOW Output of XOR (4) is LOW I4 = LOW Output of XOR (5) is LOW I5 = LOW Output of XOR (6) is LOW I6 = LOW Output of XOR (7) is LOW I7 = LOW 0 V < Vin < 0.5V Output = 000

V4

Assume 0.5V < Vin < 1.0V

0 3.5V 0 3.0V 0 2.5V 0 2.0V 0 1.5V 0 1.0V 1 0.5V 0 0 0 0 0 0 1 0

0 0 1

Example (continued)
Assume 0.5V < Vin < 1.0V Output of Op-Amps (0) is HIGH, others are LOW Output of XOR (0) is high I0 = LOW Output of XOR (1) is LOW I1 = HIGH Output of XOR (2) is LOW I2 = LOW Output of XOR (3) is LOW I3 = LOW Output of XOR (4) is LOW I4 = LOW Output of XOR (5) is LOW I5 = LOW Output of XOR (6) is LOW I6 = LOW Output of XOR (7) is LOW I7 = LOW 0 V < Vin < 0.5V Output = 001

V4

Assume 2.0V < Vin < 2.5V

0 3.5V 0 3.0V 0 2.5V 1 2.0V 1 1.5V 1 1.0V 1 0.5V 0 0 0 1 0 0 0 0

1 0 0

Example (continued)
Assume 2.0V < Vin < 2.5V Output of Op-Amps (0), (1), (2), and (3) are HIGH, others are LOW Output of XOR (0) is high I0 = LOW Output of XOR (1) is LOW I1 = LOW Output of XOR (2) is LOW I2 = LOW Output of XOR (3) is LOW I3 = LOW Output of XOR (4) is LOW I4 = HIGH Output of XOR (5) is LOW I5 = LOW Output of XOR (6) is LOW I6 = LOW Output of XOR (7) is LOW I7 = LOW 0 V < Vin < 0.5V Output = 100

Advantages / Disadvantages
Advantages:
Very fast. Conversion time is only the delay of the components No input clock

Disadvantages
Expensive . Why? Lot of components for a 10 bit converter we would need 1024 Op-Amps and 1024 to 10 line encoder. (not very easy to build)

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