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LOW POWER TECHNIQUES IN NANOMETER TECHNOLOGY

Name Reg No Course Module Module Leader

: Rama Krishna P. : CGB0911012 : M.Sc. [Engg.] in VLSI System Design : Integrated Circuit Analysis and Design : Prof. Cyril Prasanna Raj P.

M.S.Ramaiah School of Advanced Studies, Bangalore

Discussion
Why low power?

Types of power consumption


Dynamic power Static power Low power techniques

Clock gating
Multi vdd Multiple vth Power gating

Trade off
Future scope Conclusion References

M.S.Ramaiah School of Advanced Studies, Bangalore

Why low power...?

Desirability of portable devices.


Advent of hand held battery operated devices. Large power dissipation requires larger heat sinks hence increased area. Cost of providing power has resulted in significant interest in power reduction

of non portable devices.


Lowering transistor threshold voltage.

Pavg=Pswitching+Pshort-circuit + Pleakage =0 1CL Vdd2 fclk + Vdd Isc +Ileakage Vdd

M.S.Ramaiah School of Advanced Studies, Bangalore

Types of Power Consumption

Dynamic power During the switching of transistors Depends on the clock frequency and switching activity Consists of switching power and internal power. Static Power

Transistor leakage current that flows whenever power is applied to the device
Independent of the clock frequency or switching activity.

M.S.Ramaiah School of Advanced Studies, Bangalore

Dynamic power ( Pswitching =CL Vdd2 fclk )


capacitance
Vdd

1)

Output node capacitance of the logic gate: due to the drain diffusion region.

PMOS

2)
Vout Cdrain+ CloadCinterconnect+ Cinput

Total

interconnects

capacitance:

has

higher

effect

as

technology node shrinks.


B NMOS

3)

Input node capacitance of the driven gate: due to the gate oxide capacitance.

Input voltage Internal node voltage swing can be only Vi which can be smaller than
Fig 1:cmos inverter

the full voltage swing of Vdd leading to the partial voltage swing. Frequency F increases then power automatically increases.

M.S.Ramaiah School of Advanced Studies, Bangalore

(Pshort-circuit =Vdd Isc )


Both PMOS and NMOS are
More rise/fall timemore short circuit Lower threshold voltagemore short circuit
Vdd- |Vthp| 2.5V

conducting for a short duration of time short between supply power and ground

PMOS curve
Vthn<Vin<Vdd-|Vthp|

Vout

NMOS curve
0V Vthn Vin 2.5V

Fig 3:Trance analysis of cmos

Fig 2:shorte circuit

To get equal rise/fall balance transistor sizing

Vdd<Vthn+|Vthp|
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Static power (Pleakage =Ileakage Vdd)


1). Diode reverse biasI1 2). Sub threshold current I2
Vgs <~ Vth carrier diffusion causes sub threshold leakage.
Vgs <=0 accumulation mode. 0< Vgs << Vth depletion mode. Vgs ~ Vth weak inversion. Vgs > Vth Inversion.
Fig 4:Diode reverse bias

3). Gate induced drain leakage I3


Higher supply voltage. thinner oxide. increase in Vdb and Vdg.

4).Gate oxide tunneling I4


high electric field across a thin
gate oxide. Direct tunneling through the

silicon oxide layer if it is less than


34 nm thick.
Fig 5:leakage currents

M.S.Ramaiah School of Advanced Studies, Bangalore

Low power design techniques

Table 1:low power design techniques

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Clock gating
Clock tree consume more than 50 % of dynamic power Used for synchronous circuits Clock gating works by taking the enable conditions attached to registers, and uses them to gate the clocks. Save significant die area as well as power. Clock gating logic is generally in the form of "integrated clock gating" (ICG) cells.

Logic added into the design Coded into the RTL code as enable conditions--clock gating logic (fine grain clock gating). Inserted into the design manually by the RTL designers (typically as module level clock gating) Semi-automatically inserted into the RTL by (automated clock gating tools)

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Two types of clock gating styles

Latch-based clock gating

Latch-free clock

En D Q CK clk
Fig 6:Latch-based clock gating

Gated clock

CK

Fig 6:Latch-free clock gating

Uses a simple AND or OR gate Glitches are inevitable Less used

Level-sensitive latch Less glitch Easy adoption by EDA tools

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Multi Vdd (Voltage)


SVS DVFS AVS

Different but fixed voltage is applied to different blocks or subsystems of the SoC design.

Voltage as well as frequency is dynamically varied as per the different working modes of the design

When high speed of operation is required voltage is increased

Voltage areas with variable VDD. Voltage is controlled using a control loop.
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Multiple threshold

Use Hvt and Lvt cells Called as sleep transistor

Vdd standby High Prevents leakage Vt in standby mode CMOS Logic Low/Nom Vt High speed operation

Extensively used in Power gating

standby

High Prevents leakage Vt in standby mode

Fig 6:Sleep transistor

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Variable threshold
Vdd Vdd

General design: substrate is tied to power or ground

Vbias1

Vbias2

variable substrate bias voltage from a control circuitry to vary threshold voltage

Pros
Negligible area overhead Cons

Fig 7:substrate bias voltage in cmos

Considerable power reduction

Requires either twin well or triple well technology to achieve different substrate bias
voltage levels at different parts of the IC M.S.Ramaiah School of Advanced Studies, Bangalore
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Power gating
Circuit blocks that are not in use are temporarily turned off Affects design architecture more compared to the clock gating

It increases time delays as power gated modes have to be safely entered and exited
CMOS logic Power switching control signal

Power switching control signal

High Vt PMOS Header switch

CMOS logic

High Vt NMOS Footer switch

A power switch (header or footer) is added to supply rails to shut-down logic (MTCMOS switches)
Fig 8:power gating by sleep transistor

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Fine-grain power gating

Coarse-grain power gating

Fig 9:Fine grain power gating

Fig 10:Coarse grain power gating

Add a sleep transistor to every cell


Switching transistor as a part of the standard cell logic ~10X leakage reduction

Less sensitive to PVT variation Introduces less IR-drop variation Imposes a smaller area overhead

Ring based methodology Column based methodology


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Fig 11:switces for reducing the power

Low-power design requires new cells with multiple power pins Additional modeling information in .lib is required to automatically handle these cells

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Trade off for low power techniques

Table 2:trade-off analysis of power reducing techniques

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Future low power strategy?

Asynchronous Design - Solution to Dynamic Power?

Lets get rid of the clock


Micro pipeline: A Simple Asynchronous Design Methodology Is Hi-k sufficient for 22nm and 16nm? Whether this type of transistor structure (hi-k, metal gate) will continue to scale to the

next two generations22 nm and 16 nmis a question for the future.


Is there a simple, coherent power strategy that unifies the best of DVFS, power gating, asynchronous ? How do we represent and verify very complex power intent such as asynchronous ?

Carbon nano tubes.?


Spintronics..?

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conclusion

Power is becoming the restraining factor in further miniaturization and scaling. Various methodologies available but still a lot of scope for improvement. Need for developing of infrastructure. Combining of techniques into a single integrated system. discrete power saving

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References

[1] Keshava Murali, Low power techniques, SNUG 2007 and 2008 presentations on low power, Retrieved on 17 oct 2011. [2] Jan.M.Rabey and Massoud Pedram Kluwer academic publishers, low power design methodologies, Retrieved on 17 oct 2011.

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Thank you.

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