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LOGIC DESIGN & COMPUTER ARCHITECTURE

LOGIC DESIGN & COMPUTER ARCHITECTURE


Sub Topic 2.1: Computer Aided Design

Learning Outcome
At the end of this presentation, you will be able to:

2.1.1 Define the primary approaches to IC chip design a. Mask-programmable ICs b. Standard-cell devices c. Custom devices d. PLD and VHDL 2.1.2 Explain Schematic logic design using CPLD a. Overview of Schematic Design Methods b. Design Flow Summary c. Generated Reports after compilation schematic. d. Simulation concept
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IC DESIGN METHODOLOGY
DESIGN METHODOLOGY TREE DIAGRAM

IC DESIGN METHODOLOGY
STANDARD IC

Standard IC :
Integrated circuits designed and fabricated for general purpose use. Standard IC is available in the market at a very low cost. Examples of standard ICs:
74 - SERIES TTL, 4000 - SERIES CMOS, OP-AMP, TIMER, INSTRUMENTATION AMPLIFIER, MEMORY, MICROCONTROLLER, etc.

IC DESIGN METHODOLOGY
EXAMPLES OF STANDARD IC

4000 series CMOS

74-series TTL

IC DESIGN METHODOLOGY
EXAMPLES OF STANDARD IC

Op-Amp

Timer
Microcontroller

Memory

IC DESIGN METHODOLOGY
ASICs

Progress in the fabrication of IC's has enabled the designer to create fast and powerful circuits in smaller and smaller devices.
This also means that we can pack a lot more of functionality into the same area.

The biggest application of this ability is found in the design of ASICs.

IC DESIGN METHODOLOGY
ASICs

ASICs stands for : Application Specific Integrated Circuits

ASICs are IC's that are created for specific purposes - each device is created to do a particular job.
ASICs are produced for only one or a few customers or applications.

ASICs are devices made for a specific application such as a mobile phone.

IC DESIGN METHODOLOGY
EXAMPLES OF ASICs

IC DESIGN METHODOLOGY
EXAMPLES OF ASICs

GRAPHIC MEDIA ACCELERATOR

SMART CARD CHIPS

IC DESIGN METHODOLOGY

IC DESIGN METHODOLOGY
FULL CUSTOM DESIGN
All the circuits and mask layouts are

completely designed for the requirements of a particular IC. custom design ICdesigners spend many hours squeezing the most out of every last square micron of microprocessor chip space by hand.

A microprocessor is an example of a full-

IC DESIGN METHODOLOGY
SEMI CUSTOM DESIGN
To make ASICs economic at lower volumes,

the semi-custom concept was introduced where many applications share the same basic configuration of logic cells. requirements of a particular IC.

The mask layers are customized to fulfill the

Often used for speedy design with less effort

compared to full custom design.

IC DESIGN METHODOLOGY
SEMI CUSTOM DESIGN
There are 3 types of semi custom

design:-

1. Gate array (mask-programmable ICs)

2. Standard Cell
3. Programmable Logic Device (PLD)

IC DESIGN METHODOLOGY
SEMI CUSTOM IC

GATE ARRAY (mask programmable ICs)


1. Gate arrays are integrated circuits containing large numbers of digital gates or transistor cells, which can be interconnected in different ways to implement various logic functions. 2. Gate array consists of transistors, usually arranged in two pairs of PMOS and NMOS. 3. ASIC vendors offer a selection of gate array cells, with a different total numbers of transistors on each cell, for example, gate arrays with 50k-, 75k-, and 100k-gates.

IC DESIGN METHODOLOGY
SEMI CUSTOM IC

GATE ARRAY FLOOR PLAN

IC DESIGN METHODOLOGY
SEMI CUSTOM IC gate array

Gate array

IC DESIGN METHODOLOGY
SEMI CUSTOM IC gate array

IC DESIGN METHODOLOGY
SEMI CUSTOM IC

STANDARD CELL
1. Standard cell design involves the use of predesigned standard cell @ library cell that has been and stored in database. 2. Standard cell @ library cell consists of simple circuit such as inverter or logic gates (AND, OR, XOR, XNOR, flip-flop), and complex circuit such as register, adder, ROM and RAM.

IC DESIGN METHODOLOGY
SEMI CUSTOM IC

STANDARD CELL
3. Design is carried out by simply using the predesigned cells from the library and then connect the cells so that certain functions can be implemented. 4. To facilitate placement and routing, the standard cells are designed to have equal height but variable widths, so that the final IC layout will have a regular pattern with rows of cells and interconnect routing running between the rows.

IC DESIGN METHODOLOGY
SEMI CUSTOM IC

STANDARD CELL FLOOR PLAN


I/O Pads

Standard Cell

LOGIC BLOCK

Routing Standard Cell Routing

Standard Cell Routing Standard Cell Routing

BLOCK

IC DESIGN METHODOLOGY
SEMI CUSTOM IC

PROGRAMMABLE LOGIC DEVICE (PLD)

PLD is an array of logic gates that can be programmed by the user which contains functions of a small number of logic circuits in a single chip.

PROGRAMMABLE LOGIC DEVICE (PLD)

PROGRAMMABLE LOGIC DEVICE (PLD)


PLD MANUFACTURERS

PROGRAMMABLE LOGIC DEVICE (PLD)


GENERAL CHARACTERISTICS OF PLD IC

1. PLD does not require a common mask layout in design.


2. The design time is shorter. 3. It consists of a large block of internal connections that can be a programmed. 4. Programming can be done at different stages: i) at the earliest, it is programmed by the semiconductor vendor (standard cell, gate array). ii) by the designer prior to assembly or field deployment. iii) by the user in circuit.

IC DESIGN METHODOLOGY
PROGRAMMABLE LOGIC DEVICE

Inputs

(logic variables)

Logic gates and programmable switches

Outputs

(logic functions)

Programmable logic device as a black box.

IC DESIGN METHODOLOGY
DESIGN METHODOLOGY DIFFERENCES
Design method Full custom Standard cell Gate array PLD Design cost The most expensive Average Chip size The smallest Small Operation speed Highest speed High-speed Power dissipatio n 5x Smaller 3x smaller 2x Smaller 1x Smaller No. of mask Numero us Many 1@2 piece None Design time Timeconsumi ng Average

Cheaper The Cheapest

Large

Slow

Fast The fastest

Largest

Slowest

PLD programming
Schematic Entry Text-Based Entry

VHDL
VHDL is the VHSIC Hardware Description Language. VHSIC is an abbreviation for Very High Speed Integrated Circuit a language to describe the structure and behaviour of digital electronic hardware designs, such as ASICs and FPGAs as well as conventional digital circuits.

D Flip-flop Model
Bit values are enclosed in single quotes

Design Entry Techniques


Schematic Designer draws the equivalent design using gates and other logic circuits (can include ICs such as JK FF or 74xxx parts) Waveform Design draws the desired input and output waveforms for the device Text Design Files Design specifies the design using a design language such as Altera Hardware Design Language (AHDL)

Example of Schematic Design

Example of Waveform Design

At the end of this presentation, you will be able to:

Learning Outcome

2.2

Realize element logic in computer logic

2.2.1 Define clocking in terms of a digital computer. 2.2.2 Explain function clocks (wave form) in digital computer. 2.2.3 Explain gated flip-flop: a. SR flip-flop b. D flip-flop c. Master-slave flip-flop d. JK flip-flop 2.2.4 Use schematic CPLD to simulate digital output for above flip-flop.

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Element Logic in Computer Logic

Introduction
Latch is a type of temporary storage device that has two stable states (bistable). Latches and Flip-flops are used in sequential circuits. Differences between sequential circuits and combinational circuits.

37

Introduction
Latch is normally placed in a category separate from that flip flops. The main difference between latch and FF is in the method used for changing their state. Term synchronous means that the output changes state only at a specified point on the triggering input called the clock (CLK).

38

Element Logic in Computer Logic


Logic circuits are classified into two groups:
Combinational logic circuits
Basic building blocks include:
Logic gates make decisions

Sequential logic circuits

Flip Flops have memory

Basic building blocks include FLIP-FLOPS:

FLIP-FLOPS
Flip-flops are memory elements that change state on clock signals. Memory elements capable of storing one bit
command Memory element

Q
stored value

clock

Flip Flops are wired to form counters, shift registers, and various memory devices.

Edge Triggered Flip - Flops

1. 2. 3. 4.

Change state either at the positive edge (rising edge) or at the negative edge (falling edge) of the clock pulse. Sensitive to its inputs only at this transition of the clock. Three types of edge triggered FF SR D T JK
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Edge Triggered Flip Flops Logic Symbols

42

CLOCK SIGNAL
The clock signal is generally a rectangular pulse train or
square wave, as shown below :
Positive pulses

Positive edges

Negative edges

Circuits in computers are clocked At each clock rising (or falling) edge, some specified actions are done, usually within the next rising (or falling) edge
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TRIGGERING OF FLIP-FLOPS
Level-triggering is the transfer of data from input to output of a flip-flop anytime the clock pulse is proper voltage level.

SR FF Logic Symbols

45

SR FF Truth Table
Inputs S R CLK Outputs Q Q Comments

0
0 1 1

0
1 0 1

Qo
0 1 ?

Qo
1 0 ?

No change
RESET SET Invalid condition

= clock transition LOW to HIGH X = Irrelevant (dont care) Qo = output level prior to clock transition
46

SR FF Example

47

D FF
D flip flop is useful when a single data bit (1 or 0) is to be stored. The addition of an inverter to an S R flip flop creates a basic D flip flop.

48

D FF Truth Table
Inputs S 1 0 CLK Outputs Q 1 0 Q 0 1 SET (stores a 1) RESET (stores a 0) Comments

= clock transition LOW to HIGH

49

D FF Example

50

JK FF
Versatile and is widely used type flip flop. The difference between J K and S R is that J K flip flop has no invalid state as does S R flip flop.

51

JK FF
Transitions illustrating the toggle operation when J = 1 and K = 1.

52

JK FF Truth Table
Inputs J 0 K 0 CLK Q Qo Outputs Q Qo No change Comments

0
1 1

1
0 1

0
1 Qo

1
0 Qo

RESET
SET Toggle

= clock transition LOW to HIGH Qo = output level prior to clock transition


53

JK FF Example

54

Asynchronous Preset and Clear Inputs


Independent of the clock. Active level on the preset input will set the flip flop. Active level on the clear input will reset it.

Note : for synchronous operation, both preset and clear inputs must both kept HIGH.
55

Asynchronous Preset and Clear Inputs Logic Diagram

56

Asynchronous Preset and Clear Inputs Example

57

Master Slave Flip Flops


Data are entered into the flip flop at the leading edge of the clock pulses, but the output does not reflect the input state until the trailing edge. Pulse triggered master slave flip flop does not allow data to change while the clock pulse is active.

58

Pulse Triggered Master Slave Flip Flops

Master Slave JK Flip-flop


59

Pulse Triggered Master Slave Flip Flops


Composed of two sections, the master section and the slave section. A master section is basically a gated latch. The slave section is the same except that it is clocked on the inverted clock pulse and is controlled by the outputs of the master section rather than by the external J K inputs.

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Pulse Triggered Master Slave Flip Flops Truth Table


Inputs J 0 K 0 CLK Q Qo Outputs Q Qo No change

Comments

0
1 0

1
0 1

0
1 Qo

1
0 Qo

RESET
SET Toggle

= clock transition LOW to HIGH Qo = output level prior to clock transition


61

Pulse Triggered Master Slave Flip Flops Logic Symbol

62

At the end of this presentation, you will be able to:

Learning Outcome

2.3 Realize flip-flop application

2.3.1 Explain Shift Register operation. 2.3.2 Design Shift Register using flip-flop JK. 2.3.3 Determine kinds of binary counter 2.3.4 Explain binary counter operation using: a. Flip-flop SR b. Flip-flop JK 2.3.5 Design a sequence counter (3 bit) 2.3.6 Design sequential magnitude comparator 2.3.7 Design BCD to seven segment decoder

63

Flip-Flop Applications
Applications of Flip-Flop: Counters
Asynchronous Counter Synchronous Counter

Register

Shift Register
Shift registers are constructed using several flipflop, connected in such a way to STORE and TRANSFER digital data. Basically, D flip-flop is used. The input data (either 0 or 1) is applied to the D terminal and the data will be stored at Q during positive/negative-edge transition of the clock positive edge transition of CLK pulse.
1

65

Shift Register
One D FF is used to store 1-bit of data. Thus, the number of flip-flops used is the same with the number of bit stored. Shift register mean that the data in each FF can be transferred/move to other FF upon edge triggering of the clock signal. Four types of data movement in shift register are:-

Parallel in / parallel out (PIPO)


Serial in / serial out (SISO) Parallel in / serial out (PISO)
66

Shift Register
Serial Data VS Parallel Data movement
Serial
Movement of N-bit data require N number of CLK pulses. Thus, the operation is slow. Only one FF is required to be connected at the output terminal, thus only one wire is required.

Parallel
Require only one CLK pulse to transfer all N-bit of data. Thus, operation is faster than serial. Required N number of connection to the output terminal, which is proportional to the number of bit. Thus, too many connection is required.
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Parallel in / parallel out (PIPO)


Flip-flop configuration for PIPO register.
D3 D2 D1 D0

D Q3
CP

D Q2
CP

D Q1
CP

D Q0
CP

CLK Q3 Q2 Q1
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Q0

Parallel in / parallel out (PIPO)


PIPO data movement.
CLK D3 D2 D1 D0 Q3 Q2 Q1 Q0 0 0 0 0 0 1 0 1 1 0
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1 0

0 1

1 0

1 1

1 0

1
0 1

1
0 0

1
0

0
1

1
0

Serial in / serial out (SISO)


Flip-flop connection for SISO.
1st CLK 2nd CLK 3rd CLK 4th CLK

DIN

D Q0
CP

D Q1
CP

D Q2
CP

D Q3
CP

CLK

FF0

FF1

FF2

FF3

70

Serial in / serial out (SISO)


SISO data movement. Binary data 10111 is transferred! 4th 1st 2nd 3rd 5th
CLK DATA-IN 1 0 1 1 1

Q0 Q1

Q2

Q3

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Serial in / parallel out (SIPO)


Flip-flop connection for SIPO.
1st CLK 2nd CLK 3rd CLK 4th CLK

DIN

D Q0
CP

D Q1
CP

D Q2
CP

D Q3
CP

CLK

FF0

FF1

FF2

FF3

Q0

Q1

Q2
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Q3

Serial in / parallel out (SIPO)


SIPO data movement. Binary data 10111 is transferred! 4th 1st 2nd 3rd 5th
CLK DATA-IN 1 0 1 1 1 1 Q1 1

Q0

0
Q2 1

Q3

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Parallel in / serial out (PISO)


Flip-flop connection for PISO.
SHIFT/LOADD0
D1 D2 D3

D Q0
CLK CP

D Q1
CP

D Q2
CP

D Q3
CP

Serial data out

FF0

FF1

FF2

FF3
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Parallel in / serial out (PISO)


PISO data movement.
CLK D0 D1 D2 D3 0 0 0 1 1 0 1 1 1 0

1
1

1
0

1
0

0
1

1
1

SHIFT/ LOAD
Q3 0 1 1 0 0 1
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Shift Register Counters


A shift register counter is a shift register whose output being fed back (connected back) to the serial input. This shift register would count the state in a unique sequence! Two types of shift register counter:-

The ring counter


The Johnson counter

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Ring Counter
Q3 Q2 Q1 Q0

77

Ring Counter (continue)


0 1 0 0 0 0 1 0

0 0

1 0

0 1

0 0

78

Ring Counter (continue)

79

Ring Counter (continue)


Ring counters are used to construct One-Hot counters It can be constructed for any desired MOD number A MOD-N ring counter uses N flip-flops connected in the arrangement as shown in fig. a) In general ring-counter will require more flip-flops than a binary counter for the same MOD number

80

Ring Counter (continue)

81

Johnson Counter
Or Twisted-ring counter

Johnson counter constructed exactly like a normal ring counter except that the inverted output of the last flip-flop is fed back to first flip-flop

82

Johnson Counter
(Continue)

0
A 0

C 0

83

Johnson Counter
(Continue)

84

Chips for shift registers


74164 is a 8-bit SIPO shift register
A B CLR CLK

74164

Q0 Q1 Q2 Q3 Q4 Q 5 Q6 Q7

85

Chips for shift registers


74165 is a 8-bit PISO register
D0 D1 D2 D3 D4 D5 D6 D7

SH/LD SER CLK INH CLK 74165

Q7 Q7

86

Chips for shift registers


74195 can be used as a 4-bit PIPO register
D0 D1 D2 D3

J K SH/LD CLR CLK 74195

Q0 Q1 Q2 Q3
87

Chips for shift registers


74194 is a 4-bit universal bidirectional shift register D D D D
0 1 2 3

CLR S0 S1 SR SER SL SER CLK 74194

Q0 Q1 Q2 Q3

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Counters
A counter is a register that goes through a predetermined sequence of states upon the application of clock pulses. Asynchronous counters Synchronous counters

Async. counters (or ripple counters)


the clock signal (CLK) is only used to clock the first FF. Each FF (except the first FF) is clocked by the preceding FF.

Sync. counters,
the clock signal (CLK) is applied to all FF, which means that all FF shares the same clock signal, thus the output will change at the same time.
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Flip-Flop Applications
Applications of Flip-Flop: Counters
Asynchronous Counter Synchronous Counter

90

Asynchronous counters
Modulus (MOD) the number of states it counts in a complete cycle before it goes back to the initial state. Thus, the number of flip-flops used depends on the MOD of the counter (ie; MOD-4 use 2 FF (2bit), MOD-8 use 3 FF (3-bit), etc..) Example: MOD-4 ripple/asynchronous upcounter.

91

Asynchronous Counters (continue)


The asynchronous counter that counts 4 number starts from 00011011 and back to 00 is called MOD-4 ripple (asynchronous) up-counter. Next state table and state diagram
Present State Q1Q0 00 01 10 11 Next State Q1Q0 01 10 11 00
00 11 10
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01

Asynchronous Counters (continue)


MOD-4 Asynchronous up-counter
Q0 (LSB) 1 CLK Q1 (MSB)

J
CLK

J
CLK

K
CLK
Q1 Q0 Binary 0 0 0 0 1 1 0 1 1 2

0 0 3

0 1 0

1 0 1

1 1

0 0 2 3 0
93

Asynchronous Counters (continue)


MOD-8 Asynchronous up-counter
C B A

J
CLK

J
CLK

J
CLK

K
CLK
A 0

B
C

0
0

94

Asynchronous Counters (continue)


Next state table and state diagram Present State ABC Next State ABC
0 7 6 5 4 3 1 2

000 001 010 011 100 101 110 111

001 010 011 100 101 110 111 000

95

Asynchronous Counters (continue)


Exercise:
Design a MOD-16 ripple up-counter Design a MOD-4 ripple downcounter

Design a MOD-8 ripple down counter


Design a MOD-16 ripple down counter

96

Asynchronous Counters (continue)


2-bit Asynchronous down counter
B (LSB) 1 CLK A (MSB)

J
CLK

J
CLK

K
CLK
B A 0 0 1 1 0 1 1 0

0 0

1 1

0 1

1 0

0 0

Binary

1 97 0

Asynchronous Counters (continue)


So far, we have design the counters with MOD number equal to 2N, where N is the number of bit (N = 1,2,3,4.) (also correspond to number of FF) Thus, the counters are limited on for counting MOD-2, MOD4, MOD-8, MOD-16 etc..

The question is how to design a MOD-5, MOD-6, MOD-7, MOD-9 which is not a MOD-2N (MOD 2N) ?
MOD-6 counters will count from 010 (0002) to 510(1012) and after that will recount back to 010 (0002) continuously.
98

Asynchronous Counters
MOD-6 ripple up-counter (MOD 2N) Present St. ABC Next St.
5 0 1 2 3

ABC

000 001 010 011 100 101

001 010 011 100 101 000(110)

Reset the state to 0002 when 1102 is detected


99

Asynchronous Counters (continue)


Circuit diagram for MOD-6 ripple up-counter (MOD 2N) C B A
1 CLK

Q
CLK

Q
CLK

Q
CLK

K Q
CLR

K Q
CLR

K Q
CLR

Detect the output at ABC=110 to activate CLR. NAND gate is used to detect outputs that generates 1!
100

74293 IC for Asynchronous counter with Reset (MR1 and MR2) MR1 CP1
74293 MR2

Chip for Asynchronous counters


Q3 Q2 Q1 Q0
CP0

Q0
1 CP0

Q1

Q2 J Q
1

Q3

CLK K Q CLR

CLK K Q CLR

CLK K Q CLR

CLK K Q CLR

CP1 MR1 MR2


101

Chip for Asynchronous counters


(continue)
Using 74293 IC to design MOD 16 asynchronous up-counter!

Exercise:
use 74293 IC to design MOD-10 ripple up-counter
MR1 74293 MR2 CP0 CP1

Q3 Q2 Q1 Q0 1 0 0 1
102

Chip for Asynchronous counters


Exercise:

(continue)

Determine the MOD for each configuration shown below?


MR1 74293 MR2 CP0 CP1

Q3 Q2 Q1 Q0

MR1

CP1

74293
MR2 CP0

Q3 Q2 Q1 Q0 1 0 1

103

Chip for Asynchronous counters


(continue)
Determine the MOD for each configuration shown below? MR1 CP1
74293 MR2 CP0

Q3 Q2 Q1 Q0

104

Asynchronous counters
Disadvantages of Asynchronous Counters: Propagation delay is severe for larger MOD of counters, especially at the MSB. Existence of glitch is inevitable for MOD 2N counters. Difficult to design random counters (i.e:- to design circuit that counts numbers in these sequence 56723156723156.)

Solution, use SYNCHRONOUS COUNTERS.


105

Synchronous counters
For synchronous counters, all the flip-flops are using the same CLOCK signal. Thus, the output would change synchronously. Procedure to design synchronous counter are as follows:-

STEP 1: Obtain the State Diagram.


STEP 2: Obtain the Excitation Table using state transition table for any particular FF (JK or D). Determine number of FF used. STEP 3: Obtain and simplify the function of each FF input using K-Map. STEP 4: Draw the circuit.
106

Synchronous counters
Design a MOD-4 synchronous up-counter, using JK FF.

STEP 1: Obtain the State transition Diagram


0 3 2 1 11 10 00 01

Binary

107

Synchronous counters
STEP 2: Obtain the Excitation table. Two JK FF are used. OUTPUT TRANSITION FF INPUT
QN QN+1 J K

0 0 1 1 Present State A 0 0 1 1 B 0 1 0 1

0 1 0 1

0 1 X X

X X 1 0

Excitation table

Next State A 0 1 1 0 B 1 0 1 0 JA KA 0 X 1 X X 0 X 1 JB KB 1 X X 1 1 X X 1

108

Synchronous counters
STEP 3: Obtain the simplified function using K-Map

B
A 0 0 0 1 X 1 1 X A

JA = B

0 0 X 1 0

1 X 1

KA = B

0 0 1 1 1

1 X X

JB = 1

0 0 X 1 X

1 1 1

KB = 1
109

Synchronous counters
STEP 4: Draw the circuit diagram
B (LSB) 1 A (MSB)

JB
CLK

JA
CLK

KB

KA

110

Synchronous counters
Exercise: Design MOD-4 sync up-counter using D flip-flop. Design MOD-8 sync up-counter using D flip-flop. Design MOD-8 sync up-counter. Use T FF for MSB, D FF for second bit and JK FF for LSB. Design MOD-16 sync up-counter using T flipflop.

111

Synchronous counters
Design a MOD-4 synchronous down-counter, using JK FF?

STEP 1: Obtain the State transition Diagram


0 1 2 3 01 10 00 11

Binary

112

Synchronous counters
Obtain the Excitation table. Two JK FF are used.
OUTPUT TRANSITION QN QN+1 FF INPUT J K

0 0 1 1

0 1 0 1

0 1 X X

X X 1 0

Present St. A B

Next St. A B JA KA JB KB

0 0 0 1 1 0

113

Synchronous counters
Obtain the simplified function using K-Map

B
A 0 1 0 1 A

B
0 0 1 1

JA =

KA =

A
0 1

0
0 1

JB =

KB =
114

Synchronous counters
Draw the circuit diagram

JA
CLK

KA

JB
CLK

KB

Q
115

Synchronous counters
Exercise: Design MOD-4 sync down-counter using D flipflop. Design MOD-8 sync down-counter using D flipflop. Design MOD-8 sync down-counter. Use T FF for MSB, D FF for second bit and JK FF for LSB. Design MOD-16 sync down-counter using T flipflop.
116

Chip for synchronous counter 74163


D0 D1 D2 D 3 CLR LOAD ENT ENP CLK

74163

RCO

Q0 Q 1 Q2 Q3

117