Beruflich Dokumente
Kultur Dokumente
Introduction
Slide 1
Organization
Prerequisites: logic design, basic computer organization See sample questions Architecture design versus chip design Example: innovative processor Overview of material Bottom-up approach, CAD tools See syllabus for individual topics Course organization Website, TA, office hours, HW, projects Acknowledgements J. Abraham (UT), D. Harris (HMC), R. Tupuri (AMD)
Introduction
Slide 2
Course relevance
2007 world wide sales of chips: ~250B$ Primarily digital High-margin business Basis for systems Most CE graduates work in VLSI design: Intel, Qualcomm System design: HP, Cisco Software: Microsoft, Google
Introduction
Slide 3
Course Goals
Learn to design and analyze state-of-the-art digital VLSI chips using CMOS technology Employ hierarchical design methods Understand design issues at the layout, transistor, logic and register-transfer levels Use integrated circuit cells as building blocks Use commercial design software in the lab Understand the complete design flow Wont cover architecture, solid-state physics, analog design Superficial treatment of transistor functioning
Introduction
Slide 5
Course Information
Instructor: Adnan Aziz (512) 465-9774, Adnan@ece.utexas.edu http://www.ece.utexas.edu/~adnan Course Web Page Link from my page Book: Weste and Harris, CMOS VLSI Design: A Circuits and Systems Perspective, AW, 3rd edition
Introduction
Slide 6
Introduction
Slide 8
Introduction
Slide 9
Academic Honesty
Cheating will not be tolerated OK to discuss homework, laboratory exercises with classmates, TAs and the instructors However: write the homework and lab exercises by yourself We check for cheating, and report incidents
Introduction
Slide 10
General Principles
Technology changes fast => important to understand general principles optimization, tradeoffs work as part of a group leverage existing work: programs ,building blocks Concepts remain the same: Example: relays -> tubes -> bipolar transistors -> MOS transistors
Introduction
Slide 11
Types of IC Designs
IC Designs can be Analog or Digital Digital designs can be one of three groups Full Custom Every transistor designed and laid out by hand ASIC (Application-Specific Integrated Circuits) Designs synthesized automatically from a high-level language description Semi-Custom Mixture of custom and synthesized modules
Introduction
Slide 12
Introduction
Slide 13
Steps in Design
Designer Tasks Define Overall Chip A rchitect C/RTL Model Initial Floorplan Behavioral Simulation Logic Designer Logic Simulation Synthesis Datapath Schematics Cell Libraries Circuit Designer Circuit Schematics Circuit Simulation Megacell Blocks Layout and Floorplan Physical Designer Place and Route Parasitics Extraction DRC/LVS/ERC Place/Route Tools Physical Design and Evaluation Tools Schematic Editor Circuit Simulator Router RTL Simulator Synthesis Tools Timing A nalyzer Power Estimator Tools Text Editor C Compiler
Introduction
Slide 14
System on a Chip
Source: ARM
Introduction
Slide 15
Laboratory Exercises
Layout and evaluation of standard cells Familiarity with layout, circuit simulation, timing Design and evaluation of an ALU, performance optimization Learn schematic design, timing optimization Design, synthesis and analysis of a simple controller as part of an SoC Learn RT-level design, system simulation, logic synthesis and place-and-route If you already have industrial experience with some of these tools, you can substitute lab for final project Need my approval; will expect more from project
Introduction CMOS VLSI Design Slide 16
Laboratory Exercise 1
Schematics (Cadence)
Library Symbol
DRC
Layout (Cadence)
Introduction
Slide 18
Laboratory Exercise 2
Library Schematics (Cadence) Functional Verification VerilogXL Library LVS Layout (Cadence) Static Timing Analysis (Synopsys) Schematic Layout
DRC
Extraction (Cadence)
Introduction
Slide 19
Laboratory Exercise 3
Verilog RTL model Synthesis (Synopsis) APR (Cadence) Extraction (Cadence) Static Timing Analysis (Synopsys)
Introduction
Slide 20
Introduction
Slide 21
Triode: based on Edisons bulbs! See Ch. 1, Tom Lee, Design of CMOS RF ICs
Introduction CMOS VLSI Design Slide 22
Introduction
Slide 23
Lilienfeld patents
1930: Method and apparatus for controlling electric currents, U.S. Patent 1,745,175 1933: Device for controlling electric current, U. S. Patent 1,900,018
Introduction
Slide 24
Bell Labs
1940: Ohl develops the PN Junction 1945: Shockley's laboratory established 1947: Bardeen and Brattain create point contact transistor (U.S. Patent 2,524,035)
Diagram from patent application
Introduction
Slide 25
Bell Labs
1951: Shockley develops a junction transistor manufacturable in quantity (U.S. Patent 2,623,105)
Diagram from patent application
Introduction
Slide 26
Introduction
Slide 27
Introduction
Slide 28
Integrated Circuits
1961: TI and Fairchild introduce the first logic ICs ($50 in quantity) 1962: RCA develops the first MOS transistor
Fairchild bipolar RTL Flip-Flop RCA 16-transistor MOSFET IC
Introduction
Slide 29
Computer-Aided Design
1967: Fairchild develops the Micromosaic IC using CAD Final Al layer of interconnect could be customized for different applications
RAMs
1970: Fairchild introduces 256-bit Static RAMs 1970: Intel starts selling1K-bit Dynamic RAMs
Fairchild 4100 256-bit SRAM Intel 1103 1K-bit DRAM
Introduction
Slide 31
The Microprocessor
1971: Intel introduces the 4004 General purpose programmable computer instead of custom chip for Japanese calculator company
Introduction
Slide 32