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Lecture 2: IBM PC/AT and ISA Bus

80386-based PC/AT-Compatible System


DRAM

386DX

82345 Data Buffer

386DX+82340 chip set

SYSTEM BUS

LOCAL BUS

387 DX

82346 System Controller

82341 Peripheral Combo

82385DX Cache Controller Cache

82344 ISA Controller

BIOS Industry Standard Architecture(ISA) Bus Maeng Lect 2-2

Pentium Processor/82430 PCIset ISA


Host Bus
CNTL
ADDR DATA Latch SRAM 82434 PCMC DRAM 82433 LBX Pentium Processor

PCI BUS

CNTL ADDR/DATA 82378 SIO Grahics PCI devices

ISA BUS

Maeng Lect 2-3

ISA Bus Interface Signals


Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 Name I/O CH CK* D7 D6 D5 D4 D3 D2 D1 D0 I/O CH RDY AEN A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 Ty pe I I/O I/O I/O I/O I/O I/O I/O I/O I O O O O O O O O O O O O O O O O O O O O Pin B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 Name GND RESET DRV +5V IRQ2 -5V DRQ2 -12V RESERVED +12V GND SMEMW* SMEMR* IOW* IOR* DACK3* DRQ3 DACK1* DRQ1 REFRESH* CLOCK IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 DACK2* T/C BALE +5V OSC Ty pe O I I

O O O O O I O I O O I I I I I O O O O

Maeng Lect 2-4

ISA Bus Interface Signals


Pin C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 Name SBHE* LA23 LA22 LA21 LA20 LA19 LA18 LA17 MEMR* MEMW* SD08 SD09 SD10 SD11 SD12 SD13 SD14 SD15 Ty pe O O O O O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O Pin D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 Name MEM CS 16 * IO CS 16* IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 DACK0* DRQ0 DACK5* DRQ5 DACK6* DRQ6 DACK7* DRQ7 +5V MASTER* GND Ty pe I I I I I I I O I O I O I O I I

Maeng Lect 2-5

Block Diagram of the System Board


data External Master ISA Bus CPU

addr data addr DMA MEM

Memory

I/O

All signal lines are TTL compatible. Fan-out are two low power Shottkey(LS) TTLs. SA0 through SA19: System Address Bus:(I/O)
to address memory and I/O devices; 16MB of memory with LA17 through LA23 input when CPUHLDA is high and MASTER* is low; output at all other times SA bus driven by CPU when CPUHLDA is low; SA bus driven by 8237 DMA controller when CPUHLDA is high latched with an internally generated ALE signal

Maeng Lect 2-6

LA17 through LA23 (Latchable Address Bus); I/O


the same as SA19-SA0 Input when CPUHLDA is high and MASTER* is low it is driven from the 288 bus controller when CPUHLDA is low and MASTER* is high it is driven by the 8237 DMA controller when CPUHLDA is high and MASTER* is high requires an external 10K pull-up registor Input/output determination: the same as MEMR* requires an external 10K pull-up registor Input/Output determination: the same as MEMR* active on memory read cycles to addresses below 1 MB. requires an external 10KW pull-up registor Input/Output determination: the same as MEMR* active on memory read cycles to addresses below 1 MB. requires an external 10K pull-up registor controlled the same way as the SA bus

MEMR* (Memory Read, active low); I/O

MEMW*(Memory Write, active low): I/O


SMEMR*(Memory Read): I/O


SMEMW*(Memory Write):I/O

SBHE*(System Byte High Enable) : I/O

Maeng Lect 2-7

REFRESH*(Refresh signal); I/O SYSCLK(System CLock) : O


this output is half the frequency of the BUSCLK input BALE, IOR*, IOW*, MEMR*, MEMW* are synchronized to SYSCLK the buffered inout of the external 14.318 MHz oscillator.

OSC(Oscillator): I-TTL

RSTDRV(Reset Drive): O BALE(Buffered Address Latch Enable): O


A pulse which is generated at the beginning of any bus cycle initiated from the CPU. goes high anytime the inputs CPUHLDA and MASTER* are both high DMA controller has control when this signal is active indicates that one of the DMA channels terminal count has been reached

AEN (Address Enable): O

T/C (Terminal Count): O

DACK7*- DACK5*, DACK3*- DACK0* (DMA Acknowledge): O DRQ7-DRQ5, DRQ3-DRQ0 (DMA Request) : I
DRQ0-DRQ3 : from 8-bit I/O adapters to/from system memory DRQ5-DRQ7: from 16-bit I/O to/from system memory DRQ4 is not available externally as it is used to cascade the two DMA controllers together.

Maeng Lect 2-8

IRQ15-IRQ9, IRQ7-IRQ3, IRQ1 (Interrupt Request) : I


inputs for the 8259 megacells IRQ0, IRQ2, IRQ8 ; not available as external inputs used by an external device to disable the internal DMA controllers and get access to the system bus when asserted it indicates that an external bus master has control of the bus. used to determine when a 16-bit to 8-bit conversion is needed for CPU addresses A 16 to 8 conversion is done anytime the System Controller requests a 16-bit memory cycle and MASTER* is sampled high. functions the same way as MEMCS16* signals used to indicate that an error has taken place on the I/O bus pulled low in order to extend the read or write cycles of any bus access when required the default number of wait states for cycles initiated by the CPU;
four wait states for 8-bit peripherals one wait state for 16-bit peripherals three wait states for ROM cycles

MASTER* (Master) : I

MEMCS16* (Memory Chip Select 16-bit) : I


IOCS16* (I/O Chip Select 16-bit) : I


IOCHK* (I/O Channel Check): I IOCHRDY (I/O Channel Ready) : I

One wait state is inserted as the default for all DMA cycles

Maeng Lect 2-9

WS0* (Wait State 0) : I


pulled low by a peripheral on the bus to terminate a CPU controlled bus cycle earlier than the default values

Maeng Lect 2-10