MEM DMA-CONTROLLER

DMA CONTROLLER

1)Dynamic memory access (DMA) is the fastest of all memory access techniques. 2)Even though processor can do memory transfers, a dedicated module is required to do burst transfers within less clock cycles. 3)Dma and processor can run concurrently. 4)while dma is in working the processor can able to do some other operation so that processor time will not be wasted.

avl_read avl_write avl_read A V A av_address L O av_wdata CONTROL N

REGISTE R

avl_address avl_readdatavalid
READ MASTER

avl_readdata avl_write_req

B av_rdata U S frame_type
frame_valid

F I F O

avl_write avl_write_data avl_address

WRITE MASTER

A V A L O N B U S

avl_wait_req

Data transfering using DMA

1)Initially the processor writes the starting address to be read, starting address to be write and no of bytes to be transfer in to the control register. 2)when a valid address is present in control register the read master automatically starts the data reading and copies the data in to the fifo. 3)The write master gets this data from the fifo and writes to the destination memory location. 4)This process continues until specified no of bytes are transferred.

CONTROL REGISTER

STATUS REG READ ADD REG WRITE ADD REG

WRITE ADDR REG1

BYTE COUNT REG

CONTROL REG
ALT CONTROL REG

RESET REG

Control register
The status register is 8 bit wide and remaining registers are 32 bit wide. Status register contains status of of the dma controller operations. Only 1st three bits used in the status registers and the remaining bits are unused. If the 0th bit is high it indicates read done is completed. If 1st bit is high then it indicates whole transferring is completed. If 2nd bit is high then it indicates that write done is completed. An extra registers called write address reg1 is present to transfer the data in to the two memory locations at a time.

Control register
avl_write av_read av_address start

addr_inc_identity
r_bits_identity dma_read_addr

dma_byte_cnt
av_wdata av_radta frame_valid read_done frame_type dma_active write_done Control register dma_write_addr w_bits_identity w_addr_inc_identity

WRITING IN TO THE CONTROL REGISTERS

1)Initially the processor writes the staring addr to be read, starting addr to be write and no of bytes to be transfer in to their respective registers(read addr reg,write addr reg,byte count reg) that are present in the control registers. 2)when these data are ready the start bit of control register is made high indicating to read master to start the reading process.

READ MASTER block

start_dma avl_read addr_inr_identity avl_address

bits_identity
reg_read_addr read_byte_cnt read_done dma_active fifo_data fifo_write_req fifo_full Read Master avl_read_data_valid avl_readdata avl_wait_req

Working of read master

1)when the start bit of control reg is high the read master block automatically reads the contents of the control registers and starts reading the data. 2)when a valid address is present the read data valid bit is made high and the data is written in to the FIFO Until the fifo is not full. 3)The address will incremented by multiples of 4 and read count value will be decremented by 1.

State diagram for read operation

rst=0 idl e Dma active=0 start dma=0 Dma active=1 Start dma=1

Initial addr

Read data Read cnt=0 done

Read cnt !=0

Write master block

fifo_data fifof_empty write_byte_cnt reg_write_addr bits_idntity addr_incr_identity fifo_read_req write_done Write master

avl_wait_req

avl_write av_write_data avl_address

Working of write master block

1)If the FIFO contains any data the write master automatically starts transferring that data in to the destination memory location. 2)This process will continue until the FIFO becomes empty. 3)If possible it may write in to one or more memory locations at a time. 4)The address will incremented by multiples of 4 and write count value will be decremented by 1.

State diagram for write operation

rst=0 idl e

Fifo empty =1

Fifo empty =0 Initial addr

Read data Read cnt=0 done

Read cnt !=0

FIFO BLOCK DIAGRAM

Almost full data wr_req rd_req q

FIFO
empty

Working of fifo

The fifo will buffers between read master and write master. When the fifo contains data to be transferred the fifo makes read bit high indicating the data to be write is present. The almost full value of the fifo is 220 and full value is 256.

Features of DMA

By using this DMA module we can write the data or video files in to two memory locations at a time.

Advantages of DMA

1.Computer system performance is improved by direct transfer of data between memory and I/O devices, without using processor. 2.processor is free to perform other operations while DMA is performing transferring data.

THANK Q