Analog to Digital Conversion

ADC Essentials A/D Conversion Techniques Interfacing the ADC to the IBM PC DAS (Data Acquisition Systems) How to select and use an ADC A low cost DAS for the IBM PC

Why ADC ?

Digital Signal Processing is more popular

Easy

to implement, modify, Low cost

Data from real world are typically Analog Needs conversion system
from

raw measurements to digital data Consists of

Amplifier,

Filters Sample and Hold Circuit, Multiplexer ADC

Chap 0 2

ADC Essentials

n bits ADC Number of discrete output level : 2n Quantum

Basic I/O Relationship

ADC is Rationing System

LSB size Q = LSB = FS / 2n

x = Analog input / Reference

Fraction: 0 ~ 1

Quantization Error 1/2 LSB Reduced by increasing n

Chap 0

Converter Errors

Offset Error

Integral Linearity Error

Gain Error

Differential Linearity Error

Chap 0

Can be eliminated by initial adjustments

Nonlinear Error
Hard

to remove

Terminologies

Converter Resolution The smallest change required in the analog input of an ADC to change its output code by one level Converter Accuracy The difference between the actual input voltage and the full-scale weighted equivalent of the binary output code Maximum sum of all converter errors including quantization error

Conversion Time Required time (tc) before the converter can provide valid output data Converter Throughput Rate The number of times the input signal can be sampled maintaining full accuracy Inverse of the total time required for one successful conversion Inverse of Conversion time if No S/H(Sample and Hold) circuit is used
5

Chap 0

More on Conversion Time

Input voltage change during the conversion process introduces an undesirable uncertainty Full conversion accuracy is realized only if this uncertainty is kept low below the converters resolution
Rate

Example 8-bit ADC Conversion Time: 100sec Sinusoidal input vi A sin(2 ft )

Rate of change

dvi 2 fA cos(2 ft ) 2 fA dt

Let FS = 2A

2 fA f

dV FS ( )max n dt 2 tc

of Change x tc resolution

2A 2 n tc 12.4 Hz

1 2 tc
n

Limited to Low frequency of 12.4 Hz

Few Applications
6

Chap 0

S/H increase Performance

S/H (Sample and Hold)

Analog

Example

circuits that quickly samples the input signal on command and then holds it relatively constant while the ADC performs conversion Aperture time (ta)

20 nsec aperture time

1 2 ta
n

62.17 KHz

Reasonably good for 100sec converter

Chap 0

Time delay occurs in S/H circuits between the time the hold command is received and the instant the actual transition to the hold mode takes

Analog Input Signal

Typically, Differential or Single-ended input signal of a single polarity

Typical Input Range 0 ~ 10V and 0 ~ 5V
If

Matching input signal and input range

Prescaling input signal using OP Amp

Actual input signal does not span Full Input range

In a final stage of preconditioning circuit

Chap 0

Some of the converter output code never used Waste of converter dynamic range Greater relative effects of the converter errors on output

By proportionally scaling down the reference signal

If reference signal is adjustable

Converting bipolar to unipolar

Using unipolar converter when input signal is bipolar

Scaling

Input signal is scaled and an offset is added Add offset scaled

down the

input Adding an offset

Bipolar Converter
If

polarity information in output is desired Bipolar input range

Typically, 0 ~ 5V

Chap 0

Bipolar Output 2s Complement Offset Binary Sign Magnitude

Outputs and Analog Reference Signal

I/O of typical ADC

Errors in reference signal

From Initial Adjustment Drift with time and temperature Cause Gain error in Transfer characteristics

ADC output
Number of bits 8 and 12 bits are typical 10, 14, 16 bits also available Typically

To realize full accuracy of ADC

Precise

and stable reference is crucial

Typically, precision IC voltage reference is used
5ppm/C ~ 100ppm/C
10

natural

binary
Chap 0

BCD (3 BCD)
For digital panel meter,

Control Signals

HBE / LBE
From CPU To read Output word after EOC

Start
From CPU Initiate the conversion process

HBE
High Byte Enable

BUSY / EOC
To CPU Conversion is in progress

LBE
Low Byte Enable

0=Busy: In progress 1=EOC: End of Conversion

Chap 0

11

A/D Conversion Techniques

Counter or Tracking ADC Successive Approximation ADC

Most

Commonly Used

Dual Slop Integrating ADC Voltage to Frequency ADC Parallel or Flash ADC
Fast

Conversion

Software Implementation Shaft Encoder

12

Chap 0

Counter Type ADC

Block diagram

Operation Reset and Start Counter DAC convert Digital output of Counter to Analog signal Compare Analog input and Output of DAC

Vi < VDAC
Continue counting

Vi = VDAC
Stop counting

Waveform

Digital Output = Output of Counter Disadvantage Conversion time is varied

2n Clock Period for Full Scale input

13

Chap 0

Tracking Type ADC

Tracking or Servo Type

Using Up/Down Counter to track input signal continuously

For slow varying input

Can be used as S/H circuit By stopping desired instant Digital Output Long Hold Time Disabling UP (Down) control, Converter generate Minimum (Maximum) value reached by input signal over a given period

Chap 0

14

Successive Approximation ADC

Most Commonly used in medium to high speed Converters Based on approximating the input signal with binary code and then successively revising this approximation until best approximation is achieved SAR(Successive Approximation Register) holds the current binary value

Block Diagram

Chap 0

15

Successive Approximation ADC

Circuit waveform

Conversion Time
n clock for n-bit ADC Fixed conversion time

Serial Output is easily generated

Logic Flow

Bit decision are made in serial order

Chap 0

16

Dual Slope Integrating ADC

Operation T1 Integrate 0 vi dt t2 Reset and integrate 0 Vr dt Thus T1vi ( AVG ) t2Vr t v Vr 2 i ( AVG ) Applications T1 DPM(Digital Panel Meter), DMM(Digital Multimeter),

Excellent Noise Rejection High frequency noise cancelled out by integration Proper T1 eliminates line noise Easy to obtain good resolution Low Speed If T1 = 60Hz, converter throughput rate < 30 samples/s

Chap 0

17

Voltage to Frequency ADC

VFC (Voltage to Frequency Converter) Convert analog input voltage to train of pulses Counter Generates Digital output by counting pulses over a fixed interval of time

Low Speed Good Noise Immunity High resolution

For slow varying signal With long conversion time

Applicable to remote data sensing in noisy environments

Digital transmission over a long distance

Chap 0

18

Parallel or Flash ADC

Very High speed conversion Up to 100MHz for 8 bit resolution Video, Radar, Digital Oscilloscope Single Step Conversion 2n 1 comparator Precision Resistive Network Encoder Resolution is limited Large number of comparator in IC

Homework #5-1 .

Chap 0

19

Software Implementation

Implementation with software using microprocessor

Counting Shifting Inverting Code Conversion

Limited Practical Use

Availability of Good performance with very reasonable Cost

Chap 0

20

Shaft Encoder

Elctromechanical ADC Convert shaft angle to digital output Encoding Optical or Magnetic Sensor Applications Machine tools, Industrial robotics, Numerical control

Binary Encoder Misalignment of mechanism causes large error

Ex: 011 111 (180deg)

Gray Encoder Misalignment causes 1 LSB error

Chap 0

21

Interfacing the ADC to the IBM PC

Interface Operations Most-recent-data Scheme

Using CPU Interrupt

At end of conversion it updates an output FIFO Automatically start new conversion CPU read FIFO to acquire most recent data CPU initiate conversion every time it needs new data CPU check EOC until conversion is finished

Start-and-wait Scheme

CPU initiate conversion every time it needs new data CPU can proceed to do other thing ADC interrupt CPU when conversion is complete CPU goes to ISR

See Chapter 3, For more information about 8259A

Chap 0

22

Interface Software

Memory Mapped Transfers ADC is assigned in Memory Space

MRD, MWR signal MOV instruction

More complex decoding logic I/O Mapped Transfers ADC is in I/O Space

IOR, IOW signal IN, OUT instruction

More Simple decoding logic

DMA (Direct Memory Access) CPU release system bus by the request of DMA DMA controller carried out data transfer by generating the required addresses and control signals The system bus control reverts back to CPU when data transfer is finished DMA is useful High Speed High volume data transfer

Disk Drive interface

23

Chap 0

Interface Hardware

Parallel Data Format

Three state output buffer in ADC To Interface ADC

Serial Data Format

Asynchronous Serial transmission to send data over long distance to a monitoring station

CPU + Decoding logic

To generate Chip Select signal To generate Start Signal To Check EOC signal

UART is commonly used

Interfacing 10 or 12 bit ADC

Transfer data in chunks of 8 bits one after another

24

Chap 0

DAS (Data Acquisition System)

DAS performs the complete function of converting the raw outputs from one or more sensors into equivalent digital signals usable for further processing, control, or displaying applications

Applications
Simple monitoring of a single analog variable Control and Monitoring of hundreds of parameters in a nuclear plant

Chap 0

25

Single Channel System

Transducer

Generate signal of low amplitude, mixed with undesirable noise

Amplifier, Filters
Amplify Remove noise Linearize

S/H (Sample and Hold) Reduce uncertainty error in the converted output when input changes are fast compared to the conversion time In Multi-channel system

To hold a sample from one channel while multiplexer proceed to sample next one Simultaneous sampling of two signal

Chap 0

26

Sample and Hold Circuits

Care in selecting hold capacitor Ch Low Value

Reduces acquisition time Increase Droop

Minimize Droop Increase acquisition time

High Value

Choose capacitor to get a best acquisition time while keeping the droop per conversion below 1 LSB

Chap 0

27

Commercially Available S/H

Chap 0

28

Multi-channel System

Analog multiplexer and a ADC

Local ADCs and digital multiplexer

Low cost

Higher sampling rate

Chap 0

29

How to select and use an ADC

Range of commercially available ADCs

Guidelines for using ADCs

Use the full input range of the ADC Use a good source of reference signal Look out for fast input signal changes Keep analog and digital grounds separate Minimize interference and loading problem

Chap 0

30

Commercially available monolithic ADCs

Chap 0

31

Commercially available hybrid ADCs

Chap 0

32

A low cost DAS for the IBM PC

Multi-channel system
Less than $100 ADC0816 from National Semiconductor Constant, repetitive rate

Generating clock For starting ADC conversion For causing interrupt Make a pulse stream from TCLK with short pulses of duration = x BCLK/4

TCLK from 8253 Timer/Counter

Wide pulse

1000 samples/s

Chap 0

33

ADC circuit for PC prototype board

SCSLCT (Start Conversion SeLeCT) : Latched trough port 30CH SCSLCT = H Selection of 30AH (/E10) start conversion SCSLCT = L TCLK start conversion INTSLCT (INTerrupt SeLeCT) : Latched trough port 30CH INTSLCT = H EOC cause IRQ2 INTSLCT = L No Interrupt CPU read Status register (Port 309H) to check EOC
Chap 0 34

Status Register

For polling TCLK and EOC signal Port 309H (/E9) Polling of EOC results in a low level after the data from ADC have been read

Chap 0

35

Throughput rate calculation

4.77MHz / 8 = 596KHz

Chap 0

36

Accuracy Calculation

Better than 1% accuracy is ensured Actual accuracy with smooth input signal at room temperature will be better than 0.5%

Chap 0

37

Basic Program for Controlling ADC

Sampling rate < 200 samples/s Because OUT and IN instruction in Basic takes 5ms

Chap 0

38

C Programming for Controlling ADC

Chap 0

Sampling from ADC channel 1 at 5ms interval and sending each sampled data point to the DAC

39

Homework #5-2

Prototype board C program

Outp(CNTRL,5) .

Chap 0

40