I7s Core

K. Pramod Kumar Reddy 12011D0624

Introduction
Now-a-days we are surrounded with many electronic gadgets which simplify our daily tasks. Many electronic gadgets are essentially computing devices with some extra components attached to accomplish the task for which they are designed for. For any computing device the heart is the component called Processor which is named because of its functionality i.e. it is mainly used to process data (for example addition, multiplication etc.) Over years, the architecture of the processors was subjected to many changes thanks to the advancement in VLSI technology and also due to efficient algorithms. Without the name of Intel the advancements in processor technology over years can not be described. Intel Corporation is an American multinational semiconductor chip maker corporation headquartered in Santa Clara, California. Intel is the world's largest and highest valued semiconductor chip maker.

 The Intel 4004 was a 4-bit central processing unit (CPU) released by Intel Corporation in 1971. It was the first complete CPU on one chip, and also the first commercially available microprocessor. Such a feat of integration was made possible by the use of then-new silicon gate technology allowing a higher number of transistors and a faster speed than was possible before. The processors released by Intel have underwent remarkable changes over time in terms of speed of operation, power consumption etc. The latest processor released by the Intel is Core i7

CORE i7
Core i7 architecture has certain remarkable features which help in improvement of speed of operation etc. Features include out-of-order execution for the purpose of instruction level parallelism, data level parallelism and also uniqueness in its pipeline architecture. The Intel Core i7 Processor is a new micro architecture based on a 45 nm process and designed to deliver high performance with power efficiency. Intel Core i7 is an Intel brand name for several families of desktop and laptop 64-bit x86-64 processors using the Nehalem, Westmere, Sandy Bridge and Ivy Bridge micro architectures. The Core i7 brand is targeted at the business and high-end consumer markets for both desktop and laptop computers, and is distinguished from the Core i3 (entry-level consumer), Core i5 (mainstream consumer), and Xeon (server and workstation) brands.

 In-order processors In earlier processors, the processing of instructions is normally done in these steps: Instruction fetch. If input operands are available (in registers for instance), the instruction is dispatched to the appropriate functional unit. If one or more operand is unavailable during the current clock cycle (generally because they are being fetched from memory), the processor stalls until they are available. The instruction is executed by the appropriate functional unit. The functional unit writes the results back to the register file. Out-of-order processors This new paradigm breaks up the processing of instructions into these steps: Instruction fetch. Instruction dispatch to an instruction queue (also called instruction buffer or reservation stations).

 The instruction waits in the queue until its input operands are available. The instruction is then allowed to leave the queue before earlier, older instructions. The instruction is issued to the appropriate functional unit and executed by that unit. The results are queued. Only after all older instructions have their results written back to the register file, then this result is written back to the register file. This is called the graduation or retire stage. The key concept of OoO processing is to allow the processor to avoid a class of stalls that occur when the data needed to perform an operation are unavailable. In the outline above, the OoO processor avoids the stall that occurs in step (2) of the in-order processor when the instruction is not completely ready to be processed due to missing data. The benefit of OoO processing grows as the instruction pipeline deepens and the speed difference between main memory (or cache memory) and the processor widens. On modern machines, the processor runs many times faster than the memory, so during the time an in-order processor spends waiting for data to arrive, it could have processed a large number of instructions.

 OoO processors fill these "slots" in time with other instructions that are ready, then re-order the results at the end to make it appear that the instructions were processed as normal. The way the instructions are ordered in the original computer code is known as program order, in the processor they are handled in data order, the order in which the data, operands, become available in the processor's registers. Fairly complex circuitry is needed to convert from one ordering to the other and maintain a logical ordering of the output; the processor itself runs the instructions in seemingly random order.

INTEL CORE I7 DETAILED INTERNAL ARCHITECTURE

FEATURES OF NEHALEM ARCHITECTURE

The architecture which is more popular and mostly used in Intel i7 family is Nehalem architecture which is the code name coined by Intel. Hyper-threading reintroduced. 412 MB L3 cache. Second-level branch predictor and translation look aside buffer. Native (all processor cores on a single die) quad- and octa-core processors Intel Quick Path Interconnect in high-end models replacing the legacy front side bus which offers many features like high bandwidth, less pins to connect the bus etc. 64 KB L1 cache/core (32 KB L1 Data + 32 KB L1 Instruction) and 256 KB L2 cache/core. Integration of PCI Express and DMI into the processor in mid-range models, replacing the northbridge. Integrated memory controller supporting two or three memory channels of DDR3 SDRAM or four FB-DIMM2 channels 2nd generation Intel Virtualization Technology which introduced Extended Page Table support, virtual processor identifiers (VPIDs), and non-maskable interrupt-window exiting.

Intel Quickpath Interconnect

Intel X58 Arch Replaced front side bus Max width: 20 bit Max bandwidth: 16GB/s Unidirectional

 The QuickPath architecture differs considerably from earlier Intel architectures, and is much closer to AMD's Hypertransport architecture. Except for the lack of a memory interface, the X58 is similar to the traditional northbridge: it communicates with the processor(s) via the high bandwidth QuickPath Interconnect it communicates with the Southbridge via Direct Media Interface (DMI), and it communicates with high bandwidth peripherals via PCI Express (PCIe). QPI operates at a clock rate of 2.4 GHz, 2.93 GHz, or 3.2 GHz. The clock rate for a particular link depends on the capabilities of the components at each end of the link and the signal characteristics of the signal path on the printed circuit board. The non-extreme Core i7 9xx processors are restricted to a 2.4 GHz frequency at stock reference clocks. Bit transfers occur on both the rising and the falling edges of the clock, so the transfer rate is double the clock rate.

 Intel describes the data throughput (in GB/s) by counting only the 64-bit data payload in each 80-bit "flit". However, Intel then doubles the result because the unidirectional send and receive link pair can be simultaneously active. Thus, Intel describes a 20-lane QPI link pair (send and receive) with a 3.2 GHz clock as having a data rate of 25.6 GB/s. A clock rate of 2.4 GHz yields a data rate of 19.2 GB/s. More generally, by this definition a two-link 20-lane QPI transfers eight bytes per clock cycle, four in each direction.

Peripherals System memory

CPU

Intel QPI

High Speed I/O Controller

DMI

Legacy and Low Speed I/o Controller

BIOS High Speed I/O

 Hyper-threading works by duplicating certain sections of the processor those that store the architectural statebut not duplicating the main execution resources. This allows a hyper-threading processor to appear as the usual "physical" processor and an extra "logical" processor to the host operating system (legacy operating systems see two "physical" processors), allowing the operating system to schedule two threads or processes simultaneously and appropriately. When execution resources would not be used by the current task in a processor without hyperthreading, and especially when the processor is stalled, a hyper-threading equipped processor can use those execution resources to execute another scheduled task. (The processor may stall due to a cache miss, branch mis prediction, or data dependency) This technology is transparent to operating systems and programs. The minimum that is required to take advantage of hyper-threading is symmetric multiprocessing (SMP) support in the operating system, as the logical processors appear as standard separate processors.

 It is possible to optimize operating system behavior on multi-processor hyper-threading capable systems. For example, consider an SMP system with two physical processors that are both hyper-threaded (for a total of four logical processors). If the operating system's thread scheduler is unaware of hyper-threading it will treat all four processors as being the same. If only two threads are eligible to run, it might choose to schedule those threads on the two logical processors that happen to belong to one of the physical processors; that processor would become extremely busy while the other would be idle, leading to poorer performance than is possible with better scheduling. This problem can be avoided by improving the scheduler to treat logical processors differently from physical processors; in a sense, this is a limited form of the scheduler changes that are required for NUMA systems

References
Intel i7 homepage http://www.intel.com/products/processor/corei7/index.htm Intel Quickpath http://www.intel.com/technology/quickpath/introduction.pdf Intel Turboboost http://www.intel.com/technology/turboboost/index.htm Nehalem Arch http://www.intel.com/technology/architecture-silicon/next-gen/whitepaper.pdf Computer Architecture A Quantitative approach by JOHN L.HENNESSY , DAVID A. PATTERSON