Microcontrollers: The 8051 Family

Ajit Pal Professor

Department of Computer Science and Engineering

Indian Institute of Technology Kharagpur INDIA-721302

Architecture of the Intel 8051

Onchip oscillator and CPU Timing Memory Organization Register Organization Multifunction I/O ports

ALU capability of 8051

Reset Operation Interrupt structure The 8051 Family

Key Features of 8051

8-bit CPU On-chip oscillator Harvard architecture 4 KB of on-chip ROM 128 bytes of on-chip RAM 21 special function registers 32 I/O lines 64 KB address space for external Program memory 64 KB address space for external Data memory Two 16-bit timer/counters One full-duplex serial port Five-source interrupt structure with two priority levels Bit addressability for Boolean processing

Simplified Block Diagram of 8051

EXTERNAL INTERRUPTS 4K ROM INTERRUPT CONTROL INTERNAL INTERRUPTS

128 BYTES RAM

TIMER 1 TIMER 0

COUNTER INPUTS

CPU

OSC

BUS CONTROL

4 I/O PORTS

SERIAL PORT

TXD P0 P2 P1 P3

RXD

ADDRESS / DATA

Onchip oscillator and CPU Timing

30pF 1.24 to 12 MHz. XTAL1 30pF XTAL2 External clock generator XTAL2

XTAL1

Clock Phases States Machine cycle ALE p1 p2 S1 p1 p2 p1 p2 p1 p2 p1 p2 S5 p1 p2 p1 p2 S1 p1 p2 S2

S2

S3 S4 Machine cycle

S6

Ajit Pal, IIT Kharagpur

8051 Memory Map

FFFF

FFFF

EXTERNAL

1000

0FFF

EXTERNAL DATA RAM FF

EXTERNAL ROM

INTERNAL ROM 0000

SFR 80 7F INTERNAL DATA RAM 00 0000

Register Organization of 8051

General purpose registers 4 banks of 8-registers Twenty one Special function registers A , B , DPL, DPH, IE , IP , P0 , P1 , P2 , P3 , PCON, PSW, SCON, SBUF, SP, TMOD, TCON, TL0, TH0, TL1, TH1

Special Function Register of 8051

NAME Function RAM ADDRESS E0 F0 83 NAME Function A* B* DPH Accumulator Arithmetic External Memory Address. External memory Address. IE* IP* Interrupt Enable Interrupt Priority Control I/O Port I/O Port I/O Port A8 B8 RAM ADDRESS

SCON*
SBUF

Serial Port
Serial Data Buffer. Stack Pointer

98
99

DPL

82

SP

81

TMOD

T/C Mode Control

T/C Control Timer 0 Lower

89

TCON* TL0

88 8A

P0* P1* P2*

80 90 A0

order byte
TH0 Timer 0 Higher order byte Timer 1 Lower order byte Timer 1 Higher order byte 8C

P3*
PCON PSW

I/O Port
Power Control Program Status Word

B0
87 D0

TL1

8B

TH1

8D

Program Status Word

BITS: 7 6 5 4 3 2 1 0 P

CY AY Carry Auxiliary-Carry

F0 RS1 RS0 OV

0 User Flag 0 1 1

0 1 0 1

Parity: 0-even 1-odd Reserved Overflow Bank 0 Bank 1 Bank 2 Bank 3

Interrupt Structure of 8051

5 interrupts apart from RESET Interrupts can be individually enabled/disabled Each source can be programmed to two priority levels
INTERRUPTS INTO TIMER0 FUNCTIONS VECTOR ADDRESS External Interrupt 0003H on PIN P3.2 Overflow of Timer0 000BH activates TF0 External interrupt 0013H on PIN P3.3 Overflow of Timer1 001BH activates TF1 Completion of 0023H transmission/reception

INT1
TIMER1 SERIAL

Ports of 8051
P0 While accessing external memory provides lower order byte of address (A0-A7) Otherwise acts as normal port line
ADDR / DATA CONTROL READ LATCH D Q Q2 MUX VCC Q1 P0.X PIN

INT.BUS WRITE TO LATCH READ PIN

P0.X LATCH CL Q

Ports of 8051
P1: Port 1 has no dual function. It is simply used as programmable bi-directional I/O Port.

READ LATCH D Q

VCC

*
P1.X LATCH CL Q

INTERNAL PULL-UP P1.X PIN Q1 High for two Oscillator period

VCC Week depletion mode FET

INT.BUS WRITE TO LATCH READ PIN

Ports of 8051
P2: While accessing external memory provides higher order byte of address (A8-A15) Otherwise acts as normal port line
ADDR CONTROL VCC INTERNAL PULL-UP READ LATCH MUX INT.BUS WRITE TO LATCH READ PIN D Q Q1 P2.X LATCH CL Q

*
P2.X PIN

Ports of 8051
Port Pin Name Alternate Function Serial input port P3.0
ALTERNATE OUTPUT FUNCTION VCC

RXD

P3.1
INTERNAL PULL-UP

TXD

*
READ LATCH D Q P3.X LATCH CL Q

Serial output port

External interrupt External interrupt Timer 0 external input Timer 1 external input External Data memory write store

P3.2
P3.X PIN Q1

INT0

INT.BUS WRITE TO LATCH READ PIN

P3.3

INT1

P3.4

T0

ALTERNATE INPUT FUNCTION

P3.5

T1

P3.6

WR

P3.7

RD

External Data memory Read store

Reset Operation Of 8051

Register Content 0000H 00H 00H 00H 07H 0000H 0FFH (XXX00000) (0XX00000) 00H 00H 00H 00H 00H

By holding RST pin high for two machine cycles On reset the registers have the following contents: PC, A, B, PSW, DPTR, TMOD, TCON, TH0, TL0, TH1, TL1 all are initialized to zero. SP 07H, P0 P3 0FFH, IP xxx00000, IE 0xx00000, PCON 0xxxxxxx, SBUF xxxxxxxx.

PC A B PSW SP DPTR P0-P3 IP IE TMOD TCOM THO TH1 TL1

SCOM
SBUF PCON

00H
Indeterminate (0XXXXXXX)

8051 Family
FEATURE
ROM RAM I/O Serial I/O Timer Interrupt Sources

8051 8031
4K 128 32 1 2 6 0K 128 32 1 2 6

8751
EPROM 4K 128 32 1 2 6

8052
8K 256 32 1 3 8

AT89C51

DS500-8

FLASH 4K NVRAM 8K 128 32 1 2 6 128 32 1 2 6

Ajit Pal, IIT Kharagpur

Low Power Features

ATMEL microprocessors provide several power saving options, which can be used to reduce power dissipation of the processor for battery operated systems The operating frequency of ATMEL 89C51 is from 0 to 24 MHz. Since P V2 dd.f, low-power circuits can be realized in applications where high performance is not required The processor can also be put to sleep, but the onchip peripherals remain in the active state One can invoke the idle mode by software means simply by setting the IDLE bit of the PCON special function register The IDLE bit of PECON register is cleared, which terminates the IDLE mode

Applications
Household items
Toys TVs Microwave oven Washing Machine Garage door opener Home securing system Vacuum cleaner

Office Equipment FAX machines Printers Plotters Mouse

Communication Cordless phones Cellular phones Pagers Answering machine Smart cards

Thanks!

Ajit Pal, IIT Kharagpur