Beruflich Dokumente
Kultur Dokumente
FEATURES
8-bit CPU optimized for control applications Extensive Boolean processing (Single-bit logic) capabilities 64K Program Memory address space 64K Data Memory address space 4K bytes of on-chip Program Memory 128 bytes of on-chip Data RAM 32 bidirectional and individually addressable 1/0 lines Two 16-bit timer/counters Full duplex UART 6-source/5-vector interrupt structure with two priority levels On-chip clock oscillator
3
PIN DETAILS
P1 P0
RESET
+ _
P3
P2
XTAL
SKB's
BLOCK DIAGRAM
Interrupt Control
4K ROM
128 RAM
Timer 0 Timer 1
CPU
OSC
Bus Control
4 I/O Ports
Serial Port
TXD RXD
P0
P1
P2
P3
ARCHITECURE
All
SKB's
ARCHITECURE
ARCHITECURE
ARCHITECURE
MEMORY STRUCTURE
External
60K
64K
External
SFR
64K
EXT
EA = 0
INT
EA = 1
4K
Program Memory
SFR
11
BIT Addressable Area 128 BYTE INTERNAL RAM Reg Bank 3 Reg Bank 2 Register Banks Reg Bank 1 Reg Bank 0
12
R0 R1 R2 R3 R4 R5 R6 R7 R0 R1 R2 R3 R4 R5 R6 R7
Bank 1
Bank 0
R0 R1 R2 R3 R4 R5 R6 R7
R0 R1 R2 R3 R4 R5 R6 R7
CY
AC
F0
RS1 RS0 OV
P
13
SFR
F8 F0 E8 E0 D8 D0 C8 PSW Acc B FF F7 EF E7 DF D7 CF
C0
B8 B0 A8 A0 98 90 88 80 IP P3 IE P2 SCON P1 TCON P0 TMOD SP TL0 DPL TL1 DPH TH0 TH1 PCON SBUF
C7
BF B7 AF A7 9F 97 8F 87
14
UNIT - III
15
TIMERS Timer 0
Mode 0 Mode 1 Mode 2 Mode 3
18
Timer 1
Mode 0 Mode 1 Mode 2
TIMER / COUNTER
OSC 12
C /T 0
TL
TH
TF
(1 Bit)
C /T 1
(8 Bit) (8 Bit)
T PIN
TR
Gate
INT PIN
INTERRUPT
19
TIMER 0
OSC 12
C /T 0
TL0 TH0
TF0
C /T 1
T 0PIN
TR0
Gate
INT 0 PIN
INTERRUPT
x
20
TIMER 0 Mode 0
13 Bit Timer / Counter
OSC 12
T 0PIN
TR0
Gate
INT 0 PIN
C /T 0
C /T 1
TF0
INTERRUPT
TIMER 0 Mode 1
16 Bit Timer / Counter
OSC 12
T 0PIN
TR0
Gate
INT 0 PIN
C /T 0
C /T 1
TF0
INTERRUPT
TIMER 0 Mode 2
8 Bit Timer / Counter with AUTORELOAD
OSC 12
T 0PIN
TR0
Gate
INT 0 PIN
C /T 0
C /T 1
TL0 (8 Bit)
Reload
TF0
INTERRUPT
TH0 (8 Bit)
TIMER 0 Mode 3
Two - 8 Bit Timer / Counter
OSC 12
T 0PIN
TR0
Gate
INT 0 PIN
C /T 0
C /T 1
TL0 (8 Bit)
TF0
INTERRUPT
OSC
12
TH0 (8 Bit)
TF1
INTERRUPT
TR1
24
TIMER 1
OSC 12
C /T 0
TL1 TH1
TF1
C /T 1
T1PIN
TR1
Gate
INT 1 PIN
INTERRUPT
25
TIMER 1
OSC 12
C /T 0
TL1 TH1
TF1
C /T 1
T1PIN
TR1
Gate
INT 1 PIN
INTERRUPT
Y
26
TIMER 1 Mode 0
13 Bit Timer / Counter
OSC 12
T1PIN
TR1
Gate
INT 1 PIN
C /T 0
C /T 1
TF1
INTERRUPT
TIMER 1 Mode 1
16 Bit Timer / Counter
OSC 12
T1PIN
TR1
Gate
INT 1 PIN
C /T 0
C /T 1
TF1
INTERRUPT
TIMER 1 Mode 2
8 Bit Timer / Counter with AUTORELOAD
OSC 12
T1PIN
TR1
Gate
INT 1 PIN
C /T 0
C /T 1
TL1 (8 Bit)
Reload
TF1
INTERRUPT
TH1 (8 Bit)
Timer 1
Timer 0
TCON
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
Timers
Interrupt
30
Write to BUFFER
S
Q D CL
SBUFF
Zero Detector
RXD O/P
Start
Shift
TX Control
CLK
TX Clock TI Send
RI
Receive Shift
TXD
Shift Clock
RI REN
RX Control
Start 1 1 1 1 1 1 1 0
RXD I/P
Load to BUFFER
SBUFF
Read From BUFFER
SKB's 32
SKB's
33
SKB's
34
35
36
SKB's
37
38
39
SKB's
40
41
42
SKB's
43
44
PCON
SMOD
GF1
GF0
PD
IDL
45
INTERRUPTS
The Interrupt structure has the following features: 6 sources / 5 vectored interrupts Each interrupts can be individually programmable Each interrupts can have two priority levels Priority levels can be programmed All interrupts can be masked by a single bit - EA External interrupt type can be programmed Edge triggered Level Triggered
47
TIMER / COUNTER
INT 0
IE0
TF 0
INT 1
IE1 INTERRUPT SOURCES
TF1
TI RI
48
TIMER / COUNTER
IE Reg IP Reg
INT 0
0 IT 0 1
IE0
TF 0
0
INT 1
IT1
IE1
TF1
TI RI
Individual Enable Global Disable Low Priority Interrupt
49
EA
ES
ET1
EX1
ET0
EX0
PS
PT1
PX1
PT0
PX0
TCON
TR0
SKB's
IE1
IT1
IE0
IT0
50
51
MEMORY INTERFACING
External RAM Interfacing :-
P1
P0
Data
EXT RAM
MCS 51
P3 ALE P2
ALE
Address
WR
RD
RD WR
52
MEMORY INTERFACING
External RAM Interfacing :D0
AD0
D CLK
A0 D1
AD1
D
CLK
A1 D2
AD2
D CLK
A2 D3
AD3
D CLK
A3
53
MEMORY INTERFACING
External ROM Interfacing :-
P1
P0
Instr
EA
EXT ROM
ALE
MCS 51
P3 ALE P2
EEPROM
Address
PSEN
CE
54
55
Instruction Set
5 Groups Arithmetic Operation Group Logical Operation Group Data Transfer Group Boolean Variable Manipulation Group Program Branching Group
56
Instruction Set
5 Groups Arithmetic Operation Group Logical Operation Group Data Transfer Group Boolean Variable Manipulation Group Program Branching Group
57
58
59
60
61
62
63
Instruction Set
5 Groups Arithmetic Operation Group Logical Operation Group Data Transfer Group Boolean Variable Manipulation Group Program Branching Group
64
68
Instruction Set
5 Groups Arithmetic Operation Group Logical Operation Group Data Transfer Group Boolean Variable Manipulation Group Program Branching Group
69
Instruction Set
5 Groups Arithmetic Operation Group Logical Operation Group Data Transfer Group Boolean Variable Manipulation Group Program Branching Group
74
Boolean Variable Manipulation Group CLR C CLR bit SETB C SETB bit CPL C CPL bit
75
Boolean Variable Manipulation Group ANL ANL ORL ORL MOV MOV C,bit C,/bit C,bit C,/bit C,bit bit,C
76
Boolean Variable Manipulation Group JC rel JNC rel JB bit,rel JNB bit,rel JBC bit,rel
77
Instruction Set
5 Groups Arithmetic Operation Group Logical Operation Group Data Transfer Group Boolean Variable Manipulation Group Program Branching Group
78
79
80
81
UNIT - IV
82
UNIT - IV
83
8255
Programmable Peripheral Interface
24 Programmable I/O pins Three Configurable Ports - A,B & C BSR Mode TTL Compatible
84
8255
Programmable Peripheral Interface
SKB's
85
8255
Programmable Peripheral Interface
86
8255
Programmable Peripheral Interface
A1 0 0 1 1
A0 0 1 0 1
87
8255
Programmable Peripheral Interface
Control Word General
D7 D6 D5 D4 D3 D2 D1 D0
Group A
Mode Selection 00 = Mode 0 01 = Mode 1 1x = Mode 2 PortA 1 = Input 0 = Output PortC (Upper) 1 = Input 0 = Output BSR Mode Select 0 = BSR Mode Enabled 1 = BSR Mode Enabled SKB's
Group B
PortC (Lower) 1 = Input 0 = Output PortB 1 = Input 0 = Output Mode Selection 0 = Mode 0 1 = Mode 1
88
8255
Programmable Peripheral Interface
Control Word
BSR Mode
D7 D6 D5 D4 D3 D2 D1 D0
Bit Set/Reset X X X
Not Used 1 = Set 0 = Reset
Bit Select
000 = Bit 0 001 = Bit 1 010 = Bit 2 011 = Bit 3 100 = Bit 4 101 = Bit 5 110 = Bit 6 111 = Bit 7 89
0
BSR Mode Selected
8255
Programmable Peripheral Interface
Mode 0 :-
90
8255
Programmable Peripheral Interface
Mode 1 :-
91
8255
Programmable Peripheral Interface
Mode 2 :-
92
8253
Programmable Interval Timer
3 Independent 16bit Counters DC - 2.6MHz BCD or Binary Counting Programmable Counting Modes Single Supply Operations
93
8253
Programmable Interval Timer
Pin Diagram :-
94
8253
Programmable Interval Timer
Block Diagram :-
SKB's
95
8253
Programmable Interval Timer
System Interface :-
96
8253
Programmable Interval Timer
Control Word
SC1 SC0 RL1 RL0 M2 M1 M0 BCD
Read / Load
00 = Counter Latching 01 = Read/Load MSB only 10 = Read/Load LSB only 11 = Read/Load LSB first then MSB
Binary / BCD
1 = BCD 0 = Binary
Mode Select
000 = Mode 0 001 = Mode 1 X10 = Mode 2 X11 = Mode 3 100 = Mode 4 101 = Mode 5
Select Counter
00 = Select Counter 0 01 = Select Counter 1 10 = Select Counter 2 11 = Illegal
97
8253
Programmable Interval Timer
Mode 0 :-
98
8253
Programmable Interval Timer
Mode 1 :-
99
8253
Programmable Interval Timer
Mode 2 :-
100
8253
Programmable Interval Timer
Mode 3 :-
101
8253
Programmable Interval Timer
Mode 4 :-
102
8253
Programmable Interval Timer
Mode 5 :-
103
8279
Programmable Keyboard / Display Interface
Simultaneous Keyboard & Display Drive Scanned Keyboard Mode Scanned Sensor Mode 8-Character Keyboard FIFO Duel 8 / 16 Numerical Display R / L Entry 16 bit Display RAM Mode Programmable From CPU Programmable Scan Timing Interrupt Output on Key Entry
104
8279
Programmable Keyboard / Display Interface
Pin Diagram :-
SKB's
105
8279
Programmable Keyboard / Display Interface
Signal Diagram :-
SKB's
106
8279
Programmable Keyboard / Display Interface
Block Diagram :-
SKB's
107
8279
Programmable Keyboard / Display Interface
System Interface :-
SKB's
108
8251
Programmable Communication Interface
Pin Diagram :-
109
8251
Programmable Communication Interface
Block Diagram :-
110
8251
Programmable Communication Interface
System Interface :-
111
8251
Programmable Communication Interface
8251
Programmable Communication Interface
113
UNIT - V
114
1) Stepper Motor Control 2) Matrix Keyboard 3) Dynamic 7 Segment Display 4) Analog to Digital converter 5) DC Motor Control 6) LCD Display 7) Serial Data Transfer
115
MATRIX KEYBOARD
General Keyboard Structure Adv & Disadv of General Keyboard Layout of Matrix Keyboard Scanning and Sense Lines Scan Sequence Key De-bounce Methods
7 8 9 5 6
MATRIX KEYBOARD
0 #
2 3
MATRIX KEYBOARD
Sense Lines RL2 RL1 RL0 SL0 Scan Lines
1 4 7
2 5 8 0
3 6 9 #
SL1
SL2 SL3
MATRIX KEYBOARD
SL3 SL2 SL1 SL0 RL2 RL1 RL0
0 0 1 0 0 1 0 0 1 1 0 0 1 0 0 1 0
1 2 3 4 5
RL2 RL1 RL0 SL0 SL1
0 0 0 01
0 0 1 0
0 1 0 0
1 0 0 0
0 1 0 0 1 0 0
1 4 7
2 5 8 0
3 6 9 #
1
0 0
0
0 1
0
1 0
6 7 8 9
0
SL2 SL3
MATRIX KEYBOARD
MATRIX KEYBOARD
gV
e d dp c
dp
Common
DC MOTOR CONTROL
DC Motor Speed Control Methods Advantage of PWM Method Driving Circuit
DC MOTOR CONTROL
LCD DISPLAY
Principle of LCD 16x2 LCD LCD Module Driver & Screen RAM Character Molding Display Type Cursor, L/R Entry etc
LCD DISPLAY
LCD DISPLAY
LCD DISPLAY
Pin number
1 2 3 4
Symbol
Vss Vcc Vee RS
Level
0/1
I/O
I
Function
Power supply (GND) Power supply (+5V) Contrast adjust 0 = Instruction input, 1 = Data input 0 = Write to LCD module, 1 = Read from LCD module Enable signal Data bus line 0 (LSB)
5 6 7
R/W E DB0
I I I/O
8
9 10 11 12 13 14
DB1
DB2 DB3 DB4 DB5 DB6 DB7
0/1
0/1 0/1 0/1 0/1 0/1 0/1
I/O
I/O I/O I/O I/O I/O I/O
Code Instruction
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Description
Executi on time
Clear display Cursor home Entry mode set Display On/Off control Cursor/disp lay shift Function set Set CGRAM address Set DDRAM address Read busyflag and address counter Write to CGRAM or DDRAM Read from CGRAM or DDRAM
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 1
1 *
Clears display and returns cursor to the home position (address 0). Returns cursor to home position (address 0). Also returns display being shifted to the original position. DDRAM contents remains unchanged. Sets cursor move direction (I/D), specifies to shift the display (S). These operations are performed during data read/write. Sets On/Off of all display (D), cursor On/Off (C) and blink of cursor position character (B). Sets cursor-move or display-shift (S/C), shift direction (R/L). DDRAM contents remains unchanged. Sets interface data length (DL), number of display line (N) and character font(F). Sets the CGRAM address. CGRAM data is sent and received after this setting. Sets the DDRAM address. DDRAM data is sent and received after this setting.
1.64mS
1.64mS
I/D
40uS
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 1
0 0 1
0 1 DL
1
S/C
D
R/L
C * *
B * *
40uS
40uS 40uS
CGRAM address
40uS
DDRAM address
40uS
BF
Reads Busy-flag (BF) indicating internal operation is being performed and reads CGRAM or DDRAM address counter contents (depending on previous instruction).
0uS
write data
40uS
read data
SKB's
140
40uS
LCD DISPLAY