EECE 374: Microprocessor Architecture and Applications

Chapter 1 (Part II)

Agenda (Chapter 1, Part II)

Part II 1. Number System Part II 2. ALU
Arithmetic Operations
Integer, Floating-Point number ADD, SUB, MUL, DIV

Logical Operations
AND, OR, NOT, XOR, etc.

Shift Operations
Logical Arithmetic

Number System
Radix r number (radix = 2, 8, 10, 16, etc.) p 1 q p 1q p 2 ...q0 .q1q2 ...qn qi * r i

i n

Complement
To represent negative data, we use Radix or Radix-1 complement Radix complement of A = rN - A Radix-1 complement of A = (rN -1) - A

Number System
Example
1111 + 1011 0100 1011 1111 1000 0111 1 1000 (2s complement) (1s complement) + C B Binary 15 3 C 15 4 B 15 5 A (15s complement) 1 B (16s complement) Hexadecimal

Binary Codes
Binary Codes (radix = 2)
Unsigned number:
No sign bit. N bits binary code: 0 ~ 2N-1

Signed number:
MSB is sign bit. 1s complement, 2s complement

Binary Codes
1s 2s complement Positive : same as unsigned number Negative : invert every bit complement Positive : same as unsigned number Negative : invert every bit, and add 1

Example 8bit binary code

Binary Codes
Sign-bit extension :
Positive : fill left with 0 Negative : fill left with 1 Example : 4bit 8bit
5 : 0101b 0000 0101b -5 : 1011b 1111 1011b

Binary Codes
Fast Conversion radix 2 8,16, radix 10 2
regard 3bits in binary as 1 digit of octal number. regard 4bits in binary as 1 digit of hexadecimal number. (cf. BCH)

Computer Data Formats

ASCII (text p36 Table1-8)
A way to represent alphanumeric character 7bit code (128 characters) Extended ASCII : 8bit code

Unicode
16bit code Can represent more characters than ASCII code.

BCD (Binary-Coded Decimal)

Decimal 12 623
910

Packed 0001 0010 0000 0110 0010 0011

0000 1001 0001 0000

Unpacked 0000 0001 0000 0010 0000 0110 0000 0010 0000 0011
0000 1001 0000 0001 0000 0000

Computer Data Formats

Example : Character printing by using ASCII code

Computer Data Formats

Byte-Sized Data
8bit data (00H ~ FFH) Unsigned byte
128 64 32 16 8 4 2 1

Signed byte
-128 64 32 16 8 4 2 1

Computer Data Formats

Word-Sized Data
16bit data (0000H ~ FFFFH) Little Endian(Intel), Big Endian 1234H
Little Endian 3003H 3002H 3001H 3000H 2FFFH 12H 34H High-order byte Low-order byte 3003H 3002H 3001H 3000H 2FFFH 34H 12H Low-order byte High-order byte Big Endian

Computer Data Formats

Doubleword-Sized Data
32bit data (00000000H ~ FFFFFFFFH) 12345678H
Little Endian 00103H 12H 00102H 34H 00101H 56H 00100H 78H 000FFH Low-order byte High-order byte 00103H 78H 00102H 56H 00101H 34H 00100H 12H 000FFH High-order byte Big Endian Low-order byte

Real Number (Floating point)

Agenda (Chapter 1)
Part II 1. Number System Part II 2. ALU
Arithmetic Operations
Integer, Floating-Point number ADD, SUB, MUL, DIV

Logical Operations
AND, OR, NOT, XOR, etc.

Shift Operations
Logical Arithmetic

ALU
What is ALU?
Arithmetic and Logical Unit

Arithmetic Operation
Integer, Floating-point number

Logical Operation
Binary data(0, 1)

Components of a ALU
Arithmetic Op. Logical Op. Complement Unit

Input Data Input Data Output Data Flags Control Signals

Shift Reg. Flag Reg.

Ways to represent Negative Number

Signed-magnitude
MSB is sign-bit, and MSB-1 ~ LSB are magnitude.

1s Complement
Neg. number with 1s complement

2s Complement
Neg. Number with 2s complement

Logic Operations
AND, OR, NOT, XOR, selective-set, selective-complement, mask, insert, compare, etc.
Bitwise operation
Example ) A = 1011 0101, B = 0011 1011 A AND B = 0011 0001

Shift Operation
Logical Shift 0
0 Circular Shift

It can be used to send data. (serial)

Shift Operation
Scheme of logical shift register

CLK

0
Right Sift R

Left Sift

Shift Operation
Arithmetic shift
Same as Logical Shift except MSB. Reason?
0

Arithmetic Op. (Integer)

Operation A A + 1 A A+B A AB A A*B Term Complement Addition Subtraction Multiplication

A A/B
A A+1 A A1

Division
Increment Decrement

Arithmetic Op. (ADD)

Addition :
Made up with full-adders (# of FA = # of bits) Add two input data What is Overflow ?
0011 = 3 + 0100 = 4 + 1101 = -3 0011 = 3 0110 = 6

0011 = 3
1001 = -7

0111 = 7

0000 = 0

Arithmetic Op. (ADD)

Overflow V = C4 XOR C5
Scheme of Parallel Adder

Arithmetic Op. (SUB)

Subtraction :
Can be converted into the sum of two integers.
0010 =2 0010 + =2

0110

=6

1010 = -6

1100 = -4

1100 = -4

Arithmetic Op. (SUB)

Subtracter = Adder + Complement unit
B reg. Complement Select Signal ( +, - )

Parallel Adder Sum A reg.

Carry

Arithmetic Op. (MUL)

A, B : n bits binary number C = A * B, C : ~2n bits binary number
Shift and Add
1 1 1 0 0 0 1 1 1 0 0 1 0 0 1 1 1 1 1 1 Product 0 1 0 0 1 1 1 0 1 1 1 0 Partial Product Multiplicand Multiplier

Arithmetic Op. (MUL)

Start
A 0, Q-1 0 M multiplicand, Q multiplier, Cnt n 10

Booth Algorithm
It can be used to multiply any combination of negative or positive number.
01

AA- M

Q0, Q-1

AA+ M

11, 00
Right Shift A,Q, Q-1 Cnt Cnt -1 no
Cnt = 0 ?

Arithmetic right shift

yes

End

Arithmetic Op. (DIV)

DV=QR
D : dividend, V : divisor, Q : quotient, R : remainder

Division can be made up with series of shift and add operations.

Arithmetic Op. (DIV)

Start
A 0, M divisor, Q dividend, Cnt n Left Shift A, Q AA- M no Q0 1 A<0? yes Q0 0 AA+ M

Flow chart of Unsigned n-bit number division - Q in the Q reg. - R in the A reg.

Cnt Cnt -1 no
Cnt = 0

yes

End

Floating Point
S Exponent(E) Significand(M)

N = (-1)S 2E-127 (1.M) : single-precision N = (-1)S 2E-1023 (1.M) : double-precision Overflow

Negative/Positive overflow/underflow

NAN (not a number)

Divide by zero Square root of a negative number M0 and E=FFH or E= 7FFH

Floating Point (ADD, SUB)

By shift the smaller input, make two inputs exponent be same.
1.101 23 + 1.111 25 + 0.0110125 1.1010025 10.0100125

1.001001 26

Why we shift the smaller one?

Floating Point (Pipelining)

N1 N2 Step 1 Shift Op.
Add mantissa

Pipelining can be used to speed-up ALU operation.

Step 2

Step 3 normalize N1 + N2

Floating Point (MUL, DIV)

N1
Step 1

N2
Step 1

N1

N2

Multiply two mantissas

Divide two mantissas

Step 2

Add two exponents

Step 2

Subtract two exponents

Step 3

normalize

Step 3

normalize

N1 N2

N1 N2

Floating Point (MUL, DIV)

Exponent overflow
Set result + or -

Exponent underflow
Set result 0

Mantissa underflow
Rounding

Mantissa overflow
Realignment