Features of 8051

8 bit ALU. 16 bit PC and DPTR. 8 bit stack pointer and 8 bit PSW. 4K internal ROM (program memory) 128 bytes of Internal RAM. 32 bits arranged as four, 8 bit ports P0-P3. Two 16 bit timer/counters, T0 & T1. Full duplex serial Port. Two External and three internal interrupt sources. 0-12 MHz clock. 40 pin DIP package. Works in Power Down CISC processor

Block Diagram of 8051.

Pin details of 8051

P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST (RXD) P3.0
(Serial) 1 40

Vcc P0.0(AD0) P0.1(AD1) P0.2(AD2) P0.3(AD3) P0.4(AD4) P0.5(AD5) P0.6(AD6) P0.7(AD7) EA/VPP ALE/PROG PSEN P2.7(A15) P2.6(A14) P2.5(A13) P2.4(A12) P2.3(A11) P2.2(A10) P2.1(A9) P2.0(A8)
Ext Memory Address Ext Memory Access Control Ext Memory Address

39

38

37

36

8051

35

34

33

32

10

31

(TXD) P3.1 (INT0) P3.2

interrupt

11

30

12

29

(INT1) P3.3 (T0) P3.4

Timer

13

28

14

27

(T1) P3.5 (WR) P3.6

Ex M W/R

15

26

16

25

(RD) P3.7 XTAL 2

clock

17

24

18

23

XTAL 1 GND

19

22

20

21

PROGRAM STATUS WORD (PSW)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CY AC FO RS1 RS0 OV UD P
Symbol Function CY Carry flag AC Auxiliary Carry flag (For BCD Operations)
F0 Flag 0 (Available to the user for General Purpose) Register bank select: RS1 RS0 Working Register Bank and Address 0 0 Bank0 (D:0x00 - D:0x07) 0 1 Bank1 (D:0x08 - D:0x0F) 1 0 Bank2 (D:0x10 - D:0x17) 1 1 Bank3 (D:0x18H - D:0x1F) Overflow flag User definable flag Parity flag

RS1, RS0

0V UD P

Addressing modes

Immediate Addressing
Direct Addressing Indirect Addressing Indexed Addressing

MOV A,#20h
MOV A,30h MOV A,@R0 JMP @A+DPTR

Hardware Structure of I/O Pin

Read latch
TB2

Vcc
Load(L1)

Data bus line Write to latch

P1.X
Clk Q

P1.X pin M1

TB1 Read pin

Writing 1 to Output Pin P1.X

Read latch TB2 Load(L1) Vcc

1. write a 1 to the pin

Internal CPU bus Write to latch
D Q

2. output pin is Vcc

P1.X pin

1 0
M1

P1.X
Clk Q

output 1

TB1 Read pin

Writing 0 to Output Pin P1.X

Read latch TB2 Load(L1) Vcc

1. write a 0 to the pin

Internal CPU bus Write to latch
D Q

2. output pin is ground

P1.X pin

0 1
M1

P1.X
Clk Q

output 0

TB1 Read pin

Reading High at Input Pin

Read latch TB2 Load(L1) 1 P1.X pin Vcc 1. MOV A,P1 external pin=High

Internal CPU bus Write to latch

Q
P1.X 0 M1

Clk

TB1 Read pin 2. Read pin=1 Read latch=0 Write to latch=1

Reading Low at Input Pin

Read latch TB2 Load(L1) 0 Vcc 1. MOV A,P1 external pin=Low

Internal CPU bus Write to latch

Q
P1.X 0 M1

P1.X pin

Clk

TB1 Read pin 2. Read pin=1 Read latch=0 Write to latch=1

Timer 0 /1

C/T =0

C/T =1

11

Timer Modes
Timer Mode 0 : 8-bit counter (TH0 or TH1). 5-bit prescaler (TL0 or TL1). Timer Mode 1 : 16-bit counter (TH0 or TH1:TL0 or TL1). Timer Mode 2 : 8-bit auto-reload. Counter in TL0 or TL1. Reload value in TH0 or TH1. Provides a periodic flag or interrupt. Timer Mode 3 : TH0 and TL0 function as two independent 8 bit units

TMOD : Counter/Timer Mode Register

GATE C/T M1 M0 GATE C/T M1 M0

Timer 1

Timer 0

GATE : Permits INTx pin to enable/disable counter. C/T : Set for counter operation, reset for timer operation. M1, M0 00 : Emulate 8048 counter/timer (13-bits). 01 :16-bit counter/timer. 10 : 8-bit auto-reload mode 11 :Timer 0 = two 8-bit timers. Timer 1 = Counting disabled. Timing function allowed. (Can be used as Baud Rate generator). M1

TCON : Counter/Timer Control Register

-TF1, TF0 : Overflow flags for Timer 1 and Timer 0.

-TR1, TR0 : Run control bits for Timer 1 and Timer 0. Set to run, reset to hold.
- IE1, IE0 : Edge flag for external interrupts 1 and 0. * Set by interrupt edge, cleared when interrupt is processed. - IT1, IT0 : Type bit for external interrupts. * Set for falling edge interrupts, reset for 0 level interrupts. * = not related to counter/timer operation.