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Instruction set architectures

Unit 1
sumit

Instruction set architecture
Programmers or a users view of mp.
Contains the set of all assembly language
instructions that it can execute.
Needs to know the accessible registers, their
sizes, and specific instructions which use these
registers.
Interrupts
Information necessary to interact with
memory.
Instruction Set Architecture
Defines any aspects of the processor that an assembly
language programmer needs to know, in order to write a
correct program
Specifies:
The registers accessible to the programmer, their size and the
instructions in the instructions set that can use each register
Information necessary to interact with the memory
Certain microprocessors require instructions to start only at specific
memory locations; this alignment of the instructions will be part of the
instruction architecture
How microprocessor reacts to interrupts
Some microprocessors have interrupts, that cause the processor to stop
what is doing and perform some other preprogrammed functions (interrupt
routines)
Levels of Programming languages
Machine level languages binary level lang
Assembly level languages platform
dependent, have to be assembled and it is
unique.
High Level languages have to be compiled
which is not unique
Instruction Types
Data transfer instructions data unchanged
1. Load data from mem 2.Store data into mem
3. Move data within mp 4. Input data 5. Output data
6. Movement of blocks of data
Data operation instructions
Arithmetic, floating point, logical and shift instructions
Program control instructions
Jumps, call, interrupts, halt
Instruction types (review)
Data Transfer Instructions
operations that move data from one place to another
These instructions dont actually modify the data, they just copy it
to the destination
Data Operation Instructions
Unlike the data transfer instructions, the data operation
instructions do modify their data values
They typically perform some operation using one or two data
values (operands) and store the result
Program Control Instructions
Jump or branch instructions used to go in another part of the
program; the jumps can be absolute (always taken) or conditional
(taken only if some condition is met)
Specific instructions that can generate interrupts (software
interrupts)

Data types (1)
A microprocessor has to operate with multiple data
types;
the designer has to include different instructions to
perform the same operation on different data types
Numeric data representation:
Integer representation
Unsigned representation: n bit value range from 2
n
-1 to 0
Signed representation: n bit value range from -2
n-1
to 2
n -1
-1
Floating point representation
A processor may have special registers and instructions for
floating point data
Data type (2)
Boolean data:
Non zero value is used to represent TRUE and zero
value is used to represent FALSE
Character data
Stored as binary value, encoded using ASCII,
UNICODE, etc
A microprocessor may have instructions to
concatenate strings of characters, replace certain
characters in a string, etc..
Some instruction sets do include instructions to
directly manipulate character data
Instruction formats (1)
An instruction is represented as a binary value with
specific format, called the instruction code
It is made out of different groups of bits, with
different significations:
Opcode represents the operation to be performed (it is
the instruction identifier)
Operands one, two or three represent the operands of
the operation to be performed
A microprocessor can have one format for all the
instructions or can have several different formats
An instruction is represented by a single instruction
code
Morris mano Computer Registers
Register Number Register Register
symbol of bits name Function-----------------------
DR 16 Data register Holds memory operands
AR 12 Address register Holds address for memory
AC 16 Accumulator Processor register
IR 16 Instruction register Holds instruction code
PC 12 Program counter Holds address of instruction
TR 16 Temporary register Holds temporary data
INPR 8 Input register Holds input character
OUTR 8 Output register Holds output character

5-2 Computer Registers
Data Register(DR) : hold the operand(Data) read from memory

Accumulator Register(AC) : general purpose processing register

Instruction Register(IR) : hold the instruction read from
memory

Temporary Register(TR) : hold a temporary data during
processing

Address Register(AR) : hold a memory address, 12 bit width

5-2 Computer Registers
Program Counter(PC) :
hold the address of the next instruction to be read from
memory after the current instruction is executed
Instruction words are read and executed in sequence
unless a branch instruction is encountered
A branch instruction calls for a transfer to a
nonconsecutive instruction in the program
The address part of a branch instruction is transferred to
PC to become the address of the next instruction
To read instruction, memory read cycle is initiated, and
PC is incremented by one(next instruction fetch)

PROCESSOR REGISTERS
Instruction codes
A processor has many registers to hold instructions,
addresses, data, etc
The processor has a register, the Program Counter (PC) that
holds the memory address of the next instruction to get
Since the memory in the Basic Computer only has 4096 locations, the PC
only needs 12 bits
In a direct or indirect addressing, the processor needs to keep
track of what locations in memory it is addressing: The
Address Register (AR) is used for this
The AR is a 12 bit register in the Basic Computer
When an operand is found, using either direct or indirect
addressing, it is placed in the Data Register (DR). The
processor then uses this value as data for its operation
The Basic Computer has a single general purpose register
the Accumulator (AC)
PROCESSOR REGISTERS
Instruction codes
The significance of a general purpose register is that it can be
referred to in instructions
e.g. load AC with the contents of a specific memory location; store the
contents of AC into a specified memory location
Often a processor will need a scratch register to store
intermediate results or other temporary data; in the Basic
Computer this is the Temporary Register (TR)
The Basic Computer uses a very simple model of input/output
(I/O) operations
Input devices are considered to send 8 bits of character data to the processor
The processor can send 8 bits of character data to output devices
The Input Register (INPR) holds an 8 bit character gotten from an
input device
The Output Register (OUTR) holds an 8 bit character to be send
to an output device
BASIC COMPUTER REGISTERS
List of BC Registers
DR 16 Data Register Holds memory operand
AR 12 Address Register Holds address for memory
AC 16 Accumulator Processor register
IR 16 Instruction Register Holds instruction code
PC 12 Program Counter Holds address of instruction
TR 16 Temporary Register Holds temporary data
INPR 8 Input Register Holds input character
OUTR 8 Output Register Holds output character

Registers
Registers in the Basic Computer
11 0
PC
15 0
IR
15 0
TR
7 0
OUTR
15 0
DR
15 0
AC
11 0
AR
INPR
0 7
Memory



4096 x 16
CPU
Instruction formats (2)
The most common fields in instruction formats are:
1. Mode field: Specifies the way the effective address is determined
2. Operation code: Specifies the operations to be performed.
3. Address field: Designates a memory address or a processor
register
Mode Opcode

Address
8.4 Instruction Formats
8.4 Instruction Formats
Zero address instruction: Stack is used. Arithmetic operation
pops two operands from the stack and pushes the result.

One address instructions: AC and memory. Since the
accumulator always provides one operand, only one memory
address needs to be specified.

Two address instructions: Two address registers or two
memory locations are specified, one for the final result.

Three address instructions: Three address registers or
memory locations are specified, one for the final result.
It is also called general address organization.

Zero address instructions


Instruction: ADD
Push and pop operations need to specify one address involved in
data transfer.

Instruction: POP X
Evaluate X = ( A + B ) * ( C + D )
Stack-organized computer does not use an address field for
the instructions ADD, and MUL
PUSH, and POP instructions need an address field to
specify the operand

Zero address instructions
PUSH A
PUSH B
ADD
PUSH C
PUSH D
ADD
MUL
POP X
TOS X
B A D C TOS
D C TOS
D TOS
C TOS
B A TOS
B TOS
A TOS

+ - +
+

) ( ) (
) (
) (
Advantages: No memory addresses needed during the operation.
Disadvantages: results in longer program codes.
One address instructions
One address can be a register name or memory
address.
SINGLE ACCUMULATOR ORGANIZATION

Since the accumulator always provides one operands,
only one memory address needs to be specified.
Instruction: ADD X
Microoperation: AC AC + M[X]

One address instructions
LOAD A
ADD B
STORE T AC T M
B M AC AC
A M AC

] [
] [
] [
All operations are done between the AC register and memory operand

Advantages: fewer bits are needed to specify the address.
Disadvantages: results in writing long programs.
Two address instructions
Assumes that the destination address
is the same as that of the first operand.
Can be a memory address or a register
name.

Instruction: ADD R1, R2
Microoperation: R1 R1 + R2

Two address instructions
MOV R1, A
MOV R2, B
ADD R1, R2
MOV X, R1
1 ] [
2 1 1
] [ 2
] [ 1
R x M
R R R
B M R
A M R

most common in commercial computers



Each address fields specify either a processor register or a
memory operand
Advantages: results in writing medium size programs
Disadvantages: more bits are needed to specify two addresses.
Three address organization
GENERAL REGISTER ORGANIZATION

Three address instructions: Memory addresses for
the two operands and one destination need to be specified.
Instruction: ADD R1, R2, R3
Microoperation: R1 R2 + R3



Advantages: results in writing short programs
Disadvantages: more bits are needed to specify three addresses.

ADD R1, R2, R3
3 2 1 R R R +
EXAMPLE: Show how can the following operation be
performed using:
a- three address instruction
b- two address instruction
c- one address instruction
d- zero address instruction
X = (A + B) * (C + D)
a-Three-address instructions
(general register organization)

ADD R1, A, B
R1 M[A] + M[B]
ADD R2, C, D
R2 M[C] + M[D]
MUL X, R1, R2
M[X] R1 * R2
b-Two-address instructions
(general register organization)
MOV R1, A
R1 M[A]
ADD R1, B
R1 R1 + M[B]
MOV R2, C
R2 M[C]
ADD R2, D
R2 R2 + M[D]
MOV X, R2
M[X] R2
MUL X, R1
M[X] R1 * M[X]
c- One-address instructions
LOAD A
AC M[A]
ADD B
AC AC + M[B]
STORE T
M[T ] AC
LOAD C
AC M[C]
ADD D
AC AC + M[D]
MUL T
AC AC * M[T ]
STORE X
M[X] AC Store
d- Zero-address instructions
(stack organization)
Push value
Else If operator is encountered: Pop, pop, operation,
push
Pop operand pop another operand then perform an
operation and push the result back into the stack.

PUSH A TOS A Push
PUSH B TOS B
ADD TOS (A+B)
PUSH C TOS C
PUSH D TOS D
ADD TOS (C+D)
MUL TOS (C+D)*(A+B)
POP X M[X] TOS
(*TOS stands for top of stack).
Pop, pop, operation, push
Instruction formats (3)
Fewer operands translates into more instructions to
accomplish the same task
The hardware required to implement the microprocessor
becomes less complex with fewer operands;
microprocessors whose instructions specify a fewer
number of operands can execute instructions more quickly
than those that specify more operands
The example was simplified to show the difference
between three, two, one and zero operands instructions; in
practice, the instructions require many more bits than used
in these examples; an operand field may specify an
arbitrary memory address, rather than one of the four
registers; this could require 16, 32 or even more bits per
operand

CPU Elements
Program Counter or PC contains the address of the
instruction that will be executed next
Stack a data structure of last in first out type
A stack is described by a special register stack pointer
It can be used explicitly to save/restore data
It is used implicitly by procedure call instructions (if
available in the instruction set)
IR instruction register that holds the current
instruction being processed by the microprocessor;
it is not exposed through the instruction set
architecture; just an organization element
Addressing Modes
An architecture addressing mode is the set of syntaxes
and methods that instructions use to specify a memory
address
For operands or results
As a target address for a branch instruction
When a microprocessor accesses memory, to either read
or write data, it must specify the memory address it
needs to access
Several addressing modes to generate this address are
known, a microprocessor instruction set architecture
may contain some or all of those modes, deepening on
its design
In the following examples we will use the LDAC
instruction (loads data from a memory location into the
AC - accumulator - microprocessor register)
Direct mode
Instruction includes the A memory address
LDAC 5 accesses memory location 5, reads the data (10)
and stores the data in the microprocessors accumulator
This mode is usually used to load variables and operands
into the CPU
Address A Opcode
Instruction Memory
Operand
Indirect mode
Starts like the direct mode, but it makes an
extra memory access. The address
specified in the instruction is not the
address of the operand, it is the address of
a memory location that contains the
address of the operand.
LDAC @5 or LDAC (5), first retrieves the
content of memory location 5, say 10, and
then CPU goes to location 10, reads the
content (20) of that location and loads the
data into the CPU
Address A Opcode
Instruction Memory
Pointer to operand
operand
Register direct mode
It specifies a register instead a memory address
LDAC R if register R contains an value 5, then the value 5
is copied into the CPUs accumulator
No memory access
Very fast execution
Very limited address space
Register Address R Opcode
Instruction
Registers
Operand
Register indirect mode
LDAC @R or LDAC (R) the register contains the address of
the operand in the memory
Register R (selected by the operand), contains value 5
which represents the address of the operand in the
memory (10)
One fewer memory access than indirect addressing
Register Address R Opcode
Instruction Memory
Operand
Registers
Pointer to
operand
Immediate mode
The operand is not specifying an address, it is the
actual data to be used
LDAC #5 loads actually value 5 into the CPUs
accumulator
No memory reference to fetch data
Fast, no memory access to bring the operand

Implicit addressing mode
Doesnt explicitly specify an operand
The instruction implicitly specifies the operand
because always applies to a specific register
This is not used for load instructions
As an example, consider an instruction CLAC, that is
clearing the content of the accumulator in a
processor and it is always referring to the
accumulator
This mode is used also in CPUs that do use a stack
to store data; they dont specify an operand
because it is implicit that the operand must come
from the stack
Displacement addressing mode
Effective Address = A + (content of R)
Address field hold two values
A = base value
R = register that holds displacement
or vice versa

Register R
Opcode
Instruction
Memory
Operand
Pointer to
Operand
Registers
Address A
+
Relative addressing mode
It is a particular case of the displacement addressing,
where the register is the program counter; the supplied
operand is an offset; Effective Address = A + (PC)
The offset is added to the content of the CPUs program
counter register to generate the required address
The program counter contains the address of next
instruction to be executed, so the same relative instruction
will produce different addresses at different locations in the
program
Consider that the relative instruction LDAC $5 is located at
memory address 10 and it takes two memory locations; the
next instruction is at location 12, so the operand is actually
located at (12 +5) 17; the instruction loads the operand at
address 17 and stores it in the CPUs accumulator
This mode is useful for short jumps and relocatable code

Indexed addressing mode
Works like relative addressing mode; instead
adding the A to the content of program counter
(PC), the A is added to the content of an index
register
If the index register contains value 10, then the
instruction LDAC 5(X) reads data from memory at
location (5+10) 15 and stores it in the
accumulator
Good for accessing arrays
Effective Address = A + IndexReg
R++

Based addressing mode
Works the same with indexed addressing
mode, except that the index register is
replaced by a base address register
A holds displacement
R holds pointer to base address
R may be explicit or implicit
e.g. segment registers in 80x86
Addressing Modes Summary
47
Central Processing Unit
Addressing modes
The addressing mode specifies a rule for interpreting or
modifying the address field of the instruction before the
operand is actually executed.
Computers use addressing mode techniques for the purpose
of accommodating one of the following provisions:
1. To give programming versatilities to the user to be more
flexible.
2. To reduce the number of bits in the addressing field of the
instruction.
In some some computers, the addressing mode of the
instruction is specified with distinct binary code.
Instruction format with mode field
Address Mode Opcode
48
Central Processing Unit
Addressing modes
Other computers use a single binary for operation &
Address mode.
The mode field is used to locate the operand.
Address field may designate a memory address or a
processor register.
There are 2 modes that need no address field at all
(Implied & immediate modes).
49
Central Processing Unit
Addressing modes
The most well known addressing mode then are:
Implied mode.
Immediate mode
Register mode
Register Indirect mode
Auto-increment or Auto-decrement mode
Direct Mode
Indirect Mode
Relative Address Mode
Index Addressing Mode

50
Central Processing Unit
Addressing modes
Numerical Example
Address=500
Next Instruction
450
700
800
900
325
300
Load to AC Mode
Memory
500
Address
201
202
399
400
702
600
200
800
PC=200 R1=400
XR=100 AC
Addressing mode eff. Add Content of AC
-----------------------------------------------------------
Direct Address 500 800
Immediate operand 201 500
Indirect Address 800 300
Relative Address 702 (PC=PC+2) 325
Indexes Address 600 (XR+500) 900
Register --- 400
Register Indirect 400 700
Auto-increment 400 700
Auto-decrement 399 450
Tabular list
51
Central Processing Unit
Addressing modes
Different ways in which the address of an operand in specified in
an instruction is referred to as addressing modes.
Register mode
Operand is the contents of a processor register.
Address of the register is given in the instruction.
E.g. Clear R1
Absolute mode
Operand is in a memory location.
Address of the memory location is given explicitly in the
instruction.
E.g. Clear A
Also called as Direct mode in some assembly languages
Register and absolute modes can be used to represent variables
52
Central Processing Unit
Addressing modes
Immediate mode

Operand is given explicitly in the instruction.
E.g. Move #200, R0
Can be used to represent constants.
Register, Absolute and Immediate modes contained either the
address of the operand or the operand itself.
Some instructions provide information from which the memory
address of the operand can be determined
That is, they provide the Effective Address of the operand.
They do not provide the operand or the address of the
operand explicitly.
Different ways in which Effective Address of the operand can
be generated.
53
Central Processing Unit
Addressing modes
Indirect Mode
Effective Address of the operand is the contents of a register or
a memory location whose address appears in the instruction.
R1
Add (R1),R0 Add (A),R0
Register
B B
Operand
memory
Main
A B Operand B
Register R1 contains Address B
Address B has the operand
Address A contains Address B
Address B has the operand
R1 and A are called pointers
54
Central Processing Unit
Addressing modes
Indexing Mode
Effective Address of the operand is generated by adding a constant
value to the contents of the register
R1
Add 20(R1),R0
1000
1020
offset = 20
1000
Operand
Operand is at address 1020
Register R1 contains 1000
Offset 20 is added to the
contents of R1 to generate the
address 20
Contents of R1 do not change in the
process of generating the address
R1 is called as an index register
What address would be generated
by Add 1000(R1), R0 if R1 had 20?
55
Central Processing Unit
Addressing modes
Relative mode

Effective Address of the operand is generated by adding a
constant value to the contents of the Program Counter (PC).
Variation of the Indexing Mode, where the index register is
the PC
instead of a general purpose register.
When the instruction is being executed, the PC holds the
address of the next instruction in the program.
Useful for specifying target addresses in branch instructions.

Addressed location is relative to the PC, this is called Relative
Mode
56
Central Processing Unit
Addressing modes
Autoincrement mode:
Effective address of the operand is the contents of a register specified
in the instruction.
After accessing the operand, the contents of this register are
automatically incremented to point to the next consecutive memory
location.
(R1)+
Autodecrement mode
Effective address of the operand is the contents of a register specified
in the instruction.
Before accessing the operand, the contents of this register are
automatically decremented to point to the previous consecutive memory
location.
-(R1)
Autoincrement and Autodecrement modes are useful for
implementing Last-In-First-Out data structures
57
Instruction set architecture design (1)
What is the processor able to do
General Purpose Processor
If will be general purpose, then the ISA should be pretty rich to perform a variety of
tasks
Specialized Processor
the ISA should perform a specific set of tasks, well known in advance
The instruction set has to have all the instructions to perform its
required tasks completeness
What addressing modes?
Multimedia instructions?
RISC or CISC? Fixed length encoding or variable length encoding?
The instruction set should be orthogonal (CISC specific)
The choice of addressing mode is independent from the choice of instruction.
Any instruction that references memory should be able to use any
implemented addressing mode
an orthogonal instruction set allows a programmer to remember fewer
instructions ("ADD", "SUBTRACT", "MULTIPLY", "DIVIDE", etc.) and a set of
three to ten addressing modes ("FROM REGISTER 0", "FROM REGISTER 1",
"FROM MEMORY", etc)
Instruction set architecture design (2)
Does the microprocessor have to be backwards compatible
with other microprocessors?
What type of data and sizes of data will the microprocessor
deal with??
If floating point operation is needed, then the design must include
instructions that will work on floating point data; also registers to
store floating point data are needed;
Are interrupts needed?
If needed, the design should include the registers and instructions
to deal with interrupts
Are conditional instructions needed?
Usually, the conditions are stored in 1-bit registers that store the
value of various conditions; typical flags include the zero flag (set
1 when an operation produces a result of zero), sign flag (set to
one when an instruction produces an negative result), etc
Instruction Set Architecture (ISA)
- Memory Model
- Registers
- Instruction set
Memory Model
- This microprocessor can access 64K ( = 2
16
)
bytes of memory

- Each byte has 8 bits, therefore it can access
64K 8 bits of memory

- 64K of memory is the maximum limit,
sometimes a system based on this CPU can
have less memory

- Use memory to map I/O
Same instructions to use for accessing I/O
devices and memory
Registers
Accumulator (AC), is an 8-bit general purpose
register

Register R, is an 8-bit general purpose register.
It supplies the second operand and also it can be
use to store data that the AC will soon need to
access.

Flag Z, is an 1-bit zero flag. Z is set to 1 or 0
whenever an instruction is execute

Other registers that cannot be directly accessed
by programmer

Instruction Set
- Data movement instructions

- Data operation instructions

- Program control instructions
Data movement instruction for the
Relatively Simple CPU
Instruction Operation
NOP No operation
LDAC I AC = M[I]
STAC I M[I] = AC
MVAC R = AC
MOVR AC = R
AC accumulator register
R general purpose register
I/M[I] 16-bit memory address
NOP -- performs no operation
LDAC -- loads data from memory and stores
it in the AC
STAC -- copies data from AC to memory
location I
MVAC -- copies data in AC to register R
MOVR -- copies data from R to AC
Data operation instruction for the
Relatively Simple CPU
Instruction Operation
ADD AC = AC + R, If (AC + R = 0) Then Z = 1 Else Z = 0
SUB AC = AC - R, If (AC - R = 0) Then Z = 1 Else Z = 0
INAC AC = AC + 1, If (AC + 1 = 0) Then Z = 1 Else Z = 0
CLAC AC = 0, Z = 1
AND AC = AC . R, If (AC . R = 0) Then Z = 1 Else Z = 0
OR AC = AC v R, If (AC v R = 0) Then Z = 1 Else Z = 0
XOR AC = AC R, If (AC R = 0) Then Z = 1 Else Z = 0
NOT AC = AC', If (AC' = 0) Then Z = 1 Else Z = 0
AC accumulator register R general purpose register
Z zero flag
Program control instruction for the
Relatively Simple CPU
Instruction Operation
JUMP I GOTO I
JMPZ I If (Z = 1) Then GOTO I
JPNZ I If (Z = 0) Then GOTO I
Z zero flag
I -- 16-bit memory address
Note:
Each instruction is having an 8-bit instruction
code.
LDAC, STAC, JUMP, JUMPZ, and JPNZ
instructions all require a 16-bit memory
address, represented by I/M[I]. These
instructions each require 3 bytes in
memory.

Instruction formats for the Relatively Simple CPU
Instruction code
Low-order 8 bits of
I
High-order 8 bits of
I
byte 1
byte 2
byte 3
Example:
25: JUMP 1234 H
instruction stored in memory:
25th byte 25: 0000 0101 (JUMP)
26th byte 26: 0011 0100 (34H)
27th byte 27: 0001 0010 (12H)
H -- in hexadecimal format
The Algorithm of the program
1: total = 0, i = 0
2: i = i + 1
3: total = total + i
4: IF i = n THEN GOTO 2

What exactly this algorithm doing is: 1+ 2 + + (n 1) + n
Example program using Relatively Simple CPU coding
The Relatively Simple CPU coding of the program
CLAC
STAC total
STAC i
Loop: LDAC i
INAC
STAC i
MVAC
LDAC total
ADD
STAC total
LDAC n
SUB
JPNZ Loop
total = 0, i = 0
i = i +1
total = total +1
IF i = n THEN GOTO Loop
8085 Memory Model
- This microprocessor is a complete 8-bit
parallel Central Processing Unit (CPU).

- Each byte has 8 bits

- Isolated I/O, input and output devices are
treated as being separate from memory.
Different instructions access memory and
I/O devices
8085 Register Set
Accumulator A, is an 8-bit register.
Register B, C, D, E, H, and L, are six 8-bit
general purpose register. These registers can be
accessed individually, or can be accessed in
pairs.
Pairs are not arbitrary; BC are a pair (16- bit),
as are DE, and HL
Register HL is used to point to a memory
location.
Stack pointer, SP, is an 16-bit register, which
contains the address of the top of the stack.
The sign flag, S, indicates the sign of a value
calculated by an arithmetic or logical
instruction.
The zero flag, Z, is set to 1 if an arithmetic or
logical operation produces a result of 0;
otherwise set to 0.
The parity flag, P, is set to 1 if the result of an
arithmetic or logical operation has an even
number of 1s; otherwise it is set to 0.
The carry flag, CY, is set when an arithmetic
operation generates a carry out.
The auxiliary carry flag, AC, very similar to CY,
but it denotes a carry from the lower half of the
result to the upper half.
The interrupt mask, IM, used to enable and
disable interrupts, and to check for pending
interrupts
Instruction Set
- Data movement instructions

- Data operation instructions

- Program control instructions
Data movement instruction for the 8085 microprocessor
Instruction Operation
MOV r1, r2 r1 = r2
LDA I A = M[I]
STA I M[I] = A
PUSH rp Stack = rp (rp = SP)
PUSH PSW Stack = A, flag register
POP rp rp = Stack (rp = SP)
POP PSW A, flag register = Stack
IN n A = input port n
OUT n Output port n =A
r, r1, r2 any 8-bits register I / M[I] memory location
rp register pair BC, DE, HL, SP(Stack pointer)
n 8-bit address or data value
Data operation instruction for the 8085 microprocessor
Instruction Operation Flags
ADD r A = A + r All
ADD M A = A + M[HL] All
INR r r = r + 1 Not CY
IN M M[HL] = M[HL] + 1 Not CY
DCR n r = r - 1 Not CY
DCR M M[HL] = M[HL] - 1 Not CY
XRA M A = A M[HL] All
CMP r Compare A and r All
CMA A = A' None
CY carry flag
Program control instruction for the
8085 microprocessor
Instruction Operation
JUMP I GOTO I
Jcond I If condition is true then GOTO I
CALL I Call subroutine at I
Ccond I If condition is true then call subroutine at I
RET Return from subroutine
Rcond If condition is true then return from subroutine
cond conditional instructions
NZ (Z = 0) Z (Z = 1) P (S = 0) N (S = 1)
PO (P = 0) PE (P = 1) NC (CY = 0) C (CY = 1)
Z zero flag, S sign flag, P parity flag, C carry flag
Note:
Each instruction is having an 8-bit instruction
code.
Some instructions have fields to specify
registers, while others are fixed.

Example:
25: MOV r1, r2
instruction stored in memory:
25th byte 25: 0000 0001 (MOV)
26th byte 26: xxxx xxxx (specifies r1)
27th byte 27: yyyy yyyy (specifies r2)
Instruction code
Low-order 8 bits
High-order 8 bits
byte 1
byte 2
byte 3
Three-byte
Example:
25: LXI rp, I
instruction stored in memory:
25th byte 25: 00rp 0001 (LXI rp)
26th byte 26: xxxx xxxx (low-order memory)
27th byte 27: yyyy yyyy (high-order memory)
Example:
25: LXI rp, I
instruction stored in memory:
25th byte 25: 00rp 0001 (LXI rp)
26th byte 26: xxxx xxxx (low-order memory)
27th byte 27: yyyy yyyy (high-order memory)
Specifies rp
The Algorithm of the program
1: total = 0, i = 0
2: i = i + 1
3: total = total + i
4: IF i = n THEN GOTO 2
n + (n - 1) + + 1
The 8085 coding of the program
LDA n
MOV B, A
XRA A
Loop: ADD B
DCR B
JNZ Loop
STA total
Example program using 8085 microprocessor coding
i = n
sum = A A = 0
sum = sum + i
i = i - 1
IF i = 0 THEN GOTO Loop
total = sum
Add ten numbers stored in memory at
1001H and store result at 1000H
Ldac n
Fibonacci series with 8085

Fibonacci series with relatively
simple instruction set


Analyzing the 8085 ISA

- The 8085 CPUs instruction set is more
complete than that of the Relatively
Simple CPU. More suitable for consumer
appliance.

- Too limited to run anything as complex
as personal computer

Advantages of the 8085s ISA vs.
Relative Simple CPU

- It has the ability to use subroutines

- It can incorporate interrupts, and it has
everything the programmer needs in
order to process interrupts.

- The register set for the 8085 is mostly
sufficient, thus less coding apply which
will improve task completion.
- The instruction set is fairly orthogonal.
E.g. no clear accumulator instruction


Disadvantages of the 8085s ISA

- Like the Relatively Simple CPU, it
cannot easily process floating point data.


Summary of ISA

1. The ISA specifies
a. an instruction set that the CPU can process
b. its user accessible registers
c. how it interacts with memory

2. The ISA does not specify how the CPU is designed, but it specifies
what it must be able to do.

3. The ISA is concerned only with the machine language of a
microprocessor because CPU only executes machine language
program, not any kind of high-level program.


4. When designing an ISA, an important goal is
completeness:
a. instruction set should include the instructions
needed to program all desired tasks.
b. instruction should be orthogonal, minimizing
overlap, reducing the digital logic without
reducing its capabilities within the CPU.
c. CPU should includes enough registers to minimize
memory accesses, and improve performance.

5. An ISA should specifies the types of data the instruction set
to process.



6. An ISA should specifies the addressing modes
each instruction can use

7. An ISA should specifies the format for each
instruction

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